diff mbox series

[13/20] s390: myr operand R1 must be a FP register pair

Message ID 20260930081834.2948939-35-jremus@linux.ibm.com
State New
Headers
Series s390: Instruction cleanups |

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Context Check Description
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Commit Message

Jens Remus Sept. 30, 2026, 8:18 a.m. UTC 
  myr R1,R3,R2 operand R1 must designate a valid floating-point-
register pair; otherwise, a specification exception is recognized.
[1, 2]

Correct the instruction format RRF_FE0FF accordingly, so that the
assembler warns, if an invalid register number is coded.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-04, IBM z9,
     https://publibfp.dhe.ibm.com/epubs/pdf/a2278324.pdf

[2]: IBM z/Architecture Principles of Operation, SA22-7832-14, IBM z17,
     https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf

opcodes/
	* s390-opc.c (INSTR_RRF_FE0FF): Define R1 as FPR pair operand.

gas/testsuite/
	* gas/s390/zarch-z9-109.d (myr): Specify a valid FPR pair.
	* gas/s390/zarch-z9-109.s (myr): Likewise.
	* gas/s390/zarch-z9-109-err.l (myr): Specify an invalid FPR
	pair.
	* gas/s390/zarch-z9-109-err.s (myr): Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 gas/testsuite/gas/s390/zarch-z9-109-err.l | 1 +
 gas/testsuite/gas/s390/zarch-z9-109-err.s | 1 +
 gas/testsuite/gas/s390/zarch-z9-109.d     | 2 +-
 gas/testsuite/gas/s390/zarch-z9-109.s     | 2 +-
 opcodes/s390-opc.c                        | 2 +-
 5 files changed, 5 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/gas/testsuite/gas/s390/zarch-z9-109-err.l b/gas/testsuite/gas/s390/zarch-z9-109-err.l
index b5460b65046d..5b67ad46f76b 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109-err.l
+++ b/gas/testsuite/gas/s390/zarch-z9-109-err.l
@@ -1,2 +1,3 @@ 
 .*: Assembler messages:
 .*:3: Error: operand 1: odd numbered general purpose register specified as register pair
+.*:4: Error: operand 1: invalid floating-point register \(FPR\) pair \(valid FPR pair operands are 0, 1, 4, 5, 8, 9, 12 or 13\)
diff --git a/gas/testsuite/gas/s390/zarch-z9-109-err.s b/gas/testsuite/gas/s390/zarch-z9-109-err.s
index 6a94cb0c0e76..569326c04d61 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109-err.s
+++ b/gas/testsuite/gas/s390/zarch-z9-109-err.s
@@ -1,3 +1,4 @@ 
 .text
 foo:
 	flogr	%r7,%r8
+	myr	%f6,%f9,%f5
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d
index a192bd2c7e57..97fd239230e6 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.d
+++ b/gas/testsuite/gas/s390/zarch-z9-109.d
@@ -57,7 +57,7 @@  Disassembly of section .text:
 .*:	b2 a7 00 68 [	 ]*cutfu	%r6,%r8
 .*:	b9 b0 f0 68 [	 ]*cu14	%r6,%r8,15
 .*:	b9 b0 00 68 [	 ]*cu14	%r6,%r8
-.*:	b3 3b 60 95 [	 ]*myr	%f6,%f9,%f5
+.*:	b3 3b 50 96 [	 ]*myr	%f5,%f9,%f6
 .*:	b3 3d 60 95 [	 ]*myhr	%f6,%f9,%f5
 .*:	b3 39 60 95 [	 ]*mylr	%f6,%f9,%f5
 .*:	ed 95 af ff 50 3b [	 ]*my	%f5,%f9,4095\(%r5,%r10\)
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s
index 22dca84fd32e..0081d997cc42 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.s
+++ b/gas/testsuite/gas/s390/zarch-z9-109.s
@@ -51,7 +51,7 @@  foo:
 	cu12	%r6,%r8
 	cu14	%r6,%r8,15
 	cu14	%r6,%r8
-	myr	%f6,%f9,%f5
+	myr	%f5,%f9,%f6
 	myhr	%f6,%f9,%f5
 	mylr	%f6,%f9,%f5
 	my	%f5,%f9,4095(%r5,%r10)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 3d5778e3a79d..86cd562807ca 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -360,7 +360,7 @@  unused_s390_operands_static_asserts (void)
 #define INSTR_RRE_FR       4, { F_24,R_28,0,0,0,0 }              /* e.g. ldgr  */
 #define INSTR_RRE_FER      4, { FE_24,R_28,0,0,0,0 }             /* e.g. cxfbr */
 #define INSTR_RRF_F0FF     4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
-#define INSTR_RRF_FE0FF    4, { F_16,F_24,F_28,0,0,0 }           /* e.g. myr   */
+#define INSTR_RRF_FE0FF    4, { FE_16,F_24,F_28,0,0,0 }          /* e.g. myr   */
 #define INSTR_RRF_F0FF2    4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
 #define INSTR_RRF_F0FR     4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
 #define INSTR_RRF_FE0FER   4, { FE_24,FE_16,R_28,0,0,0 }         /* e.g. iextr */