[08/20] s390: mvcl operands R1 and R2 must be register pairs

Message ID 20260930081834.2948939-30-jremus@linux.ibm.com
State New
Headers
Series s390: Instruction cleanups |

Commit Message

Jens Remus Sept. 30, 2026, 8:18 a.m. UTC
  mvcl R1,R2 operands R1 and R2 each designate an even-odd pair of
general registers and must designate an even-numbered register;
otherwise, a specification exception is recognized. [1, 2]

[1]: IBM ESA/390 Principles of Operation, SA22-7201-07, z900,
     https://publibfp.dhe.ibm.com/epubs/pdf/dz9ar007.pdf

[2]: IBM z/Architecture Principles of Operation, SA22-7832-14, IBM z17,
     https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf

opcodes/
	* s390-opc.txt (mvcl): Use RR_RERE instruction format.

gas/testsuite/
	* gas/s390/esa-g5.d (mvcl): Operands R1 and R2 must designate
	an even-odd register pair.
	* gas/s390/esa-g5.s (mvcl): Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 gas/testsuite/gas/s390/esa-g5.d | 2 +-
 gas/testsuite/gas/s390/esa-g5.s | 2 +-
 opcodes/s390-opc.txt            | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
  

Patch

diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 044e2158f90e..74fb5920dd00 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -339,7 +339,7 @@  Disassembly of section .text:
 .*:	e5 0f 5f ff af ff [	 ]*mvcdk	4095\(%r5\),4095\(%r10\)
 .*:	e8 ff 5f ff af ff [	 ]*mvcin	4095\(256,%r5\),4095\(%r10\)
 .*:	d9 69 5f ff af ff [	 ]*mvck	4095\(%r6,%r5\),4095\(%r10\),%r9
-.*:	0e 69 [	 ]*mvcl	%r6,%r9
+.*:	0e 68 [	 ]*mvcl	%r6,%r8
 .*:	a8 68 5f ff [	 ]*mvcle	%r6,%r8,4095\(%r5\)
 .*:	eb 68 5f ff 00 8e [	 ]*mvclu	%r6,%r8,4095\(%r5\)
 .*:	da 69 5f ff af ff [	 ]*mvcp	4095\(%r6,%r5\),4095\(%r10\),%r9
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index ec81621d7bab..e33b086bc026 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -333,7 +333,7 @@  foo:
 	mvcdk	4095(%r5),4095(%r10)
 	mvcin	4095(256,%r5),4095(%r10)
 	mvck	4095(%r6,%r5),4095(%r10),%r9
-	mvcl	%r6,%r9
+	mvcl	%r6,%r8
 	mvcle	%r6,%r8,4095(%r5)
 	mvclu	%r6,%r8,4095(%r5)
 	mvcp	4095(%r6,%r5),4095(%r10),%r9
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 71b2232cb319..57bee389d4a8 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -131,7 +131,7 @@  d2 mvc SS_L0RDRD "move" g5 esa,zarch
 e50f mvcdk SSE_RDRD "move with destination key" g5 esa,zarch
 e8 mvcin SS_L0RDRD "move inverse" g5 esa,zarch
 d9 mvck SS_RRRDRD "move with key" g5 esa,zarch
-0e mvcl RR_RR "move long" g5 esa,zarch
+0e mvcl RR_RERE "move long" g5 esa,zarch
 da mvcp SS_RRRDRD "move to primary" g5 esa,zarch
 db mvcs SS_RRRDRD "move to secondary" g5 esa,zarch
 e50e mvcsk SSE_RDRD "move with source key" g5 esa,zarch