diff mbox series

[v3,4/4] microblaze: use md_number_to_chars in md_assemble too

Message ID 20260924015023.36799-3-thesamprice@gmail.com
State New
Headers
Series microblaze: fix and clean up md_apply_fix and md_assemble |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Sam Price Sept. 24, 2026, 1:50 a.m. UTC 
  From: Samuel Price <thesamprice@gmail.com>

The six remaining places that store an instruction word spell it out as
four INST_BYTEn assignments.  Each is exactly md_number_to_chars with
INST_WORD_SIZE: the macros are

  #define INST_BYTE0(x) (target_big_endian ? (((x) >> 24) & 0xFF) : ((x) & 0xFF))
  ...
  #define INST_BYTE3(x) (target_big_endian ? ((x) & 0xFF) : (((x) >> 24) & 0xFF))

which is a four-byte store in target byte order and nothing else.  Convert
them, and the macros and the comment describing them have no users left, so
drop those as well.

This finishes what the previous patch started in md_apply_fix.  INST_IMM_OFFSET
stays: it is the part md_number_to_chars cannot do, since the immediate field's
position within the word depends on byte order, not just its contents.

No functional change intended.  This one touches md_assemble, which runs for
every instruction rather than only for relocations, so it is worth saying
which suites were run: gas, binutils and ld, both byte orders, and the
results are identical to the previous patch in the series.

gas/
	* config/tc-microblaze.c (INST_BYTE0, INST_BYTE1, INST_BYTE2)
	(INST_BYTE3): Delete.
	(md_assemble): Use md_number_to_chars.

Signed-off-by: Sam Price <thesamprice@gmail.com>
Assisted-by: Claude (Anthropic)
---
 gas/config/tc-microblaze.c | 38 ++++++--------------------------------
 1 file changed, 6 insertions(+), 32 deletions(-)
diff mbox series

Patch

diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index b2edce8831b..75cf721a4a2 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -41,14 +41,6 @@ 
 void microblaze_generate_symbol (char *sym);
 static bool check_spl_reg (unsigned *);
 
-/* Several places in this file insert raw instructions into the
-   object. They should generate the instruction
-   and then use these four macros to crack the instruction value into
-   the appropriate byte values.  */
-#define	INST_BYTE0(x)  (target_big_endian ? (((x) >> 24) & 0xFF) : ((x) & 0xFF))
-#define	INST_BYTE1(x)  (target_big_endian ? (((x) >> 16) & 0xFF) : (((x) >> 8) & 0xFF))
-#define	INST_BYTE2(x)  (target_big_endian ? (((x) >> 8) & 0xFF) : (((x) >> 16) & 0xFF))
-#define	INST_BYTE3(x)  (target_big_endian ? ((x) & 0xFF) : (((x) >> 24) & 0xFF))
 /* Offset of the 16-bit immediate field within an instruction word.  The
    word is stored in target byte order, so the field moves as well as its
    bytes: it is the low half, which is at offset 2 big-endian and 0
@@ -1068,10 +1060,7 @@  md_assemble (char * str)
 
           for (i = 0; i < count - 1; i++)
 	    {
-              output[0] = INST_BYTE0 (inst);
-              output[1] = INST_BYTE1 (inst);
-              output[2] = INST_BYTE2 (inst);
-              output[3] = INST_BYTE3 (inst);
+	      md_number_to_chars (output, inst, INST_WORD_SIZE);
               output = frag_more (isize);
               immed = immed + 4;
               reg1++;
@@ -1096,10 +1085,7 @@  md_assemble (char * str)
 
               inst1 = opcode1->bit_sequence;
               inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-              output[0] = INST_BYTE0 (inst1);
-              output[1] = INST_BYTE1 (inst1);
-              output[2] = INST_BYTE2 (inst1);
-              output[3] = INST_BYTE3 (inst1);
+	      md_number_to_chars (output, inst1, INST_WORD_SIZE);
               output = frag_more (isize);
 	    }
 	  inst |= (reg1 << RD_LOW) & RD_MASK;
@@ -1631,10 +1617,7 @@  md_assemble (char * str)
 
           inst1 = opcode1->bit_sequence;
           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-          output[0] = INST_BYTE0 (inst1);
-          output[1] = INST_BYTE1 (inst1);
-          output[2] = INST_BYTE2 (inst1);
-          output[3] = INST_BYTE3 (inst1);
+	  md_number_to_chars (output, inst1, INST_WORD_SIZE);
           output = frag_more (isize);
         }
 
@@ -1697,10 +1680,7 @@  md_assemble (char * str)
 
           inst1 = opcode1->bit_sequence;
           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-          output[0] = INST_BYTE0 (inst1);
-          output[1] = INST_BYTE1 (inst1);
-          output[2] = INST_BYTE2 (inst1);
-          output[3] = INST_BYTE3 (inst1);
+	  md_number_to_chars (output, inst1, INST_WORD_SIZE);
           output = frag_more (isize);
         }
 
@@ -1770,10 +1750,7 @@  md_assemble (char * str)
 
           inst1 = opcode1->bit_sequence;
           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-          output[0] = INST_BYTE0 (inst1);
-          output[1] = INST_BYTE1 (inst1);
-          output[2] = INST_BYTE2 (inst1);
-          output[3] = INST_BYTE3 (inst1);
+	  md_number_to_chars (output, inst1, INST_WORD_SIZE);
           output = frag_more (isize);
         }
       inst |= (immed << IMM_LOW) & IMM_MASK;
@@ -1813,10 +1790,7 @@  md_assemble (char * str)
   if (strcmp (op_end, opcode->name) && strcmp (op_end, ""))
     as_warn (_("ignoring operands: %s "), op_end);
 
-  output[0] = INST_BYTE0 (inst);
-  output[1] = INST_BYTE1 (inst);
-  output[2] = INST_BYTE2 (inst);
-  output[3] = INST_BYTE3 (inst);
+  md_number_to_chars (output, inst, INST_WORD_SIZE);
 
 #ifdef OBJ_ELF
   dwarf2_emit_insn (4);