diff mbox series

[3/7] aarch64: add pauth-lr feature option

Message ID 20260827151014.9719-4-muhammad.kamran@arm.com
State New
Headers
Series aarch64: Add FEAT_PAuth_LR asm/disasm support |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed

Commit Message

Muhammad Kamran Aug. 27, 2026, 3:10 p.m. UTC 
  From: Matthieu Longo <matthieu.longo@arm.com>

Add a +pauth-lr extension option for FEAT_PAuth_LR.  The option
depends on +pauth and is used to gate the PAuth_LR instructions.
---
 gas/config/tc-aarch64.c  | 1 +
 include/opcode/aarch64.h | 2 ++
 opcodes/aarch64-tbl.h    | 5 +++++
 3 files changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c172bbb7527..dddde0cc232 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -11099,6 +11099,7 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"flagm",		AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
   {"flagm2",		AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
   {"pauth",		AARCH64_FEATURE (PAUTH), AARCH64_NO_FEATURES},
+  {"pauth-lr",		AARCH64_FEATURE (PAUTH_LR), AARCH64_FEATURE (PAUTH)},
   {"xs",		AARCH64_FEATURE (XS), AARCH64_NO_FEATURES},
   {"wfxt",		AARCH64_FEATURE (WFXT), AARCH64_NO_FEATURES},
   {"mops",		AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e07cbb35a3c..4d7ba98fd6b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -81,6 +81,8 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_LS64,
   /* v8.3 Pointer Authentication.  */
   AARCH64_FEATURE_PAUTH,
+  /* Pointer Authentication LR signing extension.  */
+  AARCH64_FEATURE_PAUTH_LR,
   /* FP instructions.  */
   AARCH64_FEATURE_FP,
   /* SIMD instructions.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 570ea52052f..af2bf296896 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2922,6 +2922,8 @@  static const aarch64_feature_set aarch64_feature_sve =
   AARCH64_FEATURE (SVE);
 static const aarch64_feature_set aarch64_feature_pauth =
   AARCH64_FEATURE (PAUTH);
+static const aarch64_feature_set aarch64_feature_pauth_lr =
+  AARCH64_FEATURES (2, PAUTH, PAUTH_LR);
 static const aarch64_feature_set aarch64_feature_compnum =
   AARCH64_FEATURE (COMPNUM);
 static const aarch64_feature_set aarch64_feature_jscvt =
@@ -3179,6 +3181,7 @@  static const aarch64_feature_set aarch64_feature_tev =
 #define FPRCVT		&aarch64_feature_fprcvt
 #define SVE		&aarch64_feature_sve
 #define PAUTH		&aarch64_feature_pauth
+#define PAUTH_LR	&aarch64_feature_pauth_lr
 #define COMPNUM		&aarch64_feature_compnum
 #define JSCVT		&aarch64_feature_jscvt
 #define RCPC		&aarch64_feature_rcpc
@@ -3338,6 +3341,8 @@  static const aarch64_feature_set aarch64_feature_tev =
     FLAGS | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL }
 #define PAUTH_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, PAUTH, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define PAUTH_LR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, PAUTH_LR, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \