diff mbox series

[v2] Support AVX10_V2_AUX instructions

Message ID 20260825201951.2408691-1-RohanRadhesh.Shenoy@amd.com
State New
Headers
Series [v2] Support AVX10_V2_AUX instructions |

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Commit Message

Rohan Shenoy Aug. 25, 2026, 8:19 p.m. UTC 
  Add assembler and disassembler support for AVX10_V2_AUX instructions.

AVX10_V2_AUX can be extended over AVX10.1, not only AVX10.2. Thus, the
only name accepted for this feature is AVX10_V2_AUX/avx10v2aux.

Reference: AI Compute Extensions (ACE) Specification, v1.15
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

Co-authored-by: Ganesh Gopalasubramanian
Co-authored-by: Umesh Kalvakuntla
---

Notes:
    - Naming: AUX10.2-aux/avx10.2aux is intentionally not supported, as such naming would imply dependence on AVX10.2.
    - Generated opcode tables are omitted.
    - Changes in V2 since V1:
      - Addressed comments by Jan and Haochen [1].
      - Add Intel tests.
    
    [1] https://sourceware.org/pipermail/binutils/2026-June/149838.html

 gas/NEWS                                      |   3 +
 gas/config/tc-i386.c                          |   1 +
 gas/doc/c-i386.texi                           |   2 +
 .../gas/i386/x86-64-avx10_v2_aux-intel.d      | 188 ++++++++++++++++
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d  | 187 ++++++++++++++++
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s  | 211 ++++++++++++++++++
 gas/testsuite/gas/i386/x86-64.exp             |   2 +
 opcodes/i386-dis-evex-mod.h                   |  15 ++
 opcodes/i386-dis-evex-prefix.h                |  52 +++++
 opcodes/i386-dis-evex-w.h                     |  45 ++++
 opcodes/i386-dis-evex.h                       |  22 +-
 opcodes/i386-dis.c                            |  26 +++
 opcodes/i386-gen.c                            |   3 +
 opcodes/i386-opc.h                            |   3 +
 opcodes/i386-opc.tbl                          |  63 ++++++
 15 files changed, 812 insertions(+), 11 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s

Comments

Jan Beulich Aug. 26, 2026, 8:15 a.m. UTC | #1 
On 25.08.2026 22:19, Rohan Shenoy wrote:
> Add assembler and disassembler support for AVX10_V2_AUX instructions.
> 
> AVX10_V2_AUX can be extended over AVX10.1, not only AVX10.2. Thus, the
> only name accepted for this feature is AVX10_V2_AUX/avx10v2aux.

I consider this a questionable justification, but well.

> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,8 @@
>  -*- text -*-
>  
> +* Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
> +  and FP6 format conversion instructions.

As the list isn't complete, I'm inclined to suggest to omit it altogether.

> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1255,6 +1255,7 @@ static const arch_entry cpu_arch[] =
>    VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
>    VECARCH (avx10.1aux, AVX10_1_AUX, ANY_AVX10_1_AUX, set),
>    VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
> +  VECARCH (avx10v2aux, AVX10_V2_AUX, ANY_AVX10_V2_AUX, set),

This will need re-basing over the other patch that I have just committed for
you. As it was clear that the other one would want to go in first, I wonder
why you didn't put the one here on top of that one right away (mentioning
the dependency in the post-commit-message area).

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
> @@ -0,0 +1,188 @@
> +#objdump: -dw -Mintel
> +#name: x86-64 AVX10 V2 AUX (Intel disassembly)
> +#source: x86-64-avx10_v2_aux.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +#...
> +[a-f0-9]+ <_intel>:
> +\s*[a-f0-9]+:\s*62 f5 7e 08 39 c1\s+vcvtps2bf8\s+xmm0,xmm1

Please can you replace \s by [ 	], like we do about everywhere else (especially
in newer tests)?

> +\s*[a-f0-9]+:\s*62 f5 7e 28 39 c1\s+vcvtps2bf8\s+xmm0,ymm1
> +\s*[a-f0-9]+:\s*62 f5 7e 48 39 c1\s+vcvtps2bf8\s+xmm0,zmm1
> +\s*[a-f0-9]+:\s*62 f5 7e 08 39 41 7f\s+vcvtps2bf8\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
> +\s*[a-f0-9]+:\s*62 f5 7e 28 39 41 7f\s+vcvtps2bf8\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
> +\s*[a-f0-9]+:\s*62 f5 7e 48 39 41 7f\s+vcvtps2bf8\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
> +\s*[a-f0-9]+:\s*62 d5 7e 18 39 01\s+vcvtps2bf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}

The fields between DWORD and BCST and [ really shouldn't be other than a single
blank. That'll then also help readability (and hence reviewability).

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
> @@ -0,0 +1,211 @@
> +# Check 64-bit AVX10 V2 AUX instructions
> +
> +	.arch generic64
> +	.arch .avx10v2aux
> +	.text
> +_start:
> +	.irp m, bf8, bf8s, hf8, hf8s
> +	vcvtps2\m	%xmm1, %xmm0
> +	vcvtps2\m	%ymm1, %xmm0
> +	vcvtps2\m	%zmm1, %xmm0
> +	vcvtps2\m\()x	2032(%rcx), %xmm0
> +	vcvtps2\m\()y	4064(%rcx), %xmm0
> +	vcvtps2\m\()z	8128(%rcx), %xmm0
> +	vcvtps2\m	(%r9){1to4}, %xmm0
> +	vcvtps2\m	(%r9){1to8}, %xmm0
> +	vcvtps2\m	(%r9){1to16}, %xmm0
> +	vcvtps2\m	%xmm1, %xmm0{%k1}
> +	vcvtps2\m	%xmm1, %xmm0{%k1}{z}
> +
> +	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0
> +	vcvtbiasps2\m	%ymm2, %ymm1, %xmm0
> +	vcvtbiasps2\m	%zmm2, %zmm1, %xmm0
> +	vcvtbiasps2\m	2032(%rcx), %xmm1, %xmm0
> +	vcvtbiasps2\m	4064(%rcx), %ymm1, %xmm0
> +	vcvtbiasps2\m	8128(%rcx), %zmm1, %xmm0
> +	vcvtbiasps2\m	(%r9){1to4}, %xmm1, %xmm0
> +	vcvtbiasps2\m	(%r9){1to8}, %ymm1, %xmm0
> +	vcvtbiasps2\m	(%r9){1to16}, %zmm1, %xmm0
> +	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0{%k1}
> +	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0{%k1}{z}
> +	.endr
> +
> +	.irp m, hf8, hf8s
> +	vcvtrops2\m	%xmm1, %xmm0
> +	vcvtrops2\m	%ymm1, %xmm0
> +	vcvtrops2\m	%zmm1, %xmm0
> +	vcvtrops2\m\()x	2032(%rcx), %xmm0
> +	vcvtrops2\m\()y	4064(%rcx), %xmm0
> +	vcvtrops2\m\()z	8128(%rcx), %xmm0
> +	vcvtrops2\m	(%r9){1to4}, %xmm0
> +	vcvtrops2\m	(%r9){1to8}, %xmm0
> +	vcvtrops2\m	(%r9){1to16}, %xmm0
> +	vcvtrops2\m	%xmm1, %xmm0{%k1}
> +	vcvtrops2\m	%xmm1, %xmm0{%k1}{z}
> +	.endr
> +
> +	.irp f, bf, hf
> +	vcvt\f\()82ps	%xmm1, %xmm0
> +	vcvt\f\()82ps	%xmm1, %ymm0
> +	vcvt\f\()82ps	%xmm1, %zmm0
> +	vcvt\f\()82ps	508(%rcx), %xmm0
> +	vcvt\f\()82ps	1016(%rcx), %ymm0
> +	vcvt\f\()82ps	2032(%rcx), %zmm0
> +	vcvt\f\()82ps	%xmm1, %xmm0{%k1}
> +	vcvt\f\()82ps	%xmm1, %xmm0{%k1}{z}
> +
> +	vcvt\f\()82bf4s	%xmm1, %xmm0
> +	vcvt\f\()82bf4s	%ymm1, %xmm0
> +	vcvt\f\()82bf4s	%zmm1, %ymm0
> +	vcvt\f\()82bf4s	%xmm1, 1016(%rcx)
> +	vcvt\f\()82bf4s	%ymm1, 2032(%rcx)
> +	vcvt\f\()82bf4s	%zmm1, 4064(%rcx)
> +
> +	.endr

Nit: Stray blank line above here (or another one wants inserting after the
.irp one, but then similarly in the other .irp above).

> +	vcvtbf82bf6s	%xmm1, %xmm0
> +	vcvtbf82bf6s	%ymm1, %ymm0
> +	vcvtbf82bf6s	%zmm1, %zmm0
> +
> +	vcvthf82hf6s	%xmm1, %xmm0
> +	vcvthf82hf6s	%ymm1, %ymm0
> +	vcvthf82hf6s	%zmm1, %zmm0
> +
> +	vcvtbf42hf8	%xmm1, %xmm0
> +	vcvtbf42hf8	%xmm1, %ymm0
> +	vcvtbf42hf8	%ymm1, %zmm0
> +	vcvtbf42hf8	1016(%rcx), %xmm0
> +	vcvtbf42hf8	2032(%rcx), %ymm0
> +	vcvtbf42hf8	4064(%rcx), %zmm0
> +	vcvtbf42hf8	%xmm1, %xmm0{%k1}
> +	vcvtbf42hf8	%xmm1, %xmm0{%k1}{z}
> +
> +	.irp f, bf, hf
> +	vcvt\f\()62hf8	%xmm1, %xmm0
> +	vcvt\f\()62hf8	%ymm1, %ymm0
> +	vcvt\f\()62hf8	%zmm1, %zmm0
> +	vcvt\f\()62hf8	%xmm1, %xmm0{%k1}
> +	vcvt\f\()62hf8	%xmm1, %xmm0{%k1}{z}
> +	.endr
> +
> +	vpmovssdb	%xmm1, %xmm0
> +	vpmovssdb	%ymm1, %xmm0
> +	vpmovssdb	%zmm1, %xmm0
> +	vpmovssdb	%xmm1, 508(%rcx)
> +	vpmovssdb	%ymm1, 1016(%rcx)
> +	vpmovssdb	%zmm1, 2032(%rcx)
> +	vpmovssdb	%xmm1, %xmm0{%k1}
> +	vpmovssdb	%xmm1, %xmm0{%k1}{z}
> +
> +	vunpackb	$1, %xmm1, %xmm0
> +	vunpackb	$1, %ymm1, %ymm0
> +	vunpackb	$1, %zmm1, %zmm0
> +	vunpackb	$1, 2032(%rcx), %xmm0
> +	vunpackb	$1, 4064(%rcx), %ymm0
> +	vunpackb	$1, 8128(%rcx), %zmm0
> +	vunpackb	$1, %xmm1, %xmm0{%k1}
> +	vunpackb	$1, %xmm1, %xmm0{%k1}{z}

Please use immediates which are actually valid for the insn. We could
in principle add warnings for 0, 1, and everything 8 upwards, and doing
so should not result in the need to touch testcases like this one.

> --- a/opcodes/i386-dis-evex-mod.h
> +++ b/opcodes/i386-dis-evex-mod.h
> @@ -18,3 +18,18 @@
>      { "enqcmd",		{ Gva, M }, 0 },
>      { VEX_W_TABLE (EVEX_W_MAP4_F8_P3_M_1) },
>    },
> +  /* MOD_EVEX_MAP5_37_P_2 */
> +  {
> +    { Bad_Opcode },
> +    { "vcvt%XF62hf8",	{ XM, EXx }, 0 },
> +  },
> +  /* MOD_EVEX_MAP5_3C_W_0_P_1 */
> +  {
> +    { Bad_Opcode },
> +    { "vcvthf82hf6s",	{ XM, EXx }, 0 },
> +  },
> +  /* MOD_EVEX_MAP5_3E_W_1_P_1 */
> +  {
> +    { Bad_Opcode },
> +    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
> +  },

I think these can move up a level (i.e. without going through mod_table[]),
by using Ux in place of EXx. As you can see from other mod_table[] entries
(and respective prior commits), they always have both elements set to
something other than Bad_Opcode.

> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> @@ -346,6 +346,11 @@
>    {
>      { "vpbroadcastmw2dY",	{ XM, MaskR }, 0 },
>    },
> +  /* EVEX_W_0F3841 */
> +  {
> +    { PREFIX_TABLE (PREFIX_EVEX_0F3841_W_0) },
> +    { Bad_Opcode },
> +  },

As you can see even from patch context here, there's no need for trailing
Bad_Opcode entries. Same about everywhere below.

> @@ -1935,6 +1958,7 @@ struct dis386 {
>     "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
>     "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding
>  	   (for BF16)
> +   "XF" => print 'hf' if EVEX.W=0 or 'bf' if EVEX.W=1

HB would be the more natural name for this. Whether to include 'f' in the
expansion is uncertain, but I'm okay with keeping it like that for now (in
the interest of shorter string literals in the tables).

> @@ -11075,6 +11099,8 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
>  		  ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
>  		}
>  	    }
> +	  else if (l == 1 && last[0] == 'X')
> +	    oappend (ins, ins->vex.w ? "bf" : "hf");

I don't think using oappend() is valid here, as that'll insert markings
for dis_style_text. Like respective surrounding code does, you want to use
"*ins->obufp++ = ..." here.

> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -251,6 +251,8 @@ static const dependency isa_dependencies[] =
>      "AVX10_1" },
>    { "AVX10_2",
>      "AVX10_1_AUX" },
> +  { "AVX10_V2_AUX",
> +    "AVX10_1" },

Just to double check: It's not AVX_1_AUX that this wants to depend upon?
I.e. in particular full-fledged ACE demands only 10.1 plus v2-aux? (I'm
leaving aside whether really we want to have ACE have a dependency on
whatever AVX10 variant it builds upon.)

> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -332,6 +332,8 @@ enum i386_cpu
>    CpuAPX_NDD,
>    /* Intel APX No-Flags-update support required.  */
>    CpuAPX_NF,
> +  /* AVX10 V2 Auxiliary Instructions support required.  */
> +  CpuAVX10_V2_AUX,

I think this would best go right after CpuAVX10_1_AUX.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -2266,6 +2266,13 @@ vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDY
>      x:AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, +
>      y:AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM>
>  
> +<Exyz:attr:src, +
> +    $i:Disp8ShiftVL|IntelSyntax:RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, +
> +    $a:Disp8ShiftVL|ATTSyntax:RegXMM|RegYMM|RegZMM|BaseIndex, +
> +    x:EVex128|Disp8MemShift=4|ATTSyntax:RegXMM|Unspecified|BaseIndex, +
> +    y:EVex256|Disp8MemShift=5|ATTSyntax:RegYMM|Unspecified|BaseIndex, +
> +    z:EVex512|Disp8MemShift=6|ATTSyntax:RegZMM|Unspecified|BaseIndex>

I can't quite spot why this is needed, i.e. why <xyz> cannot be reused.

> @@ -3614,6 +3621,62 @@ vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
>  
>  // AVX10.2 instructions end.
>  
> +// AVX10_V2_AUX instructions.
> +
> +<cvtps8:opc, +
> +    bf8:39, +
> +    bf8s:3b, +
> +    hf8:38, +
> +    hf8s:3a>

This can go on a single line.

> +vcvtps2<cvtps8><Exyz>, 0xf3<cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|<Exyz:attr>|VexW0|Masking|Broadcast|NoSuf, { <Exyz:src>|Dword, RegXMM }
> +
> +vcvtbiasps2<cvtps8>, 0x<cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM }
> +
> +<cvtps8>
> +
> +<cvtrops8:opc, +
> +    hf8:38, +
> +    hf8s:3a>

Same here.

> +vcvtrops2<cvtrops8><Exyz>, 0x66<cvtrops8:opc>, AVX10_V2_AUX, Modrm|Map5|<Exyz:attr>|VexW0|Masking|Broadcast|NoSuf, { <Exyz:src>|Dword, RegXMM }
> +
> +<cvtrops8>
> +
> +<fp:vexw, +
> +    hf:VexW0, +
> +    bf:VexW1>

And here. For this one I further think <f8> would be a better name, and then
the '8' may want including in the expansions (but see below).

> +vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex128|<fp:vexw>|Masking|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex256|<fp:vexw>|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
> +vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex512|<fp:vexw>|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
> +
> +vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex128|<fp:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
> +vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex256|<fp:vexw>|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
> +vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex512|<fp:vexw>|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
> +
> +<fp>
> +
> +vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|EVexDYN|Map5|VexW1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +
> +vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|EVexDYN|Map5|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

With an F6-opcode field added, <fp> from above looks to also be usable here.
Except that this may then need an adjustment to i386-gen, such that the
choice of h vs b can be suitably expressed for the 2nd occurrence of the
letters in the mnemonics. That is, without resorting to something like

<fp:form:vexw, $h:hf8:VexW0, $b:bf8:VexW1>

as that would result in somewhat awkward use in the mnemonics further up.

Overall - perhaps not worth it for the moment.

> +vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
> +vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
> +vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
> +
> +vcvtbf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW1|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +
> +vcvthf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW0|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

Without the '8' included in the expansion, <fp> from above would be usable here
with no adjustment at all, afaict. Then <f8> may not be a good name, yet <fp>
also doesn't look overly suitable (for being too broad a name). Maybe <hb> or
<hbf>?

Jan
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 70cfbf41a7a..7b822fc59d2 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@ 
 -*- text -*-
 
+* Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
+  and FP6 format conversion instructions.
+
 * The avr target supports .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).
   For details, see https://sourceware.org/PR34305
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 1ce5a063c67..4b87f8b71ce 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1255,6 +1255,7 @@  static const arch_entry cpu_arch[] =
   VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
   VECARCH (avx10.1aux, AVX10_1_AUX, ANY_AVX10_1_AUX, set),
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
+  VECARCH (avx10v2aux, AVX10_V2_AUX, ANY_AVX10_V2_AUX, set),
   SUBARCH (user_msr, USER_MSR, USER_MSR, false),
   SUBARCH (apx_f, APX_F, ANY_APX_F, false),
   SUBARCH (apx_nci, APX_NCI, ANY_APX_NCI, false),
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 66d94a141b9..a65efd48f6c 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -232,6 +232,7 @@  accept various extension mnemonics.  For example,
 @code{avx10.2/512},
 @code{avx10.2/256},
 @code{avx10.2/128},
+@code{avx10v2aux},
 @code{movrs},
 @code{amx_int8},
 @code{amx_bf16},
@@ -1720,6 +1721,7 @@  supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
 @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{avx512_bmm}
 @item @samp{.avx10.1} @tab @samp{.avx10.1aux} @tab @samp{.avx10.2} @tab @samp{.clwb}
+@item @samp{.avx10v2aux}
 @item @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @tab @samp{.prefetchi}
 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @tab @samp{.se1}
 @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
new file mode 100644
index 00000000000..d13225806b2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
@@ -0,0 +1,188 @@ 
+#objdump: -dw -Mintel
+#name: x86-64 AVX10 V2 AUX (Intel disassembly)
+#source: x86-64-avx10_v2_aux.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 f5 7e 08 39 c1\s+vcvtps2bf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 39 c1\s+vcvtps2bf8\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 39 c1\s+vcvtps2bf8\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 39 41 7f\s+vcvtps2bf8\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7e 28 39 41 7f\s+vcvtps2bf8\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7e 48 39 41 7f\s+vcvtps2bf8\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7e 18 39 01\s+vcvtps2bf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7e 38 39 01\s+vcvtps2bf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7e 58 39 01\s+vcvtps2bf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7e 09 39 c1\s+vcvtps2bf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 89 39 c1\s+vcvtps2bf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 74 08 39 c2\s+vcvtbiasps2bf8\s+xmm0,xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 28 39 c2\s+vcvtbiasps2bf8\s+xmm0,ymm1,ymm2
+\s*[a-f0-9]+:\s*62 f5 74 48 39 c2\s+vcvtbiasps2bf8\s+xmm0,zmm1,zmm2
+\s*[a-f0-9]+:\s*62 f5 74 08 39 41 7f\s+vcvtbiasps2bf8\s+xmm0,xmm1,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 74 28 39 41 7f\s+vcvtbiasps2bf8\s+xmm0,ymm1,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 74 48 39 41 7f\s+vcvtbiasps2bf8\s+xmm0,zmm1,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 74 18 39 01\s+vcvtbiasps2bf8\s+xmm0,xmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 38 39 01\s+vcvtbiasps2bf8\s+xmm0,ymm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 58 39 01\s+vcvtbiasps2bf8\s+xmm0,zmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 f5 74 09 39 c2\s+vcvtbiasps2bf8\s+xmm0\{k1\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 89 39 c2\s+vcvtbiasps2bf8\s+xmm0\{k1\}\{z\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 7e 08 3b c1\s+vcvtps2bf8s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 3b c1\s+vcvtps2bf8s\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 3b c1\s+vcvtps2bf8s\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 3b 41 7f\s+vcvtps2bf8s\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7e 28 3b 41 7f\s+vcvtps2bf8s\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7e 48 3b 41 7f\s+vcvtps2bf8s\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7e 18 3b 01\s+vcvtps2bf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7e 38 3b 01\s+vcvtps2bf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7e 58 3b 01\s+vcvtps2bf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7e 09 3b c1\s+vcvtps2bf8s\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 89 3b c1\s+vcvtps2bf8s\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 74 08 3b c2\s+vcvtbiasps2bf8s\s+xmm0,xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 28 3b c2\s+vcvtbiasps2bf8s\s+xmm0,ymm1,ymm2
+\s*[a-f0-9]+:\s*62 f5 74 48 3b c2\s+vcvtbiasps2bf8s\s+xmm0,zmm1,zmm2
+\s*[a-f0-9]+:\s*62 f5 74 08 3b 41 7f\s+vcvtbiasps2bf8s\s+xmm0,xmm1,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 74 28 3b 41 7f\s+vcvtbiasps2bf8s\s+xmm0,ymm1,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 74 48 3b 41 7f\s+vcvtbiasps2bf8s\s+xmm0,zmm1,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 74 18 3b 01\s+vcvtbiasps2bf8s\s+xmm0,xmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 38 3b 01\s+vcvtbiasps2bf8s\s+xmm0,ymm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 58 3b 01\s+vcvtbiasps2bf8s\s+xmm0,zmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 f5 74 09 3b c2\s+vcvtbiasps2bf8s\s+xmm0\{k1\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 89 3b c2\s+vcvtbiasps2bf8s\s+xmm0\{k1\}\{z\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 7e 08 38 c1\s+vcvtps2hf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 38 c1\s+vcvtps2hf8\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 38 c1\s+vcvtps2hf8\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 38 41 7f\s+vcvtps2hf8\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7e 28 38 41 7f\s+vcvtps2hf8\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7e 48 38 41 7f\s+vcvtps2hf8\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7e 18 38 01\s+vcvtps2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7e 38 38 01\s+vcvtps2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7e 58 38 01\s+vcvtps2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7e 09 38 c1\s+vcvtps2hf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 89 38 c1\s+vcvtps2hf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 74 08 38 c2\s+vcvtbiasps2hf8\s+xmm0,xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 28 38 c2\s+vcvtbiasps2hf8\s+xmm0,ymm1,ymm2
+\s*[a-f0-9]+:\s*62 f5 74 48 38 c2\s+vcvtbiasps2hf8\s+xmm0,zmm1,zmm2
+\s*[a-f0-9]+:\s*62 f5 74 08 38 41 7f\s+vcvtbiasps2hf8\s+xmm0,xmm1,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 74 28 38 41 7f\s+vcvtbiasps2hf8\s+xmm0,ymm1,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 74 48 38 41 7f\s+vcvtbiasps2hf8\s+xmm0,zmm1,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 74 18 38 01\s+vcvtbiasps2hf8\s+xmm0,xmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 38 38 01\s+vcvtbiasps2hf8\s+xmm0,ymm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 58 38 01\s+vcvtbiasps2hf8\s+xmm0,zmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 f5 74 09 38 c2\s+vcvtbiasps2hf8\s+xmm0\{k1\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 89 38 c2\s+vcvtbiasps2hf8\s+xmm0\{k1\}\{z\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 7e 08 3a c1\s+vcvtps2hf8s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 3a c1\s+vcvtps2hf8s\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 3a c1\s+vcvtps2hf8s\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 3a 41 7f\s+vcvtps2hf8s\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7e 28 3a 41 7f\s+vcvtps2hf8s\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7e 48 3a 41 7f\s+vcvtps2hf8s\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7e 18 3a 01\s+vcvtps2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7e 38 3a 01\s+vcvtps2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7e 58 3a 01\s+vcvtps2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7e 09 3a c1\s+vcvtps2hf8s\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 89 3a c1\s+vcvtps2hf8s\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 74 08 3a c2\s+vcvtbiasps2hf8s\s+xmm0,xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 28 3a c2\s+vcvtbiasps2hf8s\s+xmm0,ymm1,ymm2
+\s*[a-f0-9]+:\s*62 f5 74 48 3a c2\s+vcvtbiasps2hf8s\s+xmm0,zmm1,zmm2
+\s*[a-f0-9]+:\s*62 f5 74 08 3a 41 7f\s+vcvtbiasps2hf8s\s+xmm0,xmm1,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 74 28 3a 41 7f\s+vcvtbiasps2hf8s\s+xmm0,ymm1,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 74 48 3a 41 7f\s+vcvtbiasps2hf8s\s+xmm0,zmm1,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 74 18 3a 01\s+vcvtbiasps2hf8s\s+xmm0,xmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 38 3a 01\s+vcvtbiasps2hf8s\s+xmm0,ymm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 d5 74 58 3a 01\s+vcvtbiasps2hf8s\s+xmm0,zmm1,DWORD\s+BCST\s+\[r9\]
+\s*[a-f0-9]+:\s*62 f5 74 09 3a c2\s+vcvtbiasps2hf8s\s+xmm0\{k1\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 74 89 3a c2\s+vcvtbiasps2hf8s\s+xmm0\{k1\}\{z\},xmm1,xmm2
+\s*[a-f0-9]+:\s*62 f5 7d 08 38 c1\s+vcvtrops2hf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 28 38 c1\s+vcvtrops2hf8\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7d 48 38 c1\s+vcvtrops2hf8\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7d 08 38 41 7f\s+vcvtrops2hf8\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7d 28 38 41 7f\s+vcvtrops2hf8\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7d 48 38 41 7f\s+vcvtrops2hf8\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7d 18 38 01\s+vcvtrops2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7d 38 38 01\s+vcvtrops2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7d 58 38 01\s+vcvtrops2hf8\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7d 09 38 c1\s+vcvtrops2hf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 89 38 c1\s+vcvtrops2hf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 08 3a c1\s+vcvtrops2hf8s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 28 3a c1\s+vcvtrops2hf8s\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7d 48 3a c1\s+vcvtrops2hf8s\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7d 08 3a 41 7f\s+vcvtrops2hf8s\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7d 28 3a 41 7f\s+vcvtrops2hf8s\s+xmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7d 48 3a 41 7f\s+vcvtrops2hf8s\s+xmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 d5 7d 18 3a 01\s+vcvtrops2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to4\}
+\s*[a-f0-9]+:\s*62 d5 7d 38 3a 01\s+vcvtrops2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to8\}
+\s*[a-f0-9]+:\s*62 d5 7d 58 3a 01\s+vcvtrops2hf8s\s+xmm0,DWORD\s+BCST\s+\[r9\]\{1to16\}
+\s*[a-f0-9]+:\s*62 f5 7d 09 3a c1\s+vcvtrops2hf8s\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 89 3a c1\s+vcvtrops2hf8s\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 fc 08 36 c1\s+vcvtbf82ps\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fc 28 36 c1\s+vcvtbf82ps\s+ymm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fc 48 36 c1\s+vcvtbf82ps\s+zmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fc 08 36 41 7f\s+vcvtbf82ps\s+xmm0,DWORD\s+PTR\s+\[rcx\+0x1fc\]
+\s*[a-f0-9]+:\s*62 f5 fc 28 36 41 7f\s+vcvtbf82ps\s+ymm0,QWORD\s+PTR\s+\[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*62 f5 fc 48 36 41 7f\s+vcvtbf82ps\s+zmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 fc 09 36 c1\s+vcvtbf82ps\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 fc 89 36 c1\s+vcvtbf82ps\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 fe 08 3d c8\s+vcvtbf82bf4s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fe 28 3d c8\s+vcvtbf82bf4s\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 fe 48 3d c8\s+vcvtbf82bf4s\s+ymm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 fe 08 3d 49 7f\s+vcvtbf82bf4s\s+QWORD\s+PTR\s+\[rcx\+0x3f8\],xmm1
+\s*[a-f0-9]+:\s*62 f5 fe 28 3d 49 7f\s+vcvtbf82bf4s\s+XMMWORD\s+PTR\s+\[rcx\+0x7f0\],ymm1
+\s*[a-f0-9]+:\s*62 f5 fe 48 3d 49 7f\s+vcvtbf82bf4s\s+YMMWORD\s+PTR\s+\[rcx\+0xfe0\],zmm1
+\s*[a-f0-9]+:\s*62 f5 7c 08 36 c1\s+vcvthf82ps\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 28 36 c1\s+vcvthf82ps\s+ymm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 48 36 c1\s+vcvthf82ps\s+zmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 08 36 41 7f\s+vcvthf82ps\s+xmm0,DWORD\s+PTR\s+\[rcx\+0x1fc\]
+\s*[a-f0-9]+:\s*62 f5 7c 28 36 41 7f\s+vcvthf82ps\s+ymm0,QWORD\s+PTR\s+\[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*62 f5 7c 48 36 41 7f\s+vcvthf82ps\s+zmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7c 09 36 c1\s+vcvthf82ps\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 89 36 c1\s+vcvthf82ps\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 3d c8\s+vcvthf82bf4s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 3d c8\s+vcvthf82bf4s\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 3d c8\s+vcvthf82bf4s\s+ymm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 3d 49 7f\s+vcvthf82bf4s\s+QWORD\s+PTR\s+\[rcx\+0x3f8\],xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 3d 49 7f\s+vcvthf82bf4s\s+XMMWORD\s+PTR\s+\[rcx\+0x7f0\],ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 3d 49 7f\s+vcvthf82bf4s\s+YMMWORD\s+PTR\s+\[rcx\+0xfe0\],zmm1
+\s*[a-f0-9]+:\s*62 f5 fe 08 3e c1\s+vcvtbf82bf6s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fe 28 3e c1\s+vcvtbf82bf6s\s+ymm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 fe 48 3e c1\s+vcvtbf82bf6s\s+zmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7e 08 3c c1\s+vcvthf82hf6s\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7e 28 3c c1\s+vcvthf82hf6s\s+ymm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7e 48 3c c1\s+vcvthf82hf6s\s+zmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7c 08 37 c1\s+vcvtbf42hf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 28 37 c1\s+vcvtbf42hf8\s+ymm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 48 37 c1\s+vcvtbf42hf8\s+zmm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7c 08 37 41 7f\s+vcvtbf42hf8\s+xmm0,QWORD\s+PTR\s+\[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*62 f5 7c 28 37 41 7f\s+vcvtbf42hf8\s+ymm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f5 7c 48 37 41 7f\s+vcvtbf42hf8\s+zmm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f5 7c 09 37 c1\s+vcvtbf42hf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7c 89 37 c1\s+vcvtbf42hf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 fd 08 37 c1\s+vcvtbf62hf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 fd 28 37 c1\s+vcvtbf62hf8\s+ymm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 fd 48 37 c1\s+vcvtbf62hf8\s+zmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 fd 09 37 c1\s+vcvtbf62hf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 fd 89 37 c1\s+vcvtbf62hf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 08 37 c1\s+vcvthf62hf8\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 28 37 c1\s+vcvthf62hf8\s+ymm0,ymm1
+\s*[a-f0-9]+:\s*62 f5 7d 48 37 c1\s+vcvthf62hf8\s+zmm0,zmm1
+\s*[a-f0-9]+:\s*62 f5 7d 09 37 c1\s+vcvthf62hf8\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f5 7d 89 37 c1\s+vcvthf62hf8\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f2 7e 08 41 c8\s+vpmovssdb\s+xmm0,xmm1
+\s*[a-f0-9]+:\s*62 f2 7e 28 41 c8\s+vpmovssdb\s+xmm0,ymm1
+\s*[a-f0-9]+:\s*62 f2 7e 48 41 c8\s+vpmovssdb\s+xmm0,zmm1
+\s*[a-f0-9]+:\s*62 f2 7e 08 41 49 7f\s+vpmovssdb\s+DWORD\s+PTR\s+\[rcx\+0x1fc\],xmm1
+\s*[a-f0-9]+:\s*62 f2 7e 28 41 49 7f\s+vpmovssdb\s+QWORD\s+PTR\s+\[rcx\+0x3f8\],ymm1
+\s*[a-f0-9]+:\s*62 f2 7e 48 41 49 7f\s+vpmovssdb\s+XMMWORD\s+PTR\s+\[rcx\+0x7f0\],zmm1
+\s*[a-f0-9]+:\s*62 f2 7e 09 41 c8\s+vpmovssdb\s+xmm0\{k1\},xmm1
+\s*[a-f0-9]+:\s*62 f2 7e 89 41 c8\s+vpmovssdb\s+xmm0\{k1\}\{z\},xmm1
+\s*[a-f0-9]+:\s*62 f3 7c 08 3d c1 01\s+vunpackb\s+xmm0,xmm1,0x1
+\s*[a-f0-9]+:\s*62 f3 7c 28 3d c1 01\s+vunpackb\s+ymm0,ymm1,0x1
+\s*[a-f0-9]+:\s*62 f3 7c 48 3d c1 01\s+vunpackb\s+zmm0,zmm1,0x1
+\s*[a-f0-9]+:\s*62 f3 7c 08 3d 41 7f 01\s+vunpackb\s+xmm0,XMMWORD\s+PTR\s+\[rcx\+0x7f0\],0x1
+\s*[a-f0-9]+:\s*62 f3 7c 28 3d 41 7f 01\s+vunpackb\s+ymm0,YMMWORD\s+PTR\s+\[rcx\+0xfe0\],0x1
+\s*[a-f0-9]+:\s*62 f3 7c 48 3d 41 7f 01\s+vunpackb\s+zmm0,ZMMWORD\s+PTR\s+\[rcx\+0x1fc0\],0x1
+\s*[a-f0-9]+:\s*62 f3 7c 09 3d c1 01\s+vunpackb\s+xmm0\{k1\},xmm1,0x1
+\s*[a-f0-9]+:\s*62 f3 7c 89 3d c1 01\s+vunpackb\s+xmm0\{k1\}\{z\},xmm1,0x1
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
new file mode 100644
index 00000000000..1e44eb89f53
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
@@ -0,0 +1,187 @@ 
+#objdump: -dw -Mx86-64
+#name: x86-64 AVX10 V2 AUX
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f5 7e 08 39 c1\s+vcvtps2bf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 39 c1\s+vcvtps2bf8\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 39 c1\s+vcvtps2bf8\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 39 41 7f\s+vcvtps2bf8x\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 39 41 7f\s+vcvtps2bf8y\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 39 41 7f\s+vcvtps2bf8z\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 18 39 01\s+vcvtps2bf8\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 38 39 01\s+vcvtps2bf8\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 58 39 01\s+vcvtps2bf8\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 09 39 c1\s+vcvtps2bf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7e 89 39 c1\s+vcvtps2bf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 74 08 39 c2\s+vcvtbiasps2bf8\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 39 c2\s+vcvtbiasps2bf8\s+%ymm2,%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 39 c2\s+vcvtbiasps2bf8\s+%zmm2,%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 08 39 41 7f\s+vcvtbiasps2bf8\s+0x7f0\(%rcx\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 39 41 7f\s+vcvtbiasps2bf8\s+0xfe0\(%rcx\),%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 39 41 7f\s+vcvtbiasps2bf8\s+0x1fc0\(%rcx\),%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 18 39 01\s+vcvtbiasps2bf8\s+\(%r9\)\{1to4\},%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 38 39 01\s+vcvtbiasps2bf8\s+\(%r9\)\{1to8\},%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 58 39 01\s+vcvtbiasps2bf8\s+\(%r9\)\{1to16\},%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 09 39 c2\s+vcvtbiasps2bf8\s+%xmm2,%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 74 89 39 c2\s+vcvtbiasps2bf8\s+%xmm2,%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7e 08 3b c1\s+vcvtps2bf8s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3b c1\s+vcvtps2bf8s\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3b c1\s+vcvtps2bf8s\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 3b 41 7f\s+vcvtps2bf8sx\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3b 41 7f\s+vcvtps2bf8sy\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3b 41 7f\s+vcvtps2bf8sz\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 18 3b 01\s+vcvtps2bf8s\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 38 3b 01\s+vcvtps2bf8s\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 58 3b 01\s+vcvtps2bf8s\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 09 3b c1\s+vcvtps2bf8s\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7e 89 3b c1\s+vcvtps2bf8s\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 74 08 3b c2\s+vcvtbiasps2bf8s\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 3b c2\s+vcvtbiasps2bf8s\s+%ymm2,%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 3b c2\s+vcvtbiasps2bf8s\s+%zmm2,%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 08 3b 41 7f\s+vcvtbiasps2bf8s\s+0x7f0\(%rcx\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 3b 41 7f\s+vcvtbiasps2bf8s\s+0xfe0\(%rcx\),%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 3b 41 7f\s+vcvtbiasps2bf8s\s+0x1fc0\(%rcx\),%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 18 3b 01\s+vcvtbiasps2bf8s\s+\(%r9\)\{1to4\},%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 38 3b 01\s+vcvtbiasps2bf8s\s+\(%r9\)\{1to8\},%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 58 3b 01\s+vcvtbiasps2bf8s\s+\(%r9\)\{1to16\},%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 09 3b c2\s+vcvtbiasps2bf8s\s+%xmm2,%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 74 89 3b c2\s+vcvtbiasps2bf8s\s+%xmm2,%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7e 08 38 c1\s+vcvtps2hf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 38 c1\s+vcvtps2hf8\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 38 c1\s+vcvtps2hf8\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 38 41 7f\s+vcvtps2hf8x\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 38 41 7f\s+vcvtps2hf8y\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 38 41 7f\s+vcvtps2hf8z\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 18 38 01\s+vcvtps2hf8\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 38 38 01\s+vcvtps2hf8\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 58 38 01\s+vcvtps2hf8\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 09 38 c1\s+vcvtps2hf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7e 89 38 c1\s+vcvtps2hf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 74 08 38 c2\s+vcvtbiasps2hf8\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 38 c2\s+vcvtbiasps2hf8\s+%ymm2,%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 38 c2\s+vcvtbiasps2hf8\s+%zmm2,%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 08 38 41 7f\s+vcvtbiasps2hf8\s+0x7f0\(%rcx\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 38 41 7f\s+vcvtbiasps2hf8\s+0xfe0\(%rcx\),%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 38 41 7f\s+vcvtbiasps2hf8\s+0x1fc0\(%rcx\),%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 18 38 01\s+vcvtbiasps2hf8\s+\(%r9\)\{1to4\},%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 38 38 01\s+vcvtbiasps2hf8\s+\(%r9\)\{1to8\},%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 58 38 01\s+vcvtbiasps2hf8\s+\(%r9\)\{1to16\},%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 09 38 c2\s+vcvtbiasps2hf8\s+%xmm2,%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 74 89 38 c2\s+vcvtbiasps2hf8\s+%xmm2,%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7e 08 3a c1\s+vcvtps2hf8s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3a c1\s+vcvtps2hf8s\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3a c1\s+vcvtps2hf8s\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 3a 41 7f\s+vcvtps2hf8sx\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3a 41 7f\s+vcvtps2hf8sy\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3a 41 7f\s+vcvtps2hf8sz\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 18 3a 01\s+vcvtps2hf8s\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 38 3a 01\s+vcvtps2hf8s\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7e 58 3a 01\s+vcvtps2hf8s\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 09 3a c1\s+vcvtps2hf8s\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7e 89 3a c1\s+vcvtps2hf8s\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 74 08 3a c2\s+vcvtbiasps2hf8s\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 3a c2\s+vcvtbiasps2hf8s\s+%ymm2,%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 3a c2\s+vcvtbiasps2hf8s\s+%zmm2,%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 08 3a 41 7f\s+vcvtbiasps2hf8s\s+0x7f0\(%rcx\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 28 3a 41 7f\s+vcvtbiasps2hf8s\s+0xfe0\(%rcx\),%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 48 3a 41 7f\s+vcvtbiasps2hf8s\s+0x1fc0\(%rcx\),%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 18 3a 01\s+vcvtbiasps2hf8s\s+\(%r9\)\{1to4\},%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 38 3a 01\s+vcvtbiasps2hf8s\s+\(%r9\)\{1to8\},%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 d5 74 58 3a 01\s+vcvtbiasps2hf8s\s+\(%r9\)\{1to16\},%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 74 09 3a c2\s+vcvtbiasps2hf8s\s+%xmm2,%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 74 89 3a c2\s+vcvtbiasps2hf8s\s+%xmm2,%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7d 08 38 c1\s+vcvtrops2hf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 28 38 c1\s+vcvtrops2hf8\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 48 38 c1\s+vcvtrops2hf8\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 08 38 41 7f\s+vcvtrops2hf8x\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 28 38 41 7f\s+vcvtrops2hf8y\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 48 38 41 7f\s+vcvtrops2hf8z\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 18 38 01\s+vcvtrops2hf8\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 38 38 01\s+vcvtrops2hf8\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 58 38 01\s+vcvtrops2hf8\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 09 38 c1\s+vcvtrops2hf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7d 89 38 c1\s+vcvtrops2hf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7d 08 3a c1\s+vcvtrops2hf8s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 28 3a c1\s+vcvtrops2hf8s\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 48 3a c1\s+vcvtrops2hf8s\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 08 3a 41 7f\s+vcvtrops2hf8sx\s+0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 28 3a 41 7f\s+vcvtrops2hf8sy\s+0xfe0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 48 3a 41 7f\s+vcvtrops2hf8sz\s+0x1fc0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 18 3a 01\s+vcvtrops2hf8s\s+\(%r9\)\{1to4\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 38 3a 01\s+vcvtrops2hf8s\s+\(%r9\)\{1to8\},%xmm0
+\s*[a-f0-9]+:\s*62 d5 7d 58 3a 01\s+vcvtrops2hf8s\s+\(%r9\)\{1to16\},%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 09 3a c1\s+vcvtrops2hf8s\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7d 89 3a c1\s+vcvtrops2hf8s\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 fc 08 36 c1\s+vcvtbf82ps\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 fc 28 36 c1\s+vcvtbf82ps\s+%xmm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 fc 48 36 c1\s+vcvtbf82ps\s+%xmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 fc 08 36 41 7f\s+vcvtbf82ps\s+0x1fc\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 fc 28 36 41 7f\s+vcvtbf82ps\s+0x3f8\(%rcx\),%ymm0
+\s*[a-f0-9]+:\s*62 f5 fc 48 36 41 7f\s+vcvtbf82ps\s+0x7f0\(%rcx\),%zmm0
+\s*[a-f0-9]+:\s*62 f5 fc 09 36 c1\s+vcvtbf82ps\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 fc 89 36 c1\s+vcvtbf82ps\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 fe 08 3d c8\s+vcvtbf82bf4s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 fe 28 3d c8\s+vcvtbf82bf4s\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 fe 48 3d c8\s+vcvtbf82bf4s\s+%zmm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 fe 08 3d 49 7f\s+vcvtbf82bf4s\s+%xmm1,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 fe 28 3d 49 7f\s+vcvtbf82bf4s\s+%ymm1,0x7f0\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 fe 48 3d 49 7f\s+vcvtbf82bf4s\s+%zmm1,0xfe0\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 7c 08 36 c1\s+vcvthf82ps\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7c 28 36 c1\s+vcvthf82ps\s+%xmm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 7c 48 36 c1\s+vcvthf82ps\s+%xmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 7c 08 36 41 7f\s+vcvthf82ps\s+0x1fc\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7c 28 36 41 7f\s+vcvthf82ps\s+0x3f8\(%rcx\),%ymm0
+\s*[a-f0-9]+:\s*62 f5 7c 48 36 41 7f\s+vcvthf82ps\s+0x7f0\(%rcx\),%zmm0
+\s*[a-f0-9]+:\s*62 f5 7c 09 36 c1\s+vcvthf82ps\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7c 89 36 c1\s+vcvthf82ps\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7e 08 3d c8\s+vcvthf82bf4s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3d c8\s+vcvthf82bf4s\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3d c8\s+vcvthf82bf4s\s+%zmm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 3d 49 7f\s+vcvthf82bf4s\s+%xmm1,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 7e 28 3d 49 7f\s+vcvthf82bf4s\s+%ymm1,0x7f0\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 7e 48 3d 49 7f\s+vcvthf82bf4s\s+%zmm1,0xfe0\(%rcx\)
+\s*[a-f0-9]+:\s*62 f5 fe 08 3e c1\s+vcvtbf82bf6s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 fe 28 3e c1\s+vcvtbf82bf6s\s+%ymm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 fe 48 3e c1\s+vcvtbf82bf6s\s+%zmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 7e 08 3c c1\s+vcvthf82hf6s\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7e 28 3c c1\s+vcvthf82hf6s\s+%ymm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 7e 48 3c c1\s+vcvthf82hf6s\s+%zmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 7c 08 37 c1\s+vcvtbf42hf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7c 28 37 c1\s+vcvtbf42hf8\s+%xmm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 7c 48 37 c1\s+vcvtbf42hf8\s+%ymm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 7c 08 37 41 7f\s+vcvtbf42hf8\s+0x3f8\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f5 7c 28 37 41 7f\s+vcvtbf42hf8\s+0x7f0\(%rcx\),%ymm0
+\s*[a-f0-9]+:\s*62 f5 7c 48 37 41 7f\s+vcvtbf42hf8\s+0xfe0\(%rcx\),%zmm0
+\s*[a-f0-9]+:\s*62 f5 7c 09 37 c1\s+vcvtbf42hf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7c 89 37 c1\s+vcvtbf42hf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 fd 08 37 c1\s+vcvtbf62hf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 fd 28 37 c1\s+vcvtbf62hf8\s+%ymm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 fd 48 37 c1\s+vcvtbf62hf8\s+%zmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 fd 09 37 c1\s+vcvtbf62hf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 fd 89 37 c1\s+vcvtbf62hf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7d 08 37 c1\s+vcvthf62hf8\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f5 7d 28 37 c1\s+vcvthf62hf8\s+%ymm1,%ymm0
+\s*[a-f0-9]+:\s*62 f5 7d 48 37 c1\s+vcvthf62hf8\s+%zmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f5 7d 09 37 c1\s+vcvthf62hf8\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f5 7d 89 37 c1\s+vcvthf62hf8\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 7e 08 41 c8\s+vpmovssdb\s+%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f2 7e 28 41 c8\s+vpmovssdb\s+%ymm1,%xmm0
+\s*[a-f0-9]+:\s*62 f2 7e 48 41 c8\s+vpmovssdb\s+%zmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f2 7e 08 41 49 7f\s+vpmovssdb\s+%xmm1,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*62 f2 7e 28 41 49 7f\s+vpmovssdb\s+%ymm1,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*62 f2 7e 48 41 49 7f\s+vpmovssdb\s+%zmm1,0x7f0\(%rcx\)
+\s*[a-f0-9]+:\s*62 f2 7e 09 41 c8\s+vpmovssdb\s+%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f2 7e 89 41 c8\s+vpmovssdb\s+%xmm1,%xmm0\{%k1\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 7c 08 3d c1 01\s+vunpackb\s+\$0x1,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f3 7c 28 3d c1 01\s+vunpackb\s+\$0x1,%ymm1,%ymm0
+\s*[a-f0-9]+:\s*62 f3 7c 48 3d c1 01\s+vunpackb\s+\$0x1,%zmm1,%zmm0
+\s*[a-f0-9]+:\s*62 f3 7c 08 3d 41 7f 01\s+vunpackb\s+\$0x1,0x7f0\(%rcx\),%xmm0
+\s*[a-f0-9]+:\s*62 f3 7c 28 3d 41 7f 01\s+vunpackb\s+\$0x1,0xfe0\(%rcx\),%ymm0
+\s*[a-f0-9]+:\s*62 f3 7c 48 3d 41 7f 01\s+vunpackb\s+\$0x1,0x1fc0\(%rcx\),%zmm0
+\s*[a-f0-9]+:\s*62 f3 7c 09 3d c1 01\s+vunpackb\s+\$0x1,%xmm1,%xmm0\{%k1\}
+\s*[a-f0-9]+:\s*62 f3 7c 89 3d c1 01\s+vunpackb\s+\$0x1,%xmm1,%xmm0\{%k1\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
new file mode 100644
index 00000000000..150c1f01b65
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
@@ -0,0 +1,211 @@ 
+# Check 64-bit AVX10 V2 AUX instructions
+
+	.arch generic64
+	.arch .avx10v2aux
+	.text
+_start:
+	.irp m, bf8, bf8s, hf8, hf8s
+	vcvtps2\m	%xmm1, %xmm0
+	vcvtps2\m	%ymm1, %xmm0
+	vcvtps2\m	%zmm1, %xmm0
+	vcvtps2\m\()x	2032(%rcx), %xmm0
+	vcvtps2\m\()y	4064(%rcx), %xmm0
+	vcvtps2\m\()z	8128(%rcx), %xmm0
+	vcvtps2\m	(%r9){1to4}, %xmm0
+	vcvtps2\m	(%r9){1to8}, %xmm0
+	vcvtps2\m	(%r9){1to16}, %xmm0
+	vcvtps2\m	%xmm1, %xmm0{%k1}
+	vcvtps2\m	%xmm1, %xmm0{%k1}{z}
+
+	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0
+	vcvtbiasps2\m	%ymm2, %ymm1, %xmm0
+	vcvtbiasps2\m	%zmm2, %zmm1, %xmm0
+	vcvtbiasps2\m	2032(%rcx), %xmm1, %xmm0
+	vcvtbiasps2\m	4064(%rcx), %ymm1, %xmm0
+	vcvtbiasps2\m	8128(%rcx), %zmm1, %xmm0
+	vcvtbiasps2\m	(%r9){1to4}, %xmm1, %xmm0
+	vcvtbiasps2\m	(%r9){1to8}, %ymm1, %xmm0
+	vcvtbiasps2\m	(%r9){1to16}, %zmm1, %xmm0
+	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0{%k1}
+	vcvtbiasps2\m	%xmm2, %xmm1, %xmm0{%k1}{z}
+	.endr
+
+	.irp m, hf8, hf8s
+	vcvtrops2\m	%xmm1, %xmm0
+	vcvtrops2\m	%ymm1, %xmm0
+	vcvtrops2\m	%zmm1, %xmm0
+	vcvtrops2\m\()x	2032(%rcx), %xmm0
+	vcvtrops2\m\()y	4064(%rcx), %xmm0
+	vcvtrops2\m\()z	8128(%rcx), %xmm0
+	vcvtrops2\m	(%r9){1to4}, %xmm0
+	vcvtrops2\m	(%r9){1to8}, %xmm0
+	vcvtrops2\m	(%r9){1to16}, %xmm0
+	vcvtrops2\m	%xmm1, %xmm0{%k1}
+	vcvtrops2\m	%xmm1, %xmm0{%k1}{z}
+	.endr
+
+	.irp f, bf, hf
+	vcvt\f\()82ps	%xmm1, %xmm0
+	vcvt\f\()82ps	%xmm1, %ymm0
+	vcvt\f\()82ps	%xmm1, %zmm0
+	vcvt\f\()82ps	508(%rcx), %xmm0
+	vcvt\f\()82ps	1016(%rcx), %ymm0
+	vcvt\f\()82ps	2032(%rcx), %zmm0
+	vcvt\f\()82ps	%xmm1, %xmm0{%k1}
+	vcvt\f\()82ps	%xmm1, %xmm0{%k1}{z}
+
+	vcvt\f\()82bf4s	%xmm1, %xmm0
+	vcvt\f\()82bf4s	%ymm1, %xmm0
+	vcvt\f\()82bf4s	%zmm1, %ymm0
+	vcvt\f\()82bf4s	%xmm1, 1016(%rcx)
+	vcvt\f\()82bf4s	%ymm1, 2032(%rcx)
+	vcvt\f\()82bf4s	%zmm1, 4064(%rcx)
+
+	.endr
+
+	vcvtbf82bf6s	%xmm1, %xmm0
+	vcvtbf82bf6s	%ymm1, %ymm0
+	vcvtbf82bf6s	%zmm1, %zmm0
+
+	vcvthf82hf6s	%xmm1, %xmm0
+	vcvthf82hf6s	%ymm1, %ymm0
+	vcvthf82hf6s	%zmm1, %zmm0
+
+	vcvtbf42hf8	%xmm1, %xmm0
+	vcvtbf42hf8	%xmm1, %ymm0
+	vcvtbf42hf8	%ymm1, %zmm0
+	vcvtbf42hf8	1016(%rcx), %xmm0
+	vcvtbf42hf8	2032(%rcx), %ymm0
+	vcvtbf42hf8	4064(%rcx), %zmm0
+	vcvtbf42hf8	%xmm1, %xmm0{%k1}
+	vcvtbf42hf8	%xmm1, %xmm0{%k1}{z}
+
+	.irp f, bf, hf
+	vcvt\f\()62hf8	%xmm1, %xmm0
+	vcvt\f\()62hf8	%ymm1, %ymm0
+	vcvt\f\()62hf8	%zmm1, %zmm0
+	vcvt\f\()62hf8	%xmm1, %xmm0{%k1}
+	vcvt\f\()62hf8	%xmm1, %xmm0{%k1}{z}
+	.endr
+
+	vpmovssdb	%xmm1, %xmm0
+	vpmovssdb	%ymm1, %xmm0
+	vpmovssdb	%zmm1, %xmm0
+	vpmovssdb	%xmm1, 508(%rcx)
+	vpmovssdb	%ymm1, 1016(%rcx)
+	vpmovssdb	%zmm1, 2032(%rcx)
+	vpmovssdb	%xmm1, %xmm0{%k1}
+	vpmovssdb	%xmm1, %xmm0{%k1}{z}
+
+	vunpackb	$1, %xmm1, %xmm0
+	vunpackb	$1, %ymm1, %ymm0
+	vunpackb	$1, %zmm1, %zmm0
+	vunpackb	$1, 2032(%rcx), %xmm0
+	vunpackb	$1, 4064(%rcx), %ymm0
+	vunpackb	$1, 8128(%rcx), %zmm0
+	vunpackb	$1, %xmm1, %xmm0{%k1}
+	vunpackb	$1, %xmm1, %xmm0{%k1}{z}
+
+_intel:
+	.intel_syntax noprefix
+
+	.irp m, bf8, bf8s, hf8, hf8s
+	vcvtps2\m	xmm0, xmm1
+	vcvtps2\m	xmm0, ymm1
+	vcvtps2\m	xmm0, zmm1
+	vcvtps2\m	xmm0, XMMWORD PTR [rcx+2032]
+	vcvtps2\m	xmm0, YMMWORD PTR [rcx+4064]
+	vcvtps2\m	xmm0, ZMMWORD PTR [rcx+8128]
+	vcvtps2\m	xmm0, DWORD PTR [r9]{1to4}
+	vcvtps2\m	xmm0, DWORD PTR [r9]{1to8}
+	vcvtps2\m	xmm0, DWORD PTR [r9]{1to16}
+	vcvtps2\m	xmm0{k1}, xmm1
+	vcvtps2\m	xmm0{k1}{z}, xmm1
+
+	vcvtbiasps2\m	xmm0, xmm1, xmm2
+	vcvtbiasps2\m	xmm0, ymm1, ymm2
+	vcvtbiasps2\m	xmm0, zmm1, zmm2
+	vcvtbiasps2\m	xmm0, xmm1, XMMWORD PTR [rcx+2032]
+	vcvtbiasps2\m	xmm0, ymm1, YMMWORD PTR [rcx+4064]
+	vcvtbiasps2\m	xmm0, zmm1, ZMMWORD PTR [rcx+8128]
+	vcvtbiasps2\m	xmm0, xmm1, DWORD PTR [r9]{1to4}
+	vcvtbiasps2\m	xmm0, ymm1, DWORD PTR [r9]{1to8}
+	vcvtbiasps2\m	xmm0, zmm1, DWORD PTR [r9]{1to16}
+	vcvtbiasps2\m	xmm0{k1}, xmm1, xmm2
+	vcvtbiasps2\m	xmm0{k1}{z}, xmm1, xmm2
+	.endr
+
+	.irp m, hf8, hf8s
+	vcvtrops2\m	xmm0, xmm1
+	vcvtrops2\m	xmm0, ymm1
+	vcvtrops2\m	xmm0, zmm1
+	vcvtrops2\m	xmm0, XMMWORD PTR [rcx+2032]
+	vcvtrops2\m	xmm0, YMMWORD PTR [rcx+4064]
+	vcvtrops2\m	xmm0, ZMMWORD PTR [rcx+8128]
+	vcvtrops2\m	xmm0, DWORD PTR [r9]{1to4}
+	vcvtrops2\m	xmm0, DWORD PTR [r9]{1to8}
+	vcvtrops2\m	xmm0, DWORD PTR [r9]{1to16}
+	vcvtrops2\m	xmm0{k1}, xmm1
+	vcvtrops2\m	xmm0{k1}{z}, xmm1
+	.endr
+
+	.irp f, bf, hf
+	vcvt\f\()82ps	xmm0, xmm1
+	vcvt\f\()82ps	ymm0, xmm1
+	vcvt\f\()82ps	zmm0, xmm1
+	vcvt\f\()82ps	xmm0, DWORD PTR [rcx+508]
+	vcvt\f\()82ps	ymm0, QWORD PTR [rcx+1016]
+	vcvt\f\()82ps	zmm0, XMMWORD PTR [rcx+2032]
+	vcvt\f\()82ps	xmm0{k1}, xmm1
+	vcvt\f\()82ps	xmm0{k1}{z}, xmm1
+
+	vcvt\f\()82bf4s	xmm0, xmm1
+	vcvt\f\()82bf4s	xmm0, ymm1
+	vcvt\f\()82bf4s	ymm0, zmm1
+	vcvt\f\()82bf4s	QWORD PTR [rcx+1016], xmm1
+	vcvt\f\()82bf4s	XMMWORD PTR [rcx+2032], ymm1
+	vcvt\f\()82bf4s	YMMWORD PTR [rcx+4064], zmm1
+	.endr
+
+	vcvtbf82bf6s	xmm0, xmm1
+	vcvtbf82bf6s	ymm0, ymm1
+	vcvtbf82bf6s	zmm0, zmm1
+
+	vcvthf82hf6s	xmm0, xmm1
+	vcvthf82hf6s	ymm0, ymm1
+	vcvthf82hf6s	zmm0, zmm1
+
+	vcvtbf42hf8	xmm0, xmm1
+	vcvtbf42hf8	ymm0, xmm1
+	vcvtbf42hf8	zmm0, ymm1
+	vcvtbf42hf8	xmm0, QWORD PTR [rcx+1016]
+	vcvtbf42hf8	ymm0, XMMWORD PTR [rcx+2032]
+	vcvtbf42hf8	zmm0, YMMWORD PTR [rcx+4064]
+	vcvtbf42hf8	xmm0{k1}, xmm1
+	vcvtbf42hf8	xmm0{k1}{z}, xmm1
+
+	.irp f, bf, hf
+	vcvt\f\()62hf8	xmm0, xmm1
+	vcvt\f\()62hf8	ymm0, ymm1
+	vcvt\f\()62hf8	zmm0, zmm1
+	vcvt\f\()62hf8	xmm0{k1}, xmm1
+	vcvt\f\()62hf8	xmm0{k1}{z}, xmm1
+	.endr
+
+	vpmovssdb	xmm0, xmm1
+	vpmovssdb	xmm0, ymm1
+	vpmovssdb	xmm0, zmm1
+	vpmovssdb	DWORD PTR [rcx+508], xmm1
+	vpmovssdb	QWORD PTR [rcx+1016], ymm1
+	vpmovssdb	XMMWORD PTR [rcx+2032], zmm1
+	vpmovssdb	xmm0{k1}, xmm1
+	vpmovssdb	xmm0{k1}{z}, xmm1
+
+	vunpackb	xmm0, xmm1, 1
+	vunpackb	ymm0, ymm1, 1
+	vunpackb	zmm0, zmm1, 1
+	vunpackb	xmm0, XMMWORD PTR [rcx+2032], 1
+	vunpackb	ymm0, YMMWORD PTR [rcx+4064], 1
+	vunpackb	zmm0, ZMMWORD PTR [rcx+8128], 1
+	vunpackb	xmm0{k1}, xmm1, 1
+	vunpackb	xmm0{k1}{z}, xmm1, 1
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 710f749a8dc..fee205b9659 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -527,6 +527,8 @@  run_dump_test "x86-64-avx10_2-256-sm4-intel"
 run_dump_test "x86-64-avx10_2-512-sm4"
 run_dump_test "x86-64-avx10_2-512-sm4-intel"
 run_list_test "x86-64-avx10_2-sm4-inval"
+run_dump_test "x86-64-avx10_v2_aux"
+run_dump_test "x86-64-avx10_v2_aux-intel"
 run_dump_test "x86-64-amx-transpose"
 run_dump_test "x86-64-amx-transpose-intel"
 run_list_test "x86-64-amx-transpose-inval"
diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h
index 3a1e0f9b0ea..ed9524b0658 100644
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -18,3 +18,18 @@ 
     { "enqcmd",		{ Gva, M }, 0 },
     { VEX_W_TABLE (EVEX_W_MAP4_F8_P3_M_1) },
   },
+  /* MOD_EVEX_MAP5_37_P_2 */
+  {
+    { Bad_Opcode },
+    { "vcvt%XF62hf8",	{ XM, EXx }, 0 },
+  },
+  /* MOD_EVEX_MAP5_3C_W_0_P_1 */
+  {
+    { Bad_Opcode },
+    { "vcvthf82hf6s",	{ XM, EXx }, 0 },
+  },
+  /* MOD_EVEX_MAP5_3E_W_1_P_1 */
+  {
+    { Bad_Opcode },
+    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
+  },
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 1aeac210c5d..65479b45f09 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -243,6 +243,11 @@ 
     { VEX_W_TABLE (EVEX_W_0F383A_P_1) },
     { "%XEvpminuw",	{ XM, Vex, EXx }, 0 },
   },
+  /* PREFIX_EVEX_0F3841_W_0 */
+  {
+    { Bad_Opcode },
+    { "vpmovssdb",	{ EXxmmqd, XM }, 0 },
+  },
   /* PREFIX_EVEX_0F384A_W_0_L_2 */
   {
     { Bad_Opcode },
@@ -614,6 +619,53 @@ 
     { Bad_Opcode },
     { "vmovrs%BW",	{ XM, Mx }, 0 },
   },
+  /* PREFIX_EVEX_MAP5_36 */
+  {
+    { "vcvt%XF82ps",	{ XM, EXxmmqd }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_37 */
+  {
+    { VEX_W_TABLE (EVEX_W_MAP5_37_P_0) },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_EVEX_MAP5_37_P_2) },
+  },
+  /* PREFIX_EVEX_MAP5_38_W_0 */
+  {
+    { "vcvtbiasps2hf8",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2hf8%XZ",	{ XMM, EXx }, 0 },
+    { "vcvtrops2hf8%XZ",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_39_W_0 */
+  {
+    { "vcvtbiasps2bf8",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2bf8%XZ",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3A_W_0 */
+  {
+    { "vcvtbiasps2hf8s",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2hf8s%XZ",	{ XMM, EXx }, 0 },
+    { "vcvtrops2hf8s%XZ",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3B_W_0 */
+  {
+    { "vcvtbiasps2bf8s",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2bf8s%XZ",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3C_W_0 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_EVEX_MAP5_3C_W_0_P_1) },
+  },
+  /* PREFIX_EVEX_MAP5_3D */
+  {
+    { Bad_Opcode },
+    { "vcvt%XF82bf4s",	{ EXxmmq, XM }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3E_W_1 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_EVEX_MAP5_3E_W_1_P_1) },
+  },
   /* PREFIX_EVEX_MAP5_74 */
   {
     { "vcvtbiasp%XH2bf8s",	{ XMxmmq, Vex, EXxh }, 0 },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 310f121f499..71992a61137 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -346,6 +346,11 @@ 
   {
     { "vpbroadcastmw2dY",	{ XM, MaskR }, 0 },
   },
+  /* EVEX_W_0F3841 */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_0F3841_W_0) },
+    { Bad_Opcode },
+  },
   /* EVEX_W_0F384A_X86_64 */
   {
     { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) },
@@ -445,6 +450,11 @@ 
     { "vextracti32x8",	{ EXymm, XM, Ib }, PREFIX_DATA },
     { "vextracti64x4",	{ EXymm, XM, Ib }, PREFIX_DATA },
   },
+  /* EVEX_W_0F3A3D */
+  {
+    { "vunpackb",	{ XM, EXEvexXNoBcst, Ib }, NO_PREFIX },
+    { Bad_Opcode },
+  },
   /* EVEX_W_0F3A42 */
   {
     { PREFIX_TABLE (PREFIX_EVEX_0F3A42_W_0) },
@@ -486,6 +496,41 @@ 
     { "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
     { "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
   },
+  /* EVEX_W_MAP5_37_P_0 */
+  {
+    { "vcvtbf42hf8",	{ XM, EXxmmq }, 0 },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_38 */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_38_W_0) },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_39 */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_39_W_0) },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_3A */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3A_W_0) },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_3B */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3B_W_0) },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_3C */
+  {
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3C_W_0) },
+    { Bad_Opcode },
+  },
+  /* EVEX_W_MAP5_3E */
+  {
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3E_W_1) },
+  },
   /* EVEX_W_MAP5_5B_P_0 */
   {
     { "vcvtdq2ph%XY",	{ XMxmmq, EXx, EXxEVexR }, 0 },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index b2f02e494f9..fe515a01932 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -366,7 +366,7 @@  static const struct dis386 evex_table[][256] = {
     { "%XEvpmaxu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* 40 */
     { "%XEvpmull%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_0F3841) },
     { "vgetexpp%XW",	{ XM, EXx, EXxEVexS }, PREFIX_DATA },
     { "vgetexps%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
     { "vplzcnt%DQ",	{ XM, EXx }, PREFIX_DATA },
@@ -652,7 +652,7 @@  static const struct dis386 evex_table[][256] = {
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3A) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_0F3A3D) },
     { "vpcmpu%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     { "vpcmp%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     /* 40 */
@@ -1226,16 +1226,16 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_36) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_37) },
     /* 38 */
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP5_38) },
+    { VEX_W_TABLE (EVEX_W_MAP5_39) },
+    { VEX_W_TABLE (EVEX_W_MAP5_3A) },
+    { VEX_W_TABLE (EVEX_W_MAP5_3B) },
+    { VEX_W_TABLE (EVEX_W_MAP5_3C) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3D) },
+    { VEX_W_TABLE (EVEX_W_MAP5_3E) },
     { Bad_Opcode },
     /* 40 */
     { Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 23818dd6939..4800f43c1dc 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -976,6 +976,10 @@  enum
   MOD_EVEX_MAP4_61,
   MOD_EVEX_MAP4_F8_P_1,
   MOD_EVEX_MAP4_F8_P_3,
+
+  MOD_EVEX_MAP5_37_P_2,
+  MOD_EVEX_MAP5_3C_W_0_P_1,
+  MOD_EVEX_MAP5_3E_W_1_P_1,
 };
 
 enum
@@ -1211,6 +1215,7 @@  enum
   PREFIX_EVEX_0F3838,
   PREFIX_EVEX_0F3839,
   PREFIX_EVEX_0F383A,
+  PREFIX_EVEX_0F3841_W_0,
   PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
@@ -1272,6 +1277,15 @@  enum
   PREFIX_EVEX_MAP5_6D,
   PREFIX_EVEX_MAP5_6E_L_0,
   PREFIX_EVEX_MAP5_6F_X86_64,
+  PREFIX_EVEX_MAP5_36,
+  PREFIX_EVEX_MAP5_37,
+  PREFIX_EVEX_MAP5_38_W_0,
+  PREFIX_EVEX_MAP5_39_W_0,
+  PREFIX_EVEX_MAP5_3A_W_0,
+  PREFIX_EVEX_MAP5_3B_W_0,
+  PREFIX_EVEX_MAP5_3C_W_0,
+  PREFIX_EVEX_MAP5_3D,
+  PREFIX_EVEX_MAP5_3E_W_1,
   PREFIX_EVEX_MAP5_74,
   PREFIX_EVEX_MAP5_78,
   PREFIX_EVEX_MAP5_79,
@@ -1827,6 +1841,7 @@  enum
   EVEX_W_0F3835_P_2,
   EVEX_W_0F3837,
   EVEX_W_0F383A_P_1,
+  EVEX_W_0F3841,
   EVEX_W_0F384A_X86_64,
   EVEX_W_0F3859,
   EVEX_W_0F385A_L_n,
@@ -1849,6 +1864,7 @@  enum
   EVEX_W_0F3A39_L_n,
   EVEX_W_0F3A3A_L_2,
   EVEX_W_0F3A3B_L_2,
+  EVEX_W_0F3A3D,
   EVEX_W_0F3A42,
   EVEX_W_0F3A43_L_n,
   EVEX_W_0F3A70,
@@ -1860,6 +1876,13 @@  enum
   EVEX_W_MAP4_F8_P3_M_1,
   EVEX_W_MAP4_FF_R_6,
 
+  EVEX_W_MAP5_37_P_0,
+  EVEX_W_MAP5_38,
+  EVEX_W_MAP5_39,
+  EVEX_W_MAP5_3A,
+  EVEX_W_MAP5_3B,
+  EVEX_W_MAP5_3C,
+  EVEX_W_MAP5_3E,
   EVEX_W_MAP5_5B_P_0,
   EVEX_W_MAP5_6C_P_0,
   EVEX_W_MAP5_6C_P_2,
@@ -1935,6 +1958,7 @@  struct dis386 {
    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
    "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding
 	   (for BF16)
+   "XF" => print 'hf' if EVEX.W=0 or 'bf' if EVEX.W=1
    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
    "XV" => print "{vex} " pseudo prefix
    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
@@ -11075,6 +11099,8 @@  putop (instr_info *ins, const char *in_template, int sizeflag)
 		  ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
 		}
 	    }
+	  else if (l == 1 && last[0] == 'X')
+	    oappend (ins, ins->vex.w ? "bf" : "hf");
 	  else if (l == 1 && last[0] == 'C')
 	    {
 	      if (ins->vex.nd && !ins->vex.nf)
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 3fadc33a763..b8d7ad2b0b1 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -251,6 +251,8 @@  static const dependency isa_dependencies[] =
     "AVX10_1" },
   { "AVX10_2",
     "AVX10_1_AUX" },
+  { "AVX10_V2_AUX",
+    "AVX10_1" },
   { "SEV_ES",
     "SVME" },
   { "SNP",
@@ -454,6 +456,7 @@  static bitfield cpu_flags[] =
   BITFIELD (APX_F),
   BITFIELD (AVX10_1_AUX),
   BITFIELD (AVX10_2),
+  BITFIELD (AVX10_V2_AUX),
   BITFIELD (MOVRS),
   BITFIELD (MWAITX),
   BITFIELD (CLZERO),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0dbb4ce1e35..e4cbe8c9ca4 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -332,6 +332,8 @@  enum i386_cpu
   CpuAPX_NDD,
   /* Intel APX No-Flags-update support required.  */
   CpuAPX_NF,
+  /* AVX10 V2 Auxiliary Instructions support required.  */
+  CpuAVX10_V2_AUX,
 
   /* NOTE: These items, which can be combined with other ISA flags above, need
      to remain second to last and in sync with CPU_FLAGS_COMMON. */
@@ -573,6 +575,7 @@  typedef union i386_cpu_flags
       unsigned int cpuapx_nci:1;
       unsigned int cpuapx_ndd:1;
       unsigned int cpuapx_nf:1;
+      unsigned int cpuavx10_v2_aux:1;
       CPU_FLAGS_COMMON;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 557a9b2defb..1ded63d9fd3 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2266,6 +2266,13 @@  vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDY
     x:AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, +
     y:AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM>
 
+<Exyz:attr:src, +
+    $i:Disp8ShiftVL|IntelSyntax:RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, +
+    $a:Disp8ShiftVL|ATTSyntax:RegXMM|RegYMM|RegZMM|BaseIndex, +
+    x:EVex128|Disp8MemShift=4|ATTSyntax:RegXMM|Unspecified|BaseIndex, +
+    y:EVex256|Disp8MemShift=5|ATTSyntax:RegYMM|Unspecified|BaseIndex, +
+    z:EVex512|Disp8MemShift=6|ATTSyntax:RegZMM|Unspecified|BaseIndex>
+
 kand<bw>, 0x<bw:kpfx>41, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
 kandn<bw>, 0x<bw:kpfx>42, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
 kor<bw>, 0x<bw:kpfx>45, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
@@ -3614,6 +3621,62 @@  vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
 
 // AVX10.2 instructions end.
 
+// AVX10_V2_AUX instructions.
+
+<cvtps8:opc, +
+    bf8:39, +
+    bf8s:3b, +
+    hf8:38, +
+    hf8s:3a>
+
+vcvtps2<cvtps8><Exyz>, 0xf3<cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|<Exyz:attr>|VexW0|Masking|Broadcast|NoSuf, { <Exyz:src>|Dword, RegXMM }
+
+vcvtbiasps2<cvtps8>, 0x<cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM }
+
+<cvtps8>
+
+<cvtrops8:opc, +
+    hf8:38, +
+    hf8s:3a>
+
+vcvtrops2<cvtrops8><Exyz>, 0x66<cvtrops8:opc>, AVX10_V2_AUX, Modrm|Map5|<Exyz:attr>|VexW0|Masking|Broadcast|NoSuf, { <Exyz:src>|Dword, RegXMM }
+
+<cvtrops8>
+
+<fp:vexw, +
+    hf:VexW0, +
+    bf:VexW1>
+
+vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex128|<fp:vexw>|Masking|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex256|<fp:vexw>|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vcvt<fp>82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex512|<fp:vexw>|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
+
+vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex128|<fp:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
+vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex256|<fp:vexw>|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
+vcvt<fp>82bf4s, 0xf33d, AVX10_V2_AUX, RegMem|Map5|EVex512|<fp:vexw>|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
+
+<fp>
+
+vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|EVexDYN|Map5|VexW1|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|EVexDYN|Map5|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
+
+vcvtbf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW1|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+vcvthf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW0|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex128|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex256|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
+
+vunpackb, 0x3d, AVX10_V2_AUX, Modrm|Masking|Space0F3A|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+
+// AVX10_V2_AUX instructions end.
+
 // MOVRS instructions.
 
 prefetchrst2, 0xf18/4, MOVRS, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }