From patchwork Tue Jun 30 08:11:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 138121 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5F6E14BA2E2E for ; Tue, 30 Jun 2026 08:12:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5F6E14BA2E2E Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QN1pG3Ov X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by sourceware.org (Postfix) with ESMTPS id BA85C4BA5435 for ; Tue, 30 Jun 2026 08:11:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BA85C4BA5435 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BA85C4BA5435 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782807090; cv=none; b=roY6oE82xxA3tH7oJKuhbCvceRmuZIGbr7+DBVhcnF6iHG1EFFIpYeYIOYGa6i/DLzHy8XOEPU0HvRnZpdWsScErcck/gDw8eNNd0HVrYDevoTufOZA8zlhoSEumoZ3oWsgyPnetcxwg6pB3i3+989bRdoqRyrf5486ca1EAa3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782807090; c=relaxed/simple; bh=WTOY5rt+nke2w1LOp2NkTcPU2mGv6ZNdBPh17Xn6OWQ=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ka71SCb9rbtKya4/pTX512DKX4etg4XNUv6jCR/gI2kvfyFvgxvZYKyTGhpkWfjOk/81y2HbbFR+HVk9biWC8AVjnBek49qeuSzjkqgQ8nCwfPU3ytLNslE1Dg7aiKlzsnlkWKRqvhvo1goTrJkxUlW+W+vnqjv6NfP+PJ3BD/M= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QN1pG3Ov DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BA85C4BA5435 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782807090; x=1814343090; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=WTOY5rt+nke2w1LOp2NkTcPU2mGv6ZNdBPh17Xn6OWQ=; b=QN1pG3OvC6W7LgdNEJbOg0bmKA2qdmHh+CkuyA3SMwKCZDVf4h/I6nc2 EPBY1LjWSfWRS6PVGV7S7Jl+W/gtPHj0gjFF4euWmEKkeVUoEjeTZBSp6 C7VoCg9gSyv9fIWrSocTytAC6Wfn9RcuyW1Yqi1FVI3HQ+LtYHTYITgmA gqzK+Kftn+lb/mMqgtPULtyGhB4BDXyMGwsrpJJhKEJJBbe4pEkIQBBu+ lUEK/xrUPClN+8IL6zDaDeJPMHCf8S7V/QpJvAoJRuyO5tAVDdPYSjEoJ qOvijMtZmJJ3UHjG2+nB5unBVLjYrW/lUeTuIMkTRErCpwYHL18U5A8xc A==; X-CSE-ConnectionGUID: C5TGizmYQw+d1HRuZBeswA== X-CSE-MsgGUID: tBDfQfZGQVGa9kDNYIHhVw== X-IronPort-AV: E=McAfee;i="6800,10657,11832"; a="82502292" X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="82502292" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 01:11:29 -0700 X-CSE-ConnectionGUID: DYv4xb6zTZKIfvakDfVdbA== X-CSE-MsgGUID: 2xgdwsSQSoidQebDFVWiIw== X-ExtLoop1: 1 Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by fmviesa003.fm.intel.com with ESMTP; 30 Jun 2026 01:11:27 -0700 From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com Subject: [PATCH] x86: Disable AMX-TF32 by default Date: Tue, 30 Jun 2026 16:11:26 +0800 Message-Id: <20260630081126.3508651-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Hi all, AMX-TF32 got depublished in ISE062. Just like AMX-TRANSPOSE, we will keep the AMX-TF32 support for now in case there are x86 vendors want to utilize the feature. AMX-TF32 will not show up on any Intel/AMD hardware. Also in foreseeable future, no hardware will support AMX-TF32, we will disable it by default. For testcases, we will simply add .arch .amx_tf32 to keep the original test intuition. Tested on x86-64. Ok for trunk? Thx, Haochen gas/ChangeLog: * testsuite/gas/i386/x86-64-amx-tf32.s: Add .amx_tf32. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Adjust line number. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. opcodes/ChangeLog: * i386-gen.c: Disable AMX-TF32 by default. * i386-init.h: Regenerated. --- .../gas/i386/x86-64-amx-tf32-inval.l | 2 +- .../gas/i386/x86-64-amx-tf32-inval.s | 1 + gas/testsuite/gas/i386/x86-64-amx-tf32.s | 1 + .../gas/i386/x86-64-amx-transpose-inval.l | 24 +++++++++---------- .../gas/i386/x86-64-amx-transpose-inval.s | 1 + gas/testsuite/gas/i386/x86-64-amx-transpose.s | 1 + opcodes/i386-gen.c | 2 +- opcodes/i386-init.h | 2 +- 8 files changed, 19 insertions(+), 15 deletions(-) diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l index 2ac207f90ca..81db933e346 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l +++ b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l @@ -1,4 +1,4 @@ .* Assembler messages: -.*:5: Error: all tmm registers must be distinct for `tmmultf32ps' .*:6: Error: all tmm registers must be distinct for `tmmultf32ps' .*:7: Error: all tmm registers must be distinct for `tmmultf32ps' +.*:8: Error: all tmm registers must be distinct for `tmmultf32ps' diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s index 7357c3c392f..c7b4538e300 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s +++ b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s @@ -1,6 +1,7 @@ # Check Illegal 64bit AMX-TF32 instructions .text + .arch .amx_tf32 _start: tmmultf32ps %tmm1, %tmm1, %tmm2 tmmultf32ps %tmm1, %tmm2, %tmm1 diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32.s b/gas/testsuite/gas/i386/x86-64-amx-tf32.s index bb82380da48..c7a4667b04f 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-tf32.s +++ b/gas/testsuite/gas/i386/x86-64-amx-tf32.s @@ -1,6 +1,7 @@ # Check 64bit AMX-TF32 instructions .text + .arch .amx_tf32 _start: tmmultf32ps %tmm4, %tmm5, %tmm6 tmmultf32ps %tmm1, %tmm2, %tmm3 diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l index 02ad60d8343..406be53fa2c 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l +++ b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l @@ -4,16 +4,15 @@ .*:7: Error: `t2rpntlvwz1rs' is not supported on `x86_64' .*:8: Error: `t2rpntlvwz1rst1' is not supported on `x86_64' .*:9: Error: `ttmmultf32ps' is not supported on `x86_64' -.*:13: Error: all tmm registers must be distinct for `ttdpbf16ps' .*:14: Error: all tmm registers must be distinct for `ttdpbf16ps' .*:15: Error: all tmm registers must be distinct for `ttdpbf16ps' -.*:16: Error: all tmm registers must be distinct for `ttdpfp16ps' +.*:16: Error: all tmm registers must be distinct for `ttdpbf16ps' .*:17: Error: all tmm registers must be distinct for `ttdpfp16ps' .*:18: Error: all tmm registers must be distinct for `ttdpfp16ps' -.*:19: Error: all tmm registers must be distinct for `ttmmultf32ps' +.*:19: Error: all tmm registers must be distinct for `ttdpfp16ps' .*:20: Error: all tmm registers must be distinct for `ttmmultf32ps' .*:21: Error: all tmm registers must be distinct for `ttmmultf32ps' -.*:22: Error: `\(%rip\)' cannot be used here +.*:22: Error: all tmm registers must be distinct for `ttmmultf32ps' .*:23: Error: `\(%rip\)' cannot be used here .*:24: Error: `\(%rip\)' cannot be used here .*:25: Error: `\(%rip\)' cannot be used here @@ -21,11 +20,12 @@ .*:27: Error: `\(%rip\)' cannot be used here .*:28: Error: `\(%rip\)' cannot be used here .*:29: Error: `\(%rip\)' cannot be used here -.*:30: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0' -.*:31: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1' -.*:32: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1' -.*:33: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1' -.*:34: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs' -.*:35: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1' -.*:36: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs' -.*:37: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1' +.*:30: Error: `\(%rip\)' cannot be used here +.*:31: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0' +.*:32: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1' +.*:33: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1' +.*:34: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1' +.*:35: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs' +.*:36: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1' +.*:37: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs' +.*:38: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1' diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s index 7bbc1babb17..a2d8d3818b4 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s +++ b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s @@ -9,6 +9,7 @@ _start: ttmmultf32ps %tmm1, %tmm2, %tmm3 .arch .amx_transpose + .arch .amx_tf32 _transpose: ttdpbf16ps %tmm1, %tmm1, %tmm2 ttdpbf16ps %tmm1, %tmm2, %tmm1 diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose.s b/gas/testsuite/gas/i386/x86-64-amx-transpose.s index ef4a72a0cae..885a1a68391 100644 --- a/gas/testsuite/gas/i386/x86-64-amx-transpose.s +++ b/gas/testsuite/gas/i386/x86-64-amx-transpose.s @@ -1,6 +1,7 @@ # Check 64bit AMX-TRANSPOSE instructions .arch .amx_transpose + .arch .amx_tf32 .text _start: ttdpbf16ps %tmm4, %tmm5, %tmm6 diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index be580d48a18..dd8f936edcd 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -47,7 +47,7 @@ typedef struct dependency static const dependency isa_dependencies[] = { { "UNKNOWN", - "~(IAMCU|MPX|AMX_TRANSPOSE)" }, + "~(IAMCU|MPX|AMX_TRANSPOSE|AMX_TF32)" }, { "GENERIC32", "386" }, { "GENERIC64",