RISC-V: Add support for ziccamoc extension.
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Commit Message
This patch adds minimal support for the RISC-V Ziccamoc extension, version 1.0[1].
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccamoc.adoc
bfd/ChangeLog:
* elfxx-riscv.c: Add ziccamoc extension.
gas/ChangeLog:
* NEWS: Add ziccamoc extension.
* testsuite/gas/riscv/march-help.l: Ditto.
---
bfd/elfxx-riscv.c | 1 +
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
3 files changed, 4 insertions(+)
--
2.34.1
@@ -1458,6 +1458,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
{"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccamoc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -11,6 +11,8 @@
* Add support for RISC-V vendor extensions:
SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.
+* Add support for RISC-V ziccamoc extension with version 1.0.
+
Changes in 2.46:
* Add support for AMD Zen6 processor.
@@ -12,6 +12,7 @@ All available -march extensions for RISC-V:
h 1.0
zic64b 1.0
ziccamoa 1.0
+ ziccamoc 1.0
ziccif 1.0
zicclsm 1.0
ziccrse 1.0