@@ -327,12 +327,12 @@ DESCRIPTION
.#define bfd_mach_arm_6M 20
.#define bfd_mach_arm_6SM 21
.#define bfd_mach_arm_7EM 22
-.#define bfd_mach_arm_8 23
+.#define bfd_mach_arm_8A 23
.#define bfd_mach_arm_8R 24
.#define bfd_mach_arm_8M_BASE 25
.#define bfd_mach_arm_8M_MAIN 26
.#define bfd_mach_arm_8_1M_MAIN 27
-.#define bfd_mach_arm_9 28
+.#define bfd_mach_arm_9A 28
. bfd_arch_nds32, {* Andes NDS32. *}
.#define bfd_mach_n1 1
.#define bfd_mach_n1h 2
@@ -1571,12 +1571,12 @@ enum bfd_architecture
#define bfd_mach_arm_6M 20
#define bfd_mach_arm_6SM 21
#define bfd_mach_arm_7EM 22
-#define bfd_mach_arm_8 23
+#define bfd_mach_arm_8A 23
#define bfd_mach_arm_8R 24
#define bfd_mach_arm_8M_BASE 25
#define bfd_mach_arm_8M_MAIN 26
#define bfd_mach_arm_8_1M_MAIN 27
-#define bfd_mach_arm_9 28
+#define bfd_mach_arm_9A 28
bfd_arch_nds32, /* Andes NDS32. */
#define bfd_mach_n1 1
#define bfd_mach_n1h 2
@@ -139,20 +139,20 @@ processors[] =
{ bfd_mach_arm_7, "cortex-a12" },
{ bfd_mach_arm_7, "cortex-a15" },
{ bfd_mach_arm_7, "cortex-a17" },
- { bfd_mach_arm_8, "cortex-a32" },
- { bfd_mach_arm_8, "cortex-a35" },
- { bfd_mach_arm_8, "cortex-a53" },
- { bfd_mach_arm_8, "cortex-a55" },
- { bfd_mach_arm_8, "cortex-a57" },
- { bfd_mach_arm_8, "cortex-a72" },
- { bfd_mach_arm_8, "cortex-a73" },
- { bfd_mach_arm_8, "cortex-a75" },
- { bfd_mach_arm_8, "cortex-a76" },
- { bfd_mach_arm_8, "cortex-a76ae" },
- { bfd_mach_arm_8, "cortex-a77" },
- { bfd_mach_arm_8, "cortex-a78" },
- { bfd_mach_arm_8, "cortex-a78ae" },
- { bfd_mach_arm_8, "cortex-a78c" },
+ { bfd_mach_arm_8A, "cortex-a32" },
+ { bfd_mach_arm_8A, "cortex-a35" },
+ { bfd_mach_arm_8A, "cortex-a53" },
+ { bfd_mach_arm_8A, "cortex-a55" },
+ { bfd_mach_arm_8A, "cortex-a57" },
+ { bfd_mach_arm_8A, "cortex-a72" },
+ { bfd_mach_arm_8A, "cortex-a73" },
+ { bfd_mach_arm_8A, "cortex-a75" },
+ { bfd_mach_arm_8A, "cortex-a76" },
+ { bfd_mach_arm_8A, "cortex-a76ae" },
+ { bfd_mach_arm_8A, "cortex-a77" },
+ { bfd_mach_arm_8A, "cortex-a78" },
+ { bfd_mach_arm_8A, "cortex-a78ae" },
+ { bfd_mach_arm_8A, "cortex-a78c" },
{ bfd_mach_arm_6SM, "cortex-m0" },
{ bfd_mach_arm_6SM, "cortex-m0plus" },
{ bfd_mach_arm_6SM, "cortex-m1" },
@@ -166,13 +166,13 @@ processors[] =
{ bfd_mach_arm_7, "cortex-r4f" },
{ bfd_mach_arm_7, "cortex-r5" },
{ bfd_mach_arm_8R, "cortex-r52" },
- { bfd_mach_arm_8R, "cortex-r52plus" },
+ { bfd_mach_arm_8R, "cortex-r52plus" },
{ bfd_mach_arm_7, "cortex-r7" },
{ bfd_mach_arm_7, "cortex-r8" },
- { bfd_mach_arm_8, "cortex-x1" },
- { bfd_mach_arm_8, "cortex-x1c" },
+ { bfd_mach_arm_8A, "cortex-x1" },
+ { bfd_mach_arm_8A, "cortex-x1c" },
{ bfd_mach_arm_4T, "ep9312" },
- { bfd_mach_arm_8, "exynos-m1" },
+ { bfd_mach_arm_8A, "exynos-m1" },
{ bfd_mach_arm_4, "fa526" },
{ bfd_mach_arm_5TE, "fa606te" },
{ bfd_mach_arm_5TE, "fa616te" },
@@ -192,9 +192,9 @@ processors[] =
{ bfd_mach_arm_4, "strongarm1100" },
{ bfd_mach_arm_4, "strongarm1110" },
{ bfd_mach_arm_XScale, "xscale" },
- { bfd_mach_arm_8, "xgene1" },
- { bfd_mach_arm_8, "xgene2" },
- { bfd_mach_arm_9, "cortex-a710" },
+ { bfd_mach_arm_8A, "xgene1" },
+ { bfd_mach_arm_8A, "xgene2" },
+ { bfd_mach_arm_9A, "cortex-a710" },
{ bfd_mach_arm_iWMMXt, "iwmmxt" },
{ bfd_mach_arm_iWMMXt2, "iwmmxt2" },
{ bfd_mach_arm_unknown, "arm_any" }
@@ -262,12 +262,12 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_arm_6M, "armv6-m", false, & arch_info_struct[19]),
N (bfd_mach_arm_6SM, "armv6s-m", false, & arch_info_struct[20]),
N (bfd_mach_arm_7EM, "armv7e-m", false, & arch_info_struct[21]),
- N (bfd_mach_arm_8, "armv8-a", false, & arch_info_struct[22]),
+ N (bfd_mach_arm_8A, "armv8-a", false, & arch_info_struct[22]),
N (bfd_mach_arm_8R, "armv8-r", false, & arch_info_struct[23]),
N (bfd_mach_arm_8M_BASE, "armv8-m.base", false, & arch_info_struct[24]),
N (bfd_mach_arm_8M_MAIN, "armv8-m.main", false, & arch_info_struct[25]),
N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", false, & arch_info_struct[26]),
- N (bfd_mach_arm_9, "armv9-a", false, & arch_info_struct[27]),
+ N (bfd_mach_arm_9A, "armv9-a", false, & arch_info_struct[27]),
N (bfd_mach_arm_unknown, "arm_any", false, NULL)
};
@@ -3876,7 +3876,7 @@ using_thumb2 (struct elf32_arm_link_hash_table *globals)
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V7
|| arch == TAG_CPU_ARCH_V7E_M
- || arch == TAG_CPU_ARCH_V8
+ || arch == TAG_CPU_ARCH_V8A
|| arch == TAG_CPU_ARCH_V8R
|| arch == TAG_CPU_ARCH_V8M_MAIN
|| arch == TAG_CPU_ARCH_V8_1M_MAIN);
@@ -3891,7 +3891,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V9A);
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
return (arch == TAG_CPU_ARCH_V6T2
@@ -4032,14 +4032,14 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V9A);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V6K
|| arch == TAG_CPU_ARCH_V7
- || arch == TAG_CPU_ARCH_V8
+ || arch == TAG_CPU_ARCH_V8A
|| arch == TAG_CPU_ARCH_V8R
- || arch == TAG_CPU_ARCH_V9);
+ || arch == TAG_CPU_ARCH_V9A);
}
static bool
@@ -13767,8 +13767,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
return bfd_mach_arm_6SM;
case TAG_CPU_ARCH_V7E_M:
return bfd_mach_arm_7EM;
- case TAG_CPU_ARCH_V8:
- return bfd_mach_arm_8;
+ case TAG_CPU_ARCH_V8A:
+ return bfd_mach_arm_8A;
case TAG_CPU_ARCH_V8R:
return bfd_mach_arm_8R;
case TAG_CPU_ARCH_V8M_BASE:
@@ -13777,8 +13777,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
return bfd_mach_arm_8M_MAIN;
case TAG_CPU_ARCH_V8_1M_MAIN:
return bfd_mach_arm_8_1M_MAIN;
- case TAG_CPU_ARCH_V9:
- return bfd_mach_arm_9;
+ case TAG_CPU_ARCH_V9A:
+ return bfd_mach_arm_9A;
default:
/* Force entry to be added for any new known Tag_CPU_arch value. */
@@ -14111,28 +14111,28 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
};
static const int v8[] =
{
- T(V8), /* PRE_V4. */
- T(V8), /* V4. */
- T(V8), /* V4T. */
- T(V8), /* V5T. */
- T(V8), /* V5TE. */
- T(V8), /* V5TEJ. */
- T(V8), /* V6. */
- T(V8), /* V6KZ. */
- T(V8), /* V6T2. */
- T(V8), /* V6K. */
- T(V8), /* V7. */
- T(V8), /* V6_M. */
- T(V8), /* V6S_M. */
- T(V8), /* V7E_M. */
- T(V8), /* V8. */
- T(V8), /* V8-R. */
- T(V8), /* V8-M.BASE. */
- T(V8), /* V8-M.MAIN. */
- T(V8), /* V8.1. */
- T(V8), /* V8.2. */
- T(V8), /* V8.3. */
- T(V8), /* V8.1-M.MAIN. */
+ T(V8A), /* PRE_V4. */
+ T(V8A), /* V4. */
+ T(V8A), /* V4T. */
+ T(V8A), /* V5T. */
+ T(V8A), /* V5TE. */
+ T(V8A), /* V5TEJ. */
+ T(V8A), /* V6. */
+ T(V8A), /* V6KZ. */
+ T(V8A), /* V6T2. */
+ T(V8A), /* V6K. */
+ T(V8A), /* V7. */
+ T(V8A), /* V6_M. */
+ T(V8A), /* V6S_M. */
+ T(V8A), /* V7E_M. */
+ T(V8A), /* V8A. */
+ T(V8A), /* V8-R. */
+ T(V8A), /* V8-M.BASE. */
+ T(V8A), /* V8-M.MAIN. */
+ T(V8A), /* V8.1. */
+ T(V8A), /* V8.2. */
+ T(V8A), /* V8.3. */
+ T(V8A), /* V8.1-M.MAIN. */
};
static const int v8r[] =
{
@@ -14150,7 +14150,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8R), /* V6_M. */
T(V8R), /* V6S_M. */
T(V8R), /* V7E_M. */
- T(V8), /* V8. */
+ T(V8A), /* V8A. */
T(V8R), /* V8R. */
};
static const int v8m_baseline[] =
@@ -14169,7 +14169,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8M_BASE), /* V6_M. */
T(V8M_BASE), /* V6S_M. */
-1, /* V7E_M. */
- -1, /* V8. */
+ -1, /* V8A. */
-1, /* V8R. */
T(V8M_BASE) /* V8-M BASELINE. */
};
@@ -14189,7 +14189,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8M_MAIN), /* V6_M. */
T(V8M_MAIN), /* V6S_M. */
T(V8M_MAIN), /* V7E_M. */
- -1, /* V8. */
+ -1, /* V8A. */
-1, /* V8R. */
T(V8M_MAIN), /* V8-M BASELINE. */
T(V8M_MAIN) /* V8-M MAINLINE. */
@@ -14210,7 +14210,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8_1M_MAIN), /* V6_M. */
T(V8_1M_MAIN), /* V6S_M. */
T(V8_1M_MAIN), /* V7E_M. */
- -1, /* V8. */
+ -1, /* V8A. */
-1, /* V8R. */
T(V8_1M_MAIN), /* V8-M BASELINE. */
T(V8_1M_MAIN), /* V8-M MAINLINE. */
@@ -14221,29 +14221,29 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
};
static const int v9[] =
{
- T(V9), /* PRE_V4. */
- T(V9), /* V4. */
- T(V9), /* V4T. */
- T(V9), /* V5T. */
- T(V9), /* V5TE. */
- T(V9), /* V5TEJ. */
- T(V9), /* V6. */
- T(V9), /* V6KZ. */
- T(V9), /* V6T2. */
- T(V9), /* V6K. */
- T(V9), /* V7. */
- T(V9), /* V6_M. */
- T(V9), /* V6S_M. */
- T(V9), /* V7E_M. */
- T(V9), /* V8. */
- T(V9), /* V8-R. */
- T(V9), /* V8-M.BASE. */
- T(V9), /* V8-M.MAIN. */
- T(V9), /* V8.1. */
- T(V9), /* V8.2. */
- T(V9), /* V8.3. */
- T(V9), /* V8.1-M.MAIN. */
- T(V9), /* V9. */
+ T(V9A), /* PRE_V4. */
+ T(V9A), /* V4. */
+ T(V9A), /* V4T. */
+ T(V9A), /* V5T. */
+ T(V9A), /* V5TE. */
+ T(V9A), /* V5TEJ. */
+ T(V9A), /* V6. */
+ T(V9A), /* V6KZ. */
+ T(V9A), /* V6T2. */
+ T(V9A), /* V6K. */
+ T(V9A), /* V7. */
+ T(V9A), /* V6_M. */
+ T(V9A), /* V6S_M. */
+ T(V9A), /* V7E_M. */
+ T(V9A), /* V8A. */
+ T(V9A), /* V8-R. */
+ T(V9A), /* V8-M.BASE. */
+ T(V9A), /* V8-M.MAIN. */
+ T(V9A), /* V8.1. */
+ T(V9A), /* V8.2. */
+ T(V9A), /* V8.3. */
+ T(V9A), /* V8.1-M.MAIN. */
+ T(V9A), /* V9A. */
};
static const int v4t_plus_v6_m[] =
{
@@ -14261,7 +14261,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V6_M), /* V6_M. */
T(V6S_M), /* V6S_M. */
T(V7E_M), /* V7E_M. */
- T(V8), /* V8. */
+ T(V8A), /* V8A. */
-1, /* V8R. */
T(V8M_BASE), /* V8-M BASELINE. */
T(V8M_MAIN), /* V8-M MAINLINE. */
@@ -14269,7 +14269,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
-1, /* Unused (19). */
-1, /* Unused (20). */
T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
- T(V9), /* V9. */
+ T(V9A), /* V9A. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
};
static const int *const comb[] =
@@ -253,16 +253,16 @@ enum
TAG_CPU_ARCH_V6_M,
TAG_CPU_ARCH_V6S_M,
TAG_CPU_ARCH_V7E_M,
- TAG_CPU_ARCH_V8,
+ TAG_CPU_ARCH_V8A,
TAG_CPU_ARCH_V8R,
TAG_CPU_ARCH_V8M_BASE,
TAG_CPU_ARCH_V8M_MAIN,
- TAG_CPU_ARCH_8_1A,
- TAG_CPU_ARCH_8_2A,
- TAG_CPU_ARCH_8_3A,
+ TAG_CPU_ARCH_V8_1A,
+ TAG_CPU_ARCH_V8_2A,
+ TAG_CPU_ARCH_V8_3A,
TAG_CPU_ARCH_V8_1M_MAIN,
- TAG_CPU_ARCH_V9,
- MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V9,
+ TAG_CPU_ARCH_V9A,
+ MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V9A,
// Pseudo-architecture to allow objects to be compatible with the subset of
// armv4t and armv6-m. This value should never be stored in object files.
TAG_CPU_ARCH_V4T_PLUS_V6_M = (MAX_TAG_CPU_ARCH + 1)
@@ -32100,26 +32100,26 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
{TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
{TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
{TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_1A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_2A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_3A},
{TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
{TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
{TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_4A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_5A},
{TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_6A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_7A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_8A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_9A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9_1A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9_2A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9_3A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9_4A},
- {TAG_CPU_ARCH_V9, ARM_ARCH_V9_5A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_6A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_7A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_8A},
+ {TAG_CPU_ARCH_V8A, ARM_ARCH_V8_9A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9_1A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9_2A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9_3A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9_4A},
+ {TAG_CPU_ARCH_V9A, ARM_ARCH_V9_5A},
{-1, ARM_ARCH_NONE}
};
@@ -32207,9 +32207,9 @@ get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
{
/* Force revisiting of decision for each new architecture. */
- gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V9);
+ gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V9A);
*profile = 'A';
- return TAG_CPU_ARCH_V9;
+ return TAG_CPU_ARCH_V9A;
}
ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
@@ -32485,7 +32485,7 @@ aeabi_set_public_attributes (void)
by the base architecture.
For new architectures we will have to check these tests. */
- gas_assert (arch <= TAG_CPU_ARCH_V9);
+ gas_assert (arch <= TAG_CPU_ARCH_V9A);
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
aeabi_set_attribute_int (Tag_DIV_use, 0);
@@ -11065,21 +11065,21 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
};
static const int v8[] =
{
- T(V8), // PRE_V4.
- T(V8), // V4.
- T(V8), // V4T.
- T(V8), // V5T.
- T(V8), // V5TE.
- T(V8), // V5TEJ.
- T(V8), // V6.
- T(V8), // V6KZ.
- T(V8), // V6T2.
- T(V8), // V6K.
- T(V8), // V7.
- T(V8), // V6_M.
- T(V8), // V6S_M.
- T(V8), // V7E_M.
- T(V8) // V8.
+ T(V8A), // PRE_V4.
+ T(V8A), // V4.
+ T(V8A), // V4T.
+ T(V8A), // V5T.
+ T(V8A), // V5TE.
+ T(V8A), // V5TEJ.
+ T(V8A), // V6.
+ T(V8A), // V6KZ.
+ T(V8A), // V6T2.
+ T(V8A), // V6K.
+ T(V8A), // V7.
+ T(V8A), // V6_M.
+ T(V8A), // V6S_M.
+ T(V8A), // V7E_M.
+ T(V8A) // V8.
};
static const int v4t_plus_v6_m[] =
{
@@ -11097,7 +11097,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
T(V6_M), // V6_M.
T(V6S_M), // V6S_M.
T(V7E_M), // V7E_M.
- T(V8), // V8.
+ T(V8A), // V8.
T(V4T_PLUS_V6_M) // V4T plus V6_M.
};
static const int* comb[] =
@@ -108,16 +108,16 @@
#define TAG_CPU_ARCH_V6_M 11
#define TAG_CPU_ARCH_V6S_M 12
#define TAG_CPU_ARCH_V7E_M 13
-#define TAG_CPU_ARCH_V8 14
+#define TAG_CPU_ARCH_V8A 14
#define TAG_CPU_ARCH_V8R 15
#define TAG_CPU_ARCH_V8M_BASE 16
#define TAG_CPU_ARCH_V8M_MAIN 17
-#define TAG_CPU_ARCH_8_1A 18
-#define TAG_CPU_ARCH_8_2A 19
-#define TAG_CPU_ARCH_8_3A 20
+#define TAG_CPU_ARCH_V8_1A 18
+#define TAG_CPU_ARCH_V8_2A 19
+#define TAG_CPU_ARCH_V8_3A 20
#define TAG_CPU_ARCH_V8_1M_MAIN 21
-#define TAG_CPU_ARCH_V9 22
-#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V9
+#define TAG_CPU_ARCH_V9A 22
+#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V9A
/* Pseudo-architecture to allow objects to be compatible with the subset of
armv4t and armv6-m. This value should never be stored in object files. */
#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
@@ -12301,7 +12301,7 @@ select_arm_features (unsigned long mach,
case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
- case bfd_mach_arm_8:
+ case bfd_mach_arm_8A:
{
/* Add bits for extensions that Armv8.6-A recognizes. */
arm_feature_set armv8_6_ext_fset
@@ -12320,7 +12320,7 @@ select_arm_features (unsigned long mach,
ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
force_thumb = 1;
break;
- case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
+ case bfd_mach_arm_9A: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
/* If the machine type is unknown allow all architecture types and all
extensions, with the exception of MVE as that clashes with NEON. */
case bfd_mach_arm_unknown: