diff mbox series

LoongArch: Enforce 4-byte align for machine instructions.

Message ID 20260416090825.1794-1-zhaozhou@loongson.cn
State New
Headers
Series LoongArch: Enforce 4-byte align for machine instructions. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

zhaozhou April 16, 2026, 9:08 a.m. UTC 
  If no alignment is specified in the assembly file, Larch will not
perform forced alignment. When this object file (.o) is linked into an
executable, instructions may not be 4-byte aligned, which will
eventually cause instruction fetch errors.

For example, the above issue can occur when generating a shared object
file (.so) with the -nostdlib option.
---
 gas/config/tc-loongarch.c                  | 5 +++++
 gas/testsuite/gas/loongarch/insn_align_4.d | 7 +++++++
 gas/testsuite/gas/loongarch/insn_align_4.s | 4 ++++
 3 files changed, 16 insertions(+)
 create mode 100644 gas/testsuite/gas/loongarch/insn_align_4.d
 create mode 100644 gas/testsuite/gas/loongarch/insn_align_4.s

Comments

Xi Ruoyao April 16, 2026, 9:23 a.m. UTC | #1 
On Thu, 2026-04-16 at 17:08 +0800, zhaozhou wrote:
> If no alignment is specified in the assembly file, Larch will not

LoongArch instead of Larch.

> perform forced alignment. When this object file (.o) is linked into an
> executable, instructions may not be 4-byte aligned, which will
> eventually cause instruction fetch errors.
> 
> For example, the above issue can occur when generating a shared object
> file (.so) with the -nostdlib option.
> ---
>  gas/config/tc-loongarch.c                  | 5 +++++
>  gas/testsuite/gas/loongarch/insn_align_4.d | 7 +++++++
>  gas/testsuite/gas/loongarch/insn_align_4.s | 4 ++++
>  3 files changed, 16 insertions(+)
>  create mode 100644 gas/testsuite/gas/loongarch/insn_align_4.d
>  create mode 100644 gas/testsuite/gas/loongarch/insn_align_4.s
> 
> diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
> index 1eb35f2c75e..cac803eb385 100644
> --- a/gas/config/tc-loongarch.c
> +++ b/gas/config/tc-loongarch.c
> @@ -1432,6 +1432,11 @@ loongarch_assemble_INSNs (char *str, unsigned int expand_from_macro)
>        if (*str == '\0')
>  	break;
>  
> +      /* Larch64 instructions require 4-byte alignment.  When emitting

LoongArch instead of Larch64 (32-bit LoongArch requires the same
alignment anyway).
diff mbox series

Patch

diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 1eb35f2c75e..cac803eb385 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -1432,6 +1432,11 @@  loongarch_assemble_INSNs (char *str, unsigned int expand_from_macro)
       if (*str == '\0')
 	break;
 
+      /* Larch64 instructions require 4-byte alignment.  When emitting
+	 instructions into any section, record the appropriate section
+	 alignment.  */
+      record_alignment (now_seg, 2);
+
       struct loongarch_cl_insn the_one;
       memset (&the_one, 0, sizeof (the_one));
       the_one.name = str;
diff --git a/gas/testsuite/gas/loongarch/insn_align_4.d b/gas/testsuite/gas/loongarch/insn_align_4.d
new file mode 100644
index 00000000000..31a5d352a76
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/insn_align_4.d
@@ -0,0 +1,7 @@ 
+#as:
+#readelf: -S
+
+#...
+  \[ [0-9]+\] \.text             PROGBITS         [0-9a-f]{16}  [0-9a-f]{8}
+       [0-9a-f]{16}  [0-9a-f]{16}  AX       0     0     4
+#...
diff --git a/gas/testsuite/gas/loongarch/insn_align_4.s b/gas/testsuite/gas/loongarch/insn_align_4.s
new file mode 100644
index 00000000000..7b4922c113f
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/insn_align_4.s
@@ -0,0 +1,4 @@ 
+.type test, @function
+test:
+  jirl	$ra, $ra, 0
+.size test, .-test