From patchwork Tue Mar 31 20:42:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 132546 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [127.0.0.1]) by sourceware.org (Postfix) with ESMTP id 97FD04BA23F3 for ; Tue, 31 Mar 2026 20:44:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 97FD04BA23F3 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=q/CDoAUY X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) by sourceware.org (Postfix) with ESMTPS id E76ED4B7A1D2 for ; Tue, 31 Mar 2026 20:42:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E76ED4B7A1D2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.dev ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E76ED4B7A1D2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774989759; cv=none; b=QHoOQfY8OU+OD0HaSrH+OZ9Io1u04zsQ/yITX2rT5bimoRcmz3JHRNbL6uvXPjywkH7VkgV1baMLlzcRgVSX0rksUfy/EXKMb/hmWl0bfs922w6na50AqEBUYMDFzq940PW0ST64sSXJXUaRrJYdfPPAlH6NBnv8iDKafZqVlbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774989759; c=relaxed/simple; bh=euTb2CBM68u4GKCvIxBD+iYPmlf0JDCwv3fOb/5+eZs=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=DljGYCUAMLG+JHtslkPiVDVYUnkWnP3qTLyKTX9N7+PL3IL84Gz5jyMXKfxyLWEUnBNAamc7D1fMWC3JEuRyfFrhF92V6E1rJ5Nha/sN/wbfWIWmPkaET9tYyZHTY4K6Y0X7DFDRZNjd/rpJ/PFczTH4UDlM9yKFy67IhY2u/XU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E76ED4B7A1D2 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1774989758; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=51ADWBOi/zh8OabowtsmedfM+nPHgXcl7frWBujogiU=; b=q/CDoAUYqvBHV/d4ArbLbkyCXKuLHbwjQhCIirmvMIFBDizWmxULiE8bU+w92TXTvt8Qpe 2TZGgmjjD+3Ij91rGedozd34mS2CgjPE6E5n+6Vjo/HLNJUVmvYbRmYTPMxZRZZRg0mZgC yfRU+20+J3VeORlIaO6vWHdgpq8pjgY= From: Vineet Gupta To: bpf@gcc.gnu.org Cc: binutils@sourceware.org, jose.marchesi@oracle.com, ast@kernel.org, Eduard Zingerman , Yonghong Song , Vineet Gupta Subject: [v2 3/4] PR 34029: bpf: add %dR/%sR register format specifiers Date: Tue, 31 Mar 2026 13:42:11 -0700 Message-ID: <20260331204212.3992270-4-vineet.gupta@linux.dev> In-Reply-To: <20260331204212.3992270-1-vineet.gupta@linux.dev> References: <20260331204212.3992270-1-vineet.gupta@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org These accept either r or w prefix registers during assembly (pseudoc dialect), while disassembling canonically as r registers. This eliminates the need for duplicate opcode table entries for instructions that accept both w and r register forms. Signed-off-by: Vineet Gupta --- gas/config/tc-bpf.c | 16 ++++++++++++---- include/opcode/bpf.h | 4 +++- opcodes/bpf-dis.c | 6 ++++-- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index ecb6c5a70535..8d48b128fb90 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -1525,12 +1525,16 @@ md_assemble (char *str ATTRIBUTE_UNUSED) p += 2; } else if (strncmp (p, "%dr", 3) == 0 - || strncmp (p, "%dw", 3) == 0) + || strncmp (p, "%dw", 3) == 0 + || strncmp (p, "%dR", 3) == 0) { char rw = *(p + 2); uint8_t regno; - char *news = parse_bpf_register (s, rw, ®no); + char *news = parse_bpf_register (s, rw == 'R' ? 'r' : rw, + ®no); + if (rw == 'R' && news == NULL) + news = parse_bpf_register (s, 'w', ®no); if (news == NULL || (insn.has_dst && regno != insn.dst)) { if (news != NULL) @@ -1546,12 +1550,16 @@ md_assemble (char *str ATTRIBUTE_UNUSED) p += 3; } else if (strncmp (p, "%sr", 3) == 0 - || strncmp (p, "%sw", 3) == 0) + || strncmp (p, "%sw", 3) == 0 + || strncmp (p, "%sR", 3) == 0) { char rw = *(p + 2); uint8_t regno; - char *news = parse_bpf_register (s, rw, ®no); + char *news = parse_bpf_register (s, rw == 'R' ? 'r' : rw, + ®no); + if (rw == 'R' && news == NULL) + news = parse_bpf_register (s, 'w', ®no); if (news == NULL || (insn.has_src && regno != insn.src)) { if (news != NULL) diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index e4ccd430f0ce..e17ca2fdd2c1 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -252,8 +252,10 @@ struct bpf_opcode %% - literal %. %dr - destination 64-bit register. %dw - destination 32-bit register. + %dR - destination register, either r or w prefix accepted. %sr - source 64-bit register. %sw - source 32-bit register. + %sR - source register, either r or w prefix accepted. %d32 - 32-bit signed displacement (in 64-bit words minus one.) %d16 - 16-bit signed displacement (in 64-bit words minus one.) %o16 - 16-bit signed offset (in bytes.) @@ -268,7 +270,7 @@ struct bpf_opcode denote something like `[%r3 + 10]', please use a template like `[ %sr %o16]' instead of `[ %sr + %o16 ]'. - If %dr, %dw, %sr or %sw are found multiple times in a template, + If %dr, %dw, %dR, %sr, %sw or %sR are found multiple times in a template, they refer to the same register, i.e. `%rd = le64 %rd' denotes `r2 = le64 r2', but not `r2 = le64 r1'. diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index de8d417dcd38..07aacb621a3b 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -215,13 +215,15 @@ print_insn_bpf (bfd_vma pc, disassemble_info *info) p += 2; } else if (strncmp (p, "%dr", 3) == 0 - || strncmp (p, "%dw", 3) == 0) + || strncmp (p, "%dw", 3) == 0 + || strncmp (p, "%dR", 3) == 0) { print_register (info, p, bpf_extract_dst (word, endian)); p += 3; } else if (strncmp (p, "%sr", 3) == 0 - || strncmp (p, "%sw", 3) == 0) + || strncmp (p, "%sw", 3) == 0 + || strncmp (p, "%sR", 3) == 0) { print_register (info, p, bpf_extract_src (word, endian)); p += 3;