From patchwork Mon Mar 30 22:42:03 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 132477 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [127.0.0.1]) by sourceware.org (Postfix) with ESMTP id 6106E4B92090 for ; Mon, 30 Mar 2026 22:45:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6106E4B92090 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=G/fyAHJl X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out-174.mta1.migadu.com (out-174.mta1.migadu.com [95.215.58.174]) by sourceware.org (Postfix) with ESMTPS id 16CE94B920C5 for ; Mon, 30 Mar 2026 22:42:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 16CE94B920C5 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.dev ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 16CE94B920C5 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=95.215.58.174 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774910545; cv=none; b=pg8yF612PqsLUCvOfjfpEaZTXqMDJtB1AFY80hcS1NJvq5CT/gTKMrYqC01ZOpMv+9lk2XpYs6RQtXzk7qwMtxajBlhoSo8tM3DgtRuTyEGx/UzVovDX/H/GpbcTf8m5C2dk6hqmWaxeLHY1twmXINAc2Rl2qdUMMU64Ql/rpHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1774910545; c=relaxed/simple; bh=20G//a94FEm/KHbElmpGdRljjuoFceQHwrl8r7l0d5U=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=FoxwFZo3XxJaptDZ3MZnYcFnCDbhTYgvQ35Rln3GnxNeNy1wbwb4LC41Dk+vtB7w9TsuMhaJeTUsNFSjmXRQp5HBbzNeouqTjEoamk+laTSCN82mXBIY/goDHYXwoSwcdrIEt8yWIWgjw/OY70sR0Lhy6zR3sWtAmzHgP5zhO2g= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16CE94B920C5 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1774910544; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9953r6EV2TteFgrNHsgrP4P/1npsOmcJj/fGuf7JHgw=; b=G/fyAHJllpxsDDOpsuqZzs8ZB0+4HVQMw/vzWN5qO/ujgZJ6GHRa6p73pBXNoWXk5Hmq3m 9jM3u/xGFnjUJcUySeQRBnAzcoJINIcsVEFzTODFOPXhABqCzqvflnCyO3yzLbLwwDS8sW xoHwbdW6rFcVVPBfkgcPHIVkqBVYogw= From: Vineet Gupta To: bpf@gcc.gnu.org Cc: binutils@sourceware.org, jose.marchesi@oracle.com, ast@kernel.org, Eduard Zingerman , Yonghong Song , Vineet Gupta Subject: [PATCH 3/3] PR 34029: bpf: allow w regs in load insns similar to llvm Date: Mon, 30 Mar 2026 15:42:03 -0700 Message-ID: <20260330224203.3110788-4-vineet.gupta@linux.dev> In-Reply-To: <20260330224203.3110788-1-vineet.gupta@linux.dev> References: <20260330224203.3110788-1-vineet.gupta@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org e.g. | w5 = *(u32 *)(r9 +0) | Error: unexpected register name `w5' in expression Similar theme as prior patch for store insns. Signed-off-by: Vineet Gupta --- gas/testsuite/gas/bpf/mem-be-pseudoc.d | 11 +++++++---- gas/testsuite/gas/bpf/mem-pseudoc.d | 11 +++++++---- gas/testsuite/gas/bpf/mem-pseudoc.s | 3 +++ include/opcode/bpf.h | 1 + opcodes/bpf-opc.c | 6 ++++++ 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d index 8a0980dd3dfa..37178ef85849 100644 --- a/gas/testsuite/gas/bpf/mem-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d @@ -30,7 +30,10 @@ Disassembly of section .text: 98: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) a0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) a8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) - b0: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 - b8: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 - c0: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 - c8: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) + b0: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + b8: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + c0: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + c8: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + d0: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + d8: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + e0: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d index 6863cd923f3a..c60512126561 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d @@ -30,7 +30,10 @@ Disassembly of section .text: 98: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) a0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) a8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) - b0: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 - b8: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 - c0: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 - c8: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) + b0: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + b8: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + c0: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + c8: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + d0: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + d8: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + e0: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s index 08797ae58dcf..2b71b15904d3 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.s +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s @@ -23,6 +23,9 @@ r2 = *(s16*)(r1+0x7eef) r2 = *(s8*)(r1+0x7eef) r2 = *(s64*)(r1+0x7eef) + w2 = *(u32 *)(r1 + 32495) + w2 = *(u16 *)(r1 + 32495) + w2 = *(u8 *)(r1 + 32495) *(u32 *)(r1 + 32495) = w2 *(u16 *)(r1 + 32495) = w2 *(u8 *)(r1 + 32495) = w2 diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index 7befef454425..c0a80fd2ffd1 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -194,6 +194,7 @@ enum bpf_insn_id BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, /* Generic load instructions (to register.) */ BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW, + BPF_INSN_LDXBW, BPF_INSN_LDXHW, BPF_INSN_LDXWW, /* Generic signed load instructions. */ BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW, /* Generic store instructions (from register.) */ diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index c46ff07901c9..e67c7ba1fb51 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -216,6 +216,12 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM}, {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM}, + {BPF_INSN_LDXBW, "ldxb%W%dr , [ %sr %o16 ]", "%dw = * ( u8 * ) ( %sr %o16 )", + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM}, + {BPF_INSN_LDXHW, "ldxh%W%dr , [ %sr %o16 ]", "%dw = * ( u16 * ) ( %sr %o16 )", + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM}, + {BPF_INSN_LDXWW, "ldxw%W%dr , [ %sr %o16 ]", "%dw = * ( u32 * ) ( %sr %o16 )", + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM}, /* Generic signed load instructions (to register.) */ {BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( s8 * ) ( %sr %o16 )",