[3/3] PR 34029: bpf: allow w regs in load insns similar to llvm
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Commit Message
e.g.
| w5 = *(u32 *)(r9 +0)
| Error: unexpected register name `w5' in expression
Similar theme as prior patch for store insns.
Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
---
gas/testsuite/gas/bpf/mem-be-pseudoc.d | 11 +++++++----
gas/testsuite/gas/bpf/mem-pseudoc.d | 11 +++++++----
gas/testsuite/gas/bpf/mem-pseudoc.s | 3 +++
include/opcode/bpf.h | 1 +
opcodes/bpf-opc.c | 6 ++++++
5 files changed, 24 insertions(+), 8 deletions(-)
Comments
Please see the comments in the previous patch, that also apply to this
one.
> e.g.
> | w5 = *(u32 *)(r9 +0)
> | Error: unexpected register name `w5' in expression
>
> Similar theme as prior patch for store insns.
>
> Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
> ---
> gas/testsuite/gas/bpf/mem-be-pseudoc.d | 11 +++++++----
> gas/testsuite/gas/bpf/mem-pseudoc.d | 11 +++++++----
> gas/testsuite/gas/bpf/mem-pseudoc.s | 3 +++
> include/opcode/bpf.h | 1 +
> opcodes/bpf-opc.c | 6 ++++++
> 5 files changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d
> index 8a0980dd3dfa..37178ef85849 100644
> --- a/gas/testsuite/gas/bpf/mem-be-pseudoc.d
> +++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d
> @@ -30,7 +30,10 @@ Disassembly of section .text:
> 98: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
> a0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
> a8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
> - b0: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
> - b8: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
> - c0: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
> - c8: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
> + b0: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
> + b8: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
> + c0: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
> + c8: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
> + d0: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
> + d8: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
> + e0: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
> diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d
> index 6863cd923f3a..c60512126561 100644
> --- a/gas/testsuite/gas/bpf/mem-pseudoc.d
> +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d
> @@ -30,7 +30,10 @@ Disassembly of section .text:
> 98: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
> a0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
> a8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
> - b0: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
> - b8: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
> - c0: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
> - c8: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
> + b0: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
> + b8: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
> + c0: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
> + c8: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
> + d0: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
> + d8: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
> + e0: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
> diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s
> index 08797ae58dcf..2b71b15904d3 100644
> --- a/gas/testsuite/gas/bpf/mem-pseudoc.s
> +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s
> @@ -23,6 +23,9 @@
> r2 = *(s16*)(r1+0x7eef)
> r2 = *(s8*)(r1+0x7eef)
> r2 = *(s64*)(r1+0x7eef)
> + w2 = *(u32 *)(r1 + 32495)
> + w2 = *(u16 *)(r1 + 32495)
> + w2 = *(u8 *)(r1 + 32495)
> *(u32 *)(r1 + 32495) = w2
> *(u16 *)(r1 + 32495) = w2
> *(u8 *)(r1 + 32495) = w2
> diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
> index 7befef454425..c0a80fd2ffd1 100644
> --- a/include/opcode/bpf.h
> +++ b/include/opcode/bpf.h
> @@ -194,6 +194,7 @@ enum bpf_insn_id
> BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW,
> /* Generic load instructions (to register.) */
> BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
> + BPF_INSN_LDXBW, BPF_INSN_LDXHW, BPF_INSN_LDXWW,
> /* Generic signed load instructions. */
> BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW,
> /* Generic store instructions (from register.) */
> diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
> index c46ff07901c9..e67c7ba1fb51 100644
> --- a/opcodes/bpf-opc.c
> +++ b/opcodes/bpf-opc.c
> @@ -216,6 +216,12 @@ const struct bpf_opcode bpf_opcodes[] =
> BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
> {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
> BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
> + {BPF_INSN_LDXBW, "ldxb%W%dr , [ %sr %o16 ]", "%dw = * ( u8 * ) ( %sr %o16 )",
> + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},
> + {BPF_INSN_LDXHW, "ldxh%W%dr , [ %sr %o16 ]", "%dw = * ( u16 * ) ( %sr %o16 )",
> + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},
> + {BPF_INSN_LDXWW, "ldxw%W%dr , [ %sr %o16 ]", "%dw = * ( u32 * ) ( %sr %o16 )",
> + BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
>
> /* Generic signed load instructions (to register.) */
> {BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( s8 * ) ( %sr %o16 )",
@@ -30,7 +30,10 @@ Disassembly of section .text:
98: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
a0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
a8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
- b0: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
- b8: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
- c0: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
- c8: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
+ b0: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
+ b8: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
+ c0: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
+ c8: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
+ d0: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
+ d8: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
+ e0: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
@@ -30,7 +30,10 @@ Disassembly of section .text:
98: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\)
a0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\)
a8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\)
- b0: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
- b8: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
- c0: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
- c8: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
+ b0: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
+ b8: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
+ c0: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
+ c8: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
+ d0: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
+ d8: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
+ e0: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\)
@@ -23,6 +23,9 @@
r2 = *(s16*)(r1+0x7eef)
r2 = *(s8*)(r1+0x7eef)
r2 = *(s64*)(r1+0x7eef)
+ w2 = *(u32 *)(r1 + 32495)
+ w2 = *(u16 *)(r1 + 32495)
+ w2 = *(u8 *)(r1 + 32495)
*(u32 *)(r1 + 32495) = w2
*(u16 *)(r1 + 32495) = w2
*(u8 *)(r1 + 32495) = w2
@@ -194,6 +194,7 @@ enum bpf_insn_id
BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW,
/* Generic load instructions (to register.) */
BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
+ BPF_INSN_LDXBW, BPF_INSN_LDXHW, BPF_INSN_LDXWW,
/* Generic signed load instructions. */
BPF_INSN_LDXSB, BPF_INSN_LDXSH, BPF_INSN_LDXSW, BPF_INSN_LDXSDW,
/* Generic store instructions (from register.) */
@@ -216,6 +216,12 @@ const struct bpf_opcode bpf_opcodes[] =
BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
{BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
+ {BPF_INSN_LDXBW, "ldxb%W%dr , [ %sr %o16 ]", "%dw = * ( u8 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},
+ {BPF_INSN_LDXHW, "ldxh%W%dr , [ %sr %o16 ]", "%dw = * ( u16 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},
+ {BPF_INSN_LDXWW, "ldxw%W%dr , [ %sr %o16 ]", "%dw = * ( u32 * ) ( %sr %o16 )",
+ BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
/* Generic signed load instructions (to register.) */
{BPF_INSN_LDXSB, "ldxsb%W%dr , [ %sr %o16 ]", "%dr = * ( s8 * ) ( %sr %o16 )",