diff --git a/gas/testsuite/gas/aarch64/sys-rt-alias.d b/gas/testsuite/gas/aarch64/sys-rt-alias.d
new file mode 100644
index 00000000000..96c2f6844a8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sys-rt-alias.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50c879f 	tlbi	alle1
+.*:	d50c8780 	sys	#4, C8, C7, #4, x0
+.*:	d50ca79f 	plbi	alle1
+.*:	d50ca780 	sys	#4, C10, C7, #4, x0
+.*:	d50c709f 	mlbi	alle1
+.*:	d50c7080 	sys	#4, C7, C0, #4, x0
+.*:	d508751f 	ic	iallu
+.*:	d5087500 	sys	#0, C7, C5, #0, x0
+.*:	d50887bf 	tlbi	vale1, xzr
+.*:	d50887a0 	tlbi	vale1, x0
diff --git a/gas/testsuite/gas/aarch64/sys-rt-alias.s b/gas/testsuite/gas/aarch64/sys-rt-alias.s
new file mode 100644
index 00000000000..2aa107fa6d9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sys-rt-alias.s
@@ -0,0 +1,13 @@
+// sys-rt-alias.s Test file for AArch64 instructions where Rt !=31 is undefined behaviour.
+
+	.text
+	sys #4, c8, c7, #4      // TLBI ALLE1 with Rt=31
+	sys #4, c8, c7, #4, x0  // TLBI ALLE1 with Rt!=31
+	sys #4, c10, c7, #4     // PLBI ALLE1 with Rt=31
+	sys #4, c10, c7, #4, x0 // PLBI ALLE1 with Rt!=31
+	sys #4, c7, c0, #4      // MLBI ALLE1 with Rt=31
+	sys #4, c7, c0, #4, x0  // MLBI ALLE1 with Rt!=31
+	sys #0, c7, c5, #0      // IC IALLU with Rt=31
+	sys #0, c7, c5, #0, x0  // IC IALLU with Rt!=31
+	sys #0, c8, c7, #5, xzr // TLBI VALE1 with Rt=31 (valid Xt form)
+	sys #0, c8, c7, #5, x0  // TLBI VALE1 with Rt!=31 (valid Xt form)
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index f09307847e6..8544ce4b6d4 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -331,12 +331,9 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
      help the disassembler determine whether this operand is optional or
      not.  */

-  if (aarch64_sys_ins_reg_tlbid_xt (inst->operands[0].sysins_op)
-      && info->reg.regno != 31)
-    info->present = true;
-  else
-    info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
-
+  info->present
+    = (info->reg.regno != 31
+       || aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op));
   return true;
 }