From patchwork Fri Mar 13 12:30:59 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 131671 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [127.0.0.1]) by sourceware.org (Postfix) with ESMTP id B96944BC8989 for ; Fri, 13 Mar 2026 12:32:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B96944BC8989 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTPS id 816804BBCDFA for ; Fri, 13 Mar 2026 12:31:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 816804BBCDFA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 816804BBCDFA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.25 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1773405089; cv=none; b=gmymNQTa/QvsMfnhqR21/xUevnyp3CDW1Jj1i4XYGUZlHPT3zhb6KXuLuDBSL2aKal34M2kFwP/Uh2ewDhJtqXcFxgzCLc1gS/M9EYp9FqlHDFHSA68eyePYs60DosKj9PfyeJELIFEYL2pc73oxeTPQ3BJHCftmfWQMSn6iLEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1773405089; c=relaxed/simple; bh=in8wQNBKpZknBT7H2K5zWtYeHqTTEZqgT2uRvbRthG8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=fMxbhO2EpnIWOxAnn0HqFxwjCsEZWuqeYYeduv7P47gKi6Zg7HYOc90i82HzalKlETexzfrDqg2prhXPJeQemPpxkm4hmw74RMxHtS+Sgy2D2kAD6TWsIIc5KpE6HS4DLpEIJd6cfx75krlzfqRrYvGaUXh7KHb8wh9cy+swlcQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 816804BBCDFA Received: from localhost.localdomain (unknown [153.3.90.52]) by APP-05 (Coremail) with SMTP id zQCowAC3RgqaA7Rpq3JZCg--.11452S2; Fri, 13 Mar 2026 20:31:23 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, jbeulich@suse.com, kito.cheng@gmail.com, Jiawei Subject: [RFC] RISC-V: Support Zibi extension. Date: Fri, 13 Mar 2026 20:30:59 +0800 Message-ID: <20260313123059.795398-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CM-TRANSID: zQCowAC3RgqaA7Rpq3JZCg--.11452S2 X-Coremail-Antispam: 1UD129KBjvJXoW3ArWfZw1xKryxGr4DKr13twb_yoWxKw18pF 4kuF1Y93s5tFZ7Krna9Fyj9r47A3sagF1a93ySgw13A3y7XrW8J3yktw15AF4kXF4Ygr1a 9a1rGr45u3yUCa7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkm14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s 0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v26r12 6r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI 0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y 0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxV WUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1l IxAIcVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUehL0UUUUU X-Originating-IP: [153.3.90.52] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBwsFAGmzugfvsQAAsw X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch supports Zibi extension(Branch with immediate) instructions. https://github.com/riscv/zibi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New ext. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Support Zibi extension. * testsuite/gas/riscv/march-help.l: New ext. * testsuite/gas/riscv/zibi.d: New test. * testsuite/gas/riscv/zibi.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_BEQI): New match opcode. (MASK_BEQI): New mask opcode. (MATCH_BNEI): New match opcode. (MASK_BNEI): New mask opcode. (DECLARE_INSN): New insn declare. * opcode/riscv.h (enum riscv_insn_class): New ext. opcodes/ChangeLog: * riscv-opc.c: New instructions def. --- bfd/elfxx-riscv.c | 5 +++++ gas/NEWS | 3 +++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zibi.d | 16 ++++++++++++++++ gas/testsuite/gas/riscv/zibi.s | 7 +++++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 2 ++ 8 files changed, 43 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zibi.d create mode 100644 gas/testsuite/gas/riscv/zibi.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ee962b4f6f1..59e9af2400b 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1451,6 +1451,7 @@ static const struct riscv_supported_ext riscv_supported_std_ext[] = static const struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zibi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2804,6 +2805,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, { case INSN_CLASS_I: return riscv_subset_supports (rps, "i"); + case INSN_CLASS_ZIBI: + return riscv_subset_supports (rps, "zibi"); case INSN_CLASS_ZICBOM: return riscv_subset_supports (rps, "zicbom"); case INSN_CLASS_ZICBOP: @@ -3080,6 +3083,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, { case INSN_CLASS_I: return "i"; + case INSN_CLASS_ZIBI: + return "zibi"; case INSN_CLASS_ZICBOM: return "zicbom"; case INSN_CLASS_ZICBOP: diff --git a/gas/NEWS b/gas/NEWS index e384d1135c0..3a36d99f814 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,8 @@ -*- text -*- +* Add support for RISC-V standard extensions: + zibi v1.0. + Changes in 2.46: * Add support for AMD Zen6 processor. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 0ce2f896735..692ab702715 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -10,6 +10,7 @@ All available -march extensions for RISC-V: b 1.0 v 1.0 h 1.0 + zibi 1.0 zic64b 1.0 ziccamoa 1.0 ziccif 1.0 diff --git a/gas/testsuite/gas/riscv/zibi.d b/gas/testsuite/gas/riscv/zibi.d new file mode 100644 index 00000000000..da84479d47d --- /dev/null +++ b/gas/testsuite/gas/riscv/zibi.d @@ -0,0 +1,16 @@ +#as: -march=rv64ic_zibi +#source: zibi.s +#objdump: -drw + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+ : +[ ]+[0-9a-f]+:[ ]+00042063[ ]+beqi[ ]+s0,0x0,0 [ ]+0: R_RISCV_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fe442ee3[ ]+beqi[ ]+s0,0x24,0 [ ]+4: R_RISCV_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fe043ce3[ ]+bnei[ ]+s0,0x20,0 [ ]+8: R_RISCV_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fe443ae3[ ]+bnei[ ]+s0,0x24,0 [ ]+c: R_RISCV_BRANCH .* +[ ]+[0-9a-f]+:[ ]+8082[ ]+ret +#... diff --git a/gas/testsuite/gas/riscv/zibi.s b/gas/testsuite/gas/riscv/zibi.s new file mode 100644 index 00000000000..fa7a6d81a5b --- /dev/null +++ b/gas/testsuite/gas/riscv/zibi.s @@ -0,0 +1,7 @@ + .text +target: + beqi x8, 0, target + beqi x8, 4, target + bnei x8, 0, target + bnei x8, 4, target + ret diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6f2775c6152..f520f4bed64 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2400,6 +2400,11 @@ #define MASK_C_SSPUSH 0xffff #define MATCH_C_SSPOPCHK 0x6281 #define MASK_C_SSPOPCHK 0xffff +/* Zibi instructions. */ +#define MATCH_BEQI 0x2063 +#define MASK_BEQI 0x707f +#define MATCH_BNEI 0x3063 +#define MASK_BNEI 0x707f /* Zicfilp instructions. */ #define MATCH_LPAD 0x17 #define MASK_LPAD 0xfff @@ -4717,6 +4722,9 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) +/* Zibi instructions. */ +DECLARE_INSN(beqi, MATCH_BEQI, MASK_BEQI) +DECLARE_INSN(bnei, MATCH_BNEI, MASK_BNEI) /* Zicbop instructions. */ DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index de105f5df8b..a6b879c7ba6 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -500,6 +500,7 @@ enum riscv_insn_class INSN_CLASS_Q, INSN_CLASS_ZCF, INSN_CLASS_ZCD, + INSN_CLASS_ZIBI, INSN_CLASS_ZICOND, INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 54887c97880..c744819b848 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -527,6 +527,7 @@ const struct riscv_opcode riscv_opcodes[] = {"beqz", 0, INSN_CLASS_I, "s,p", MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beq", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"beq", 0, INSN_CLASS_I, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH }, +{"beqi", 0, INSN_CLASS_ZIBI, "s,>,p", MATCH_BEQI, MASK_BEQI, match_opcode, INSN_CONDBRANCH }, {"blez", 0, INSN_CLASS_I, "t,p", MATCH_BGE, MASK_BGE|MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bgez", 0, INSN_CLASS_I, "s,p", MATCH_BGE, MASK_BGE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bge", 0, INSN_CLASS_I, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH }, @@ -543,6 +544,7 @@ const struct riscv_opcode riscv_opcodes[] = {"bnez", 0, INSN_CLASS_I, "s,p", MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bne", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH }, {"bne", 0, INSN_CLASS_I, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH }, +{"bnei", 0, INSN_CLASS_ZIBI, "s,>,p", MATCH_BNEI, MASK_BNEI, match_opcode, INSN_CONDBRANCH }, {"addi", 0, INSN_CLASS_ZCA, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"addi", 0, INSN_CLASS_ZCA, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, {"addi", 0, INSN_CLASS_ZCA, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },