diff mbox series

[v3,12/12] LoongArch32: Fix and add testcases

Message ID 20251205064759.2102819-13-mengqinggang@loongson.cn
State New
Headers
Series Add support for LoongArch32 in Binutils |

Commit Message

mengqinggang Dec. 5, 2025, 6:47 a.m. UTC 
  From: Lulu Cai <cailulu@loongson.cn>

Fixed several test failures caused by the LoongArch32 assembler adding
labels during assembly. Additionally, skipped tests specific to LoongArch64.

Add test for new relocations.
Add test for tls type transition, got relaxation and call30 relaxation.
---
 gas/testsuite/gas/loongarch/macro_op_32.d     | 72 ++++++++++---------
 gas/testsuite/gas/loongarch/relocs_32.d       | 49 +++++++++++++
 gas/testsuite/gas/loongarch/relocs_32.s       | 37 ++++++++++
 ld/testsuite/ld-loongarch-elf/desc-ie.d       |  9 ++-
 ld/testsuite/ld-loongarch-elf/disas-jirl-32.d | 14 ++--
 ld/testsuite/ld-loongarch-elf/la32.d          | 15 ++++
 ld/testsuite/ld-loongarch-elf/la32.s          | 14 ++++
 .../ld-loongarch-elf/ld-loongarch-elf.exp     |  4 ++
 ld/testsuite/ld-loongarch-elf/macro_op_32.d   | 72 ++++++++++---------
 ld/testsuite/ld-loongarch-elf/pic.exp         |  4 +-
 10 files changed, 211 insertions(+), 79 deletions(-)
 create mode 100644 ld/testsuite/ld-loongarch-elf/la32.d
 create mode 100644 ld/testsuite/ld-loongarch-elf/la32.s
diff mbox series

Patch

diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index 8fd69922c14..2d6384dfeef 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -12,40 +12,46 @@  Disassembly of section .text:
    4:	02bffc04 	li.w        	\$a0, -1
    8:	00150004 	move        	\$a0, \$zero
    c:	02bffc04 	li.w        	\$a0, -1
-  10:	1a000004 	pcalau12i   	\$a0, 0
-			10: R_LARCH_GOT_PC_HI20	.L1
+
+0+10 <.Lpcadd_hi0>:
+  10:	1c000004 	pcaddu12i   	\$a0, 0
+			10: R_LARCH_GOT_PCADD_HI20	.L1
 			10: R_LARCH_RELAX	\*ABS\*
   14:	28800084 	ld.w        	\$a0, \$a0, 0
-			14: R_LARCH_GOT_PC_LO12	.L1
+			14: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi0
 			14: R_LARCH_RELAX	\*ABS\*
-  18:	1a000004 	pcalau12i   	\$a0, 0
-			18: R_LARCH_GOT_PC_HI20	.L1
+
+0+18 <.Lpcadd_hi1>:
+  18:	1c000004 	pcaddu12i   	\$a0, 0
+			18: R_LARCH_GOT_PCADD_HI20	.L1
 			18: R_LARCH_RELAX	\*ABS\*
   1c:	28800084 	ld.w        	\$a0, \$a0, 0
-			1c: R_LARCH_GOT_PC_LO12	.L1
+			1c: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi1
 			1c: R_LARCH_RELAX	\*ABS\*
-  20:	1a000004 	pcalau12i   	\$a0, 0
-			20: R_LARCH_PCALA_HI20	.L1
-			20: R_LARCH_RELAX	\*ABS\*
+
+0+20 <.Lpcadd_hi2>:
+  20:	1c000004 	pcaddu12i   	\$a0, 0
+			20: R_LARCH_PCADD_HI20	.L1
   24:	02800084 	addi.w      	\$a0, \$a0, 0
-			24: R_LARCH_PCALA_LO12	.L1
-			24: R_LARCH_RELAX	\*ABS\*
+			24: R_LARCH_PCADD_LO12	.Lpcadd_hi2
   28:	14000004 	lu12i.w     	\$a0, 0
 			28: R_LARCH_MARK_LA	\*ABS\*
 			28: R_LARCH_ABS_HI20	.L1
   2c:	03800084 	ori         	\$a0, \$a0, 0x0
 			2c: R_LARCH_ABS_LO12	.L1
-  30:	1a000004 	pcalau12i   	\$a0, 0
-			30: R_LARCH_PCALA_HI20	.L1
-			30: R_LARCH_RELAX	\*ABS\*
+
+0+30 <.Lpcadd_hi3>:
+  30:	1c000004 	pcaddu12i   	\$a0, 0
+			30: R_LARCH_PCADD_HI20	.L1
   34:	02800084 	addi.w      	\$a0, \$a0, 0
-			34: R_LARCH_PCALA_LO12	.L1
-			34: R_LARCH_RELAX	\*ABS\*
-  38:	1a000004 	pcalau12i   	\$a0, 0
-			38: R_LARCH_GOT_PC_HI20	.L1
+			34: R_LARCH_PCADD_LO12	.Lpcadd_hi3
+
+0+38 <.Lpcadd_hi4>:
+  38:	1c000004 	pcaddu12i   	\$a0, 0
+			38: R_LARCH_GOT_PCADD_HI20	.L1
 			38: R_LARCH_RELAX	\*ABS\*
   3c:	28800084 	ld.w        	\$a0, \$a0, 0
-			3c: R_LARCH_GOT_PC_LO12	.L1
+			3c: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi4
 			3c: R_LARCH_RELAX	\*ABS\*
   40:	14000004 	lu12i.w     	\$a0, 0
 			40: R_LARCH_TLS_LE_HI20	TLS1
@@ -53,21 +59,23 @@  Disassembly of section .text:
   44:	03800084 	ori         	\$a0, \$a0, 0x0
 			44: R_LARCH_TLS_LE_LO12	TLS1
 			44: R_LARCH_RELAX	\*ABS\*
-  48:	1a000004 	pcalau12i   	\$a0, 0
-			48: R_LARCH_TLS_IE_PC_HI20	TLS1
+
+0+48 <.Lpcadd_hi5>:
+  48:	1c000004 	pcaddu12i   	\$a0, 0
+			48: R_LARCH_TLS_IE_PCADD_HI20	TLS1
 			48: R_LARCH_RELAX	\*ABS\*
   4c:	28800084 	ld.w        	\$a0, \$a0, 0
-			4c: R_LARCH_TLS_IE_PC_LO12	TLS1
+			4c: R_LARCH_TLS_IE_PCADD_LO12	.Lpcadd_hi5
 			4c: R_LARCH_RELAX	\*ABS\*
-  50:	1a000004 	pcalau12i   	\$a0, 0
-			50: R_LARCH_TLS_LD_PC_HI20	TLS1
-			50: R_LARCH_RELAX	\*ABS\*
+
+0+50 <.Lpcadd_hi6>:
+  50:	1c000004 	pcaddu12i   	\$a0, 0
+			50: R_LARCH_TLS_LD_PCADD_HI20	TLS1
   54:	02800084 	addi.w      	\$a0, \$a0, 0
-			54: R_LARCH_GOT_PC_LO12	TLS1
-			54: R_LARCH_RELAX	\*ABS\*
-  58:	1a000004 	pcalau12i   	\$a0, 0
-			58: R_LARCH_TLS_GD_PC_HI20	TLS1
-			58: R_LARCH_RELAX	\*ABS\*
+			54: R_LARCH_TLS_LD_PCADD_LO12	.Lpcadd_hi6
+
+0+58 <.Lpcadd_hi7>:
+  58:	1c000004 	pcaddu12i   	\$a0, 0
+			58: R_LARCH_TLS_GD_PCADD_HI20	TLS1
   5c:	02800084 	addi.w      	\$a0, \$a0, 0
-			5c: R_LARCH_GOT_PC_LO12	TLS1
-			5c: R_LARCH_RELAX	\*ABS\*
+			5c: R_LARCH_TLS_GD_PCADD_LO12	.Lpcadd_hi7
diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d
index 96ef2800a51..c88aef5c4d8 100644
--- a/gas/testsuite/gas/loongarch/relocs_32.d
+++ b/gas/testsuite/gas/loongarch/relocs_32.d
@@ -75,3 +75,52 @@  Disassembly of section .text:
 			78: R_LARCH_TLS_DESC_LD	TLSL1
   7c:	4c000021 	jirl        	\$ra, \$ra, 0
 			7c: R_LARCH_TLS_DESC_CALL	TLSL1
+0+80 <NEW>:
+  80:	1c000001 	pcaddu12i   	\$ra, 0
+			80: R_LARCH_CALL30	\.L1
+			80: R_LARCH_RELAX	\*ABS\*
+  84:	4c000021 	jirl        	\$ra, \$ra, 0
+  88:	1c000001 	pcaddu12i   	\$ra, 0
+			88: R_LARCH_CALL30	\.L1
+			88: R_LARCH_RELAX	\*ABS\*
+  8c:	4c000020 	ret
+
+0+90 <\.Lpcadd_hi0>:
+  90:	1c000004 	pcaddu12i   	\$a0, 0
+			90: R_LARCH_PCADD_HI20	s
+  94:	02800084 	addi.w      	\$a0, \$a0, 0
+			94: R_LARCH_PCADD_LO12	\.Lpcadd_hi0
+
+0+98 <\.Lpcadd_hi1>:
+  98:	1c000004 	pcaddu12i   	\$a0, 0
+			98: R_LARCH_GOT_PCADD_HI20	s
+  9c:	28800084 	ld.w        	\$a0, \$a0, 0
+			9c: R_LARCH_GOT_PCADD_LO12	\.Lpcadd_hi1
+
+0+a0 <\.Lpcadd_hi2>:
+  a0:	1c000004 	pcaddu12i   	\$a0, 0
+			a0: R_LARCH_TLS_IE_PCADD_HI20	TLSL1
+  a4:	28800084 	ld.w        	\$a0, \$a0, 0
+			a4: R_LARCH_TLS_IE_PCADD_LO12	\.Lpcadd_hi2
+
+0+a8 <\.Lpcadd_hi3>:
+  a8:	1c000004 	pcaddu12i   	\$a0, 0
+			a8: R_LARCH_TLS_LD_PCADD_HI20	TLSL1
+  ac:	02800084 	addi.w      	\$a0, \$a0, 0
+			ac: R_LARCH_TLS_LD_PCADD_LO12	\.Lpcadd_hi3
+
+0+b0 <\.Lpcadd_hi4>:
+  b0:	1c000004 	pcaddu12i   	\$a0, 0
+			b0: R_LARCH_TLS_GD_PCADD_HI20	TLSL1
+  b4:	02800084 	addi.w      	\$a0, \$a0, 0
+			b4: R_LARCH_TLS_GD_PCADD_LO12	\.Lpcadd_hi4
+
+0+b8 <\.Lpcadd_hi5>:
+  b8:	1c000004 	pcaddu12i   	\$a0, 0
+			b8: R_LARCH_TLS_DESC_PCADD_HI20	TLS1
+  bc:	02800084 	addi.w      	\$a0, \$a0, 0
+			bc: R_LARCH_TLS_DESC_PCADD_LO12	\.Lpcadd_hi5
+  c0:	28800081 	ld.w        	\$ra, \$a0, 0
+			c0: R_LARCH_TLS_DESC_LD	TLS1
+  c4:	4c000021 	jirl        	\$ra, \$ra, 0
+			c4: R_LARCH_TLS_DESC_CALL	TLS1
diff --git a/gas/testsuite/gas/loongarch/relocs_32.s b/gas/testsuite/gas/loongarch/relocs_32.s
index c5139a7582c..8a6074d018a 100644
--- a/gas/testsuite/gas/loongarch/relocs_32.s
+++ b/gas/testsuite/gas/loongarch/relocs_32.s
@@ -59,3 +59,40 @@  lu12i.w	  $r4,%desc_hi20(TLSL1)
 ori	  $r4,$r4,%desc_lo12(TLSL1)
 ld.w	  $r1,$r4,%desc_ld(TLSL1)
 jirl	  $r1,$r1,%desc_call(TLSL1)
+
+NEW:
+/* LA32S/R medium call.  */
+call30	  .L1
+tail30	  $r1, .L1
+
+/* LA32R PCREL.  */
+.Lpcadd_hi0:
+pcaddu12i $r4, %pcadd_hi20(s)
+addi.w	  $r4, $r4, %pcadd_lo12(.Lpcadd_hi0)
+
+/* LA32R GOT.  */
+.Lpcadd_hi1:
+pcaddu12i $r4, %got_pcadd_hi20(s)
+ld.w	  $r4, $r4, %got_pcadd_lo12(.Lpcadd_hi1)
+
+/* LA32R TLS IE.  */
+.Lpcadd_hi2:
+pcaddu12i $r4, %ie_pcadd_hi20(TLSL1)
+ld.w	  $r4, $r4, %ie_pcadd_lo12(.Lpcadd_hi2)
+
+/* Part of LA32R TLS LD relocs.  */
+.Lpcadd_hi3:
+pcaddu12i $r4, %ld_pcadd_hi20(TLSL1)
+addi.w	  $r4, $r4, %ld_pcadd_lo12(.Lpcadd_hi3)
+
+/* Part of LA32R TLS GD relocs.  */
+.Lpcadd_hi4:
+pcaddu12i $r4, %gd_pcadd_hi20(TLSL1)
+addi.w	  $r4, $r4, %gd_pcadd_lo12(.Lpcadd_hi4)
+
+/* Part of LA32R TLS DESC relocs.  */
+.Lpcadd_hi5:
+pcaddu12i $r4, %desc_pcadd_hi20(TLS1)
+addi.w	  $r4, $r4, %desc_pcadd_lo12(.Lpcadd_hi5)
+ld.w	  $r1, $r4, %desc_ld(TLS1)
+jirl	  $r1, $r1, %desc_call(TLS1)
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d
index 0759404b89a..007406a04f0 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d
@@ -1,14 +1,13 @@ 
 #as:
 #ld: -shared -z norelro --hash-style=both
 #objdump: -dr
-#skip: loongarch32-*-*
 
 .*:     file format .*
 
 Disassembly of section .text:
 
 [0-9a-f]+ <fn1>:
- +[0-9a-f]+:	[0-9a-f]+ 	pcalau12i   	\$a0, .*
- +[0-9a-f]+:	[0-9a-f]+ 	ld.d        	\$a0, \$a0, .*
- +[0-9a-f]+:	[0-9a-f]+ 	pcalau12i   	\$a0, .*
- +[0-9a-f]+:	[0-9a-f]+ 	ld.d        	\$a0, \$a0, .*
+.*[pcalau12i|pcaddu12i].*
+.*ld.[d|w].*
+.*[pcalau12i|pcaddu12i].*
+.*ld.[d|w].*
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
index cab7a5d4c99..a78bf24e7d3 100644
--- a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
@@ -7,11 +7,9 @@ 
 
 Disassembly of section .text:
 
-00000000.* <_start>:
-[ 	]+0:[ 	]+1a000014[ 	]+pcalau12i[ 	]+\$t8,[ 	]+0
-[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+_start
-[ 	]+0:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
-[ 	]+4:[ 	]+02800294[ 	]+addi.w[ 	]+\$t8,[ 	]+\$t8,[ 	]+0
-[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+_start
-[ 	]+4:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
-[ 	]+8:[ 	]+4c000281[ 	]+jirl[ 	]+\$ra,[ 	]+\$t8,[ 	]+0
+0+ <_start>:
+   0:	1c000014 	pcaddu12i   	\$t8, 0
+			0: R_LARCH_PCADD_HI20	_start
+   4:	02800294 	addi.w      	\$t8, \$t8, 0
+			4: R_LARCH_PCADD_LO12	.Lpcadd_hi0
+   8:	4c000281 	jirl        	\$ra, \$t8, 0
diff --git a/ld/testsuite/ld-loongarch-elf/la32.d b/ld/testsuite/ld-loongarch-elf/la32.d
new file mode 100644
index 00000000000..9f66b7bba8f
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/la32.d
@@ -0,0 +1,15 @@ 
+#as -mabi=ilp32d:
+#ld: -z norelro --hash-style=both -e0
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+.*
+.*bl.*
+.*pcaddu12i.*
+.*addi.w.*
+.*li.w.*
+.*li.w.*
diff --git a/ld/testsuite/ld-loongarch-elf/la32.s b/ld/testsuite/ld-loongarch-elf/la32.s
new file mode 100644
index 00000000000..312f3192862
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/la32.s
@@ -0,0 +1,14 @@ 
+	.global var
+	.section .tdata,"awT",@progbits
+var:
+	.word 1
+
+	.text
+  	.global .L1
+  	.hidden .L1
+.L1:
+  call30 .L1 # relax to bl
+  la.got $t0, .L1 # relax to pcaddu12i + addi.w
+  la.tls.ie $t0, var # relax to tls le
+  la.tls.desc $t0, var # relax to tls le
+
diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
index 5bc48b28ca8..7b0b066190c 100644
--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
@@ -58,6 +58,10 @@  if [istarget "loongarch32-*-*"] {
     run_dump_test "macro_op_32"
     run_dump_test "syscall"
     run_dump_test "disas-jirl-32"
+    run_dump_test "la32"
+    if [check_shared_lib_support] {
+      run_dump_test "desc-ie"
+    }
 }
 
 if [istarget "loongarch64-*-*"] {
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index 8fd69922c14..2d6384dfeef 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -12,40 +12,46 @@  Disassembly of section .text:
    4:	02bffc04 	li.w        	\$a0, -1
    8:	00150004 	move        	\$a0, \$zero
    c:	02bffc04 	li.w        	\$a0, -1
-  10:	1a000004 	pcalau12i   	\$a0, 0
-			10: R_LARCH_GOT_PC_HI20	.L1
+
+0+10 <.Lpcadd_hi0>:
+  10:	1c000004 	pcaddu12i   	\$a0, 0
+			10: R_LARCH_GOT_PCADD_HI20	.L1
 			10: R_LARCH_RELAX	\*ABS\*
   14:	28800084 	ld.w        	\$a0, \$a0, 0
-			14: R_LARCH_GOT_PC_LO12	.L1
+			14: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi0
 			14: R_LARCH_RELAX	\*ABS\*
-  18:	1a000004 	pcalau12i   	\$a0, 0
-			18: R_LARCH_GOT_PC_HI20	.L1
+
+0+18 <.Lpcadd_hi1>:
+  18:	1c000004 	pcaddu12i   	\$a0, 0
+			18: R_LARCH_GOT_PCADD_HI20	.L1
 			18: R_LARCH_RELAX	\*ABS\*
   1c:	28800084 	ld.w        	\$a0, \$a0, 0
-			1c: R_LARCH_GOT_PC_LO12	.L1
+			1c: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi1
 			1c: R_LARCH_RELAX	\*ABS\*
-  20:	1a000004 	pcalau12i   	\$a0, 0
-			20: R_LARCH_PCALA_HI20	.L1
-			20: R_LARCH_RELAX	\*ABS\*
+
+0+20 <.Lpcadd_hi2>:
+  20:	1c000004 	pcaddu12i   	\$a0, 0
+			20: R_LARCH_PCADD_HI20	.L1
   24:	02800084 	addi.w      	\$a0, \$a0, 0
-			24: R_LARCH_PCALA_LO12	.L1
-			24: R_LARCH_RELAX	\*ABS\*
+			24: R_LARCH_PCADD_LO12	.Lpcadd_hi2
   28:	14000004 	lu12i.w     	\$a0, 0
 			28: R_LARCH_MARK_LA	\*ABS\*
 			28: R_LARCH_ABS_HI20	.L1
   2c:	03800084 	ori         	\$a0, \$a0, 0x0
 			2c: R_LARCH_ABS_LO12	.L1
-  30:	1a000004 	pcalau12i   	\$a0, 0
-			30: R_LARCH_PCALA_HI20	.L1
-			30: R_LARCH_RELAX	\*ABS\*
+
+0+30 <.Lpcadd_hi3>:
+  30:	1c000004 	pcaddu12i   	\$a0, 0
+			30: R_LARCH_PCADD_HI20	.L1
   34:	02800084 	addi.w      	\$a0, \$a0, 0
-			34: R_LARCH_PCALA_LO12	.L1
-			34: R_LARCH_RELAX	\*ABS\*
-  38:	1a000004 	pcalau12i   	\$a0, 0
-			38: R_LARCH_GOT_PC_HI20	.L1
+			34: R_LARCH_PCADD_LO12	.Lpcadd_hi3
+
+0+38 <.Lpcadd_hi4>:
+  38:	1c000004 	pcaddu12i   	\$a0, 0
+			38: R_LARCH_GOT_PCADD_HI20	.L1
 			38: R_LARCH_RELAX	\*ABS\*
   3c:	28800084 	ld.w        	\$a0, \$a0, 0
-			3c: R_LARCH_GOT_PC_LO12	.L1
+			3c: R_LARCH_GOT_PCADD_LO12	.Lpcadd_hi4
 			3c: R_LARCH_RELAX	\*ABS\*
   40:	14000004 	lu12i.w     	\$a0, 0
 			40: R_LARCH_TLS_LE_HI20	TLS1
@@ -53,21 +59,23 @@  Disassembly of section .text:
   44:	03800084 	ori         	\$a0, \$a0, 0x0
 			44: R_LARCH_TLS_LE_LO12	TLS1
 			44: R_LARCH_RELAX	\*ABS\*
-  48:	1a000004 	pcalau12i   	\$a0, 0
-			48: R_LARCH_TLS_IE_PC_HI20	TLS1
+
+0+48 <.Lpcadd_hi5>:
+  48:	1c000004 	pcaddu12i   	\$a0, 0
+			48: R_LARCH_TLS_IE_PCADD_HI20	TLS1
 			48: R_LARCH_RELAX	\*ABS\*
   4c:	28800084 	ld.w        	\$a0, \$a0, 0
-			4c: R_LARCH_TLS_IE_PC_LO12	TLS1
+			4c: R_LARCH_TLS_IE_PCADD_LO12	.Lpcadd_hi5
 			4c: R_LARCH_RELAX	\*ABS\*
-  50:	1a000004 	pcalau12i   	\$a0, 0
-			50: R_LARCH_TLS_LD_PC_HI20	TLS1
-			50: R_LARCH_RELAX	\*ABS\*
+
+0+50 <.Lpcadd_hi6>:
+  50:	1c000004 	pcaddu12i   	\$a0, 0
+			50: R_LARCH_TLS_LD_PCADD_HI20	TLS1
   54:	02800084 	addi.w      	\$a0, \$a0, 0
-			54: R_LARCH_GOT_PC_LO12	TLS1
-			54: R_LARCH_RELAX	\*ABS\*
-  58:	1a000004 	pcalau12i   	\$a0, 0
-			58: R_LARCH_TLS_GD_PC_HI20	TLS1
-			58: R_LARCH_RELAX	\*ABS\*
+			54: R_LARCH_TLS_LD_PCADD_LO12	.Lpcadd_hi6
+
+0+58 <.Lpcadd_hi7>:
+  58:	1c000004 	pcaddu12i   	\$a0, 0
+			58: R_LARCH_TLS_GD_PCADD_HI20	TLS1
   5c:	02800084 	addi.w      	\$a0, \$a0, 0
-			5c: R_LARCH_GOT_PC_LO12	TLS1
-			5c: R_LARCH_RELAX	\*ABS\*
+			5c: R_LARCH_TLS_GD_PCADD_LO12	.Lpcadd_hi7
diff --git a/ld/testsuite/ld-loongarch-elf/pic.exp b/ld/testsuite/ld-loongarch-elf/pic.exp
index 510c3fd8c0d..177ce89313f 100644
--- a/ld/testsuite/ld-loongarch-elf/pic.exp
+++ b/ld/testsuite/ld-loongarch-elf/pic.exp
@@ -111,7 +111,7 @@  set link_tests [list \
 run_ld_link_tests $link_tests
 
 
-
+if [istarget "loongarch64-*-*"] {
 set link_tests_libc [list \
   [list \
     "$testname readelf -s/-r nopic-global-so" \
@@ -208,6 +208,6 @@  set link_exec_tests [list \
 #   8:linker warning (optional)
 #   9:ld trailing options, placed after object files (optional)
 run_ld_link_exec_tests $link_exec_tests
-
+}
 
 #set verbose  old_verbose