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CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(35042699022)(376014)(1800799024)(14060799003)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2025 12:44:00.2532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be873baf-b689-48ff-6939-08de3332cc58 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001AF.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB10845 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, PROLO_LEO1, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch adds support for FEAT_TEV feature enabled by "+tev" flag along with support for following instructions. * TENTER * TEXIT TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED operand to handle the not_balanced (NB) argument , where as a new operand AARCH64_OPND_NOT_BALANCED_1 is added to support the NB (not_balanced) argument in TEXIT instruction. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath --- gas/config/tc-aarch64.c | 37 +++++++++++++++++-- gas/doc/c-aarch64.texi | 2 + gas/testsuite/gas/aarch64/poe2-invalid-1.l | 36 +++++++++--------- gas/testsuite/gas/aarch64/tev-invalid-1.d | 4 ++ gas/testsuite/gas/aarch64/tev-invalid-1.l | 21 +++++++++++ gas/testsuite/gas/aarch64/tev-invalid-1.s | 25 +++++++++++++ gas/testsuite/gas/aarch64/tev-invalid-2.d | 4 ++ gas/testsuite/gas/aarch64/tev-invalid-2.l | 20 ++++++++++ gas/testsuite/gas/aarch64/tev.d | 28 ++++++++++++++ gas/testsuite/gas/aarch64/tev.s | 26 +++++++++++++ include/opcode/aarch64.h | 6 ++- opcodes/aarch64-asm-2.c | 1 + opcodes/aarch64-dis-2.c | 43 ++++++++++++++++------ opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 1 + opcodes/aarch64-tbl-2.h | 2 + opcodes/aarch64-tbl.h | 11 ++++++ 17 files changed, 235 insertions(+), 33 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.d create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.l create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-1.s create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-2.d create mode 100644 gas/testsuite/gas/aarch64/tev-invalid-2.l create mode 100644 gas/testsuite/gas/aarch64/tev.d create mode 100644 gas/testsuite/gas/aarch64/tev.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 5eae44b1b8a..24cb00e27b6 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -261,6 +261,7 @@ set_fatal_syntax_error (const char *error) return the information of the parsed result, e.g. register number, on success. */ #define PARSE_FAIL -1 +#define PARSE_FAIL2 -2 /* This is an invalid condition code that means no conditional field is present. */ @@ -4595,6 +4596,31 @@ parse_barrier (char **str) return o->value; } +/* Parse an option for instructions with not_balanced optional operands. On + sucess, return the encoding for the matched operand. On failure, return + PARSE_FAIL. However, if the instruction is TEXIT with no optional operands, + on failure return PARSE_FAIL2 instead. */ + +static int +parse_not_balanced (char **str) +{ + char *p, *q; + const struct aarch64_name_value_pair *o; + + p = q = *str; + while (ISALPHA (*q)) + q++; + + o = str_hash_find_n (aarch64_barrier_opt_hsh, p, q - p); + if ((q-p) == 0 && !o) + return PARSE_FAIL2; + else if (!o) + return PARSE_FAIL; + + *str = q; + return o->value; +} + /* Parse an option for barrier, bti and guarded control stack data synchronization instructions. Return true on matching the target options else return false. */ @@ -6442,6 +6468,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, break; case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: operand->imm.value = default_value; break; @@ -8177,14 +8204,17 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->barrier = aarch64_barrier_dsb_nxs_options + val; break; + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NOT_BALANCED: - val = parse_barrier (&str); - if (val != PARSE_FAIL) + val = parse_not_balanced (&str); + if (val == PARSE_FAIL2) + goto failure; + else if (val != PARSE_FAIL) info->imm.value = val; else { set_syntax_error (_("the specified operand is not accepted in" - " TCHANGE instruction")); + " TCHANGE/TENTER/TEXIT instructions")); /* Turn off backtrack as this optional operand is present. */ backtrack_pos = 0; goto failure; @@ -10847,6 +10877,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES}, {"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)}, {"poe2", AARCH64_FEATURE (S1POE2), AARCH64_NO_FEATURES}, + {"tev", AARCH64_FEATURE (TEV), AARCH64_NO_FEATURES}, {"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)}, {"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)}, {"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 2064d22706b..261e5abd06d 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -367,6 +367,8 @@ automatically cause those extensions to be disabled. @tab Enable the Translation Hardening Extension. @item @code{tme} @tab @tab Enable the Transactional Memory Extension. +@item @code{tve} @tab + @tab TIndex Exception-like Vector Extension. @item @code{wfxt} @tab @tab Enable @code{wfet} and @code{wfit} instructions. @item @code{xs} @tab diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.l b/gas/testsuite/gas/aarch64/poe2-invalid-1.l index df536613fde..4998b76ed0e 100644 --- a/gas/testsuite/gas/aarch64/poe2-invalid-1.l +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.l @@ -2,17 +2,17 @@ .*: Error: constant expression required at operand 2 -- `tchangef x0,x31' .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,x3' .*: Error: comma expected between operands at operand 2 -- `tchangef x7' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,x10' +.*: Error: unexpected comma before the omitted optional operand at operand 3 -- `tchangef x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x30,x0,x10' .*: Error: comma expected between operands at operand 2 -- `tchangef x10 x0' .*: Error: expected an integer or zero register at operand 1 -- `tchangef #1,#100' .*: Error: expected an integer or zero register at operand 1 -- `tchangef #10,x0' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,x1,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x0,x1,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangef x1,x3 nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x3,x7,n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x3,x7,n' .*: Error: unexpected characters following instruction at operand 3 -- `tchangef x7,x15,nb,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x15,x30,Nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x30,x0,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x30,x0,nB' .*: Error: constant expression required at operand 2 -- `tchangef x10,NB,NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,NB' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10' @@ -22,10 +22,10 @@ .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#15' .*: Error: constant expression required at operand 2 -- `tchangef x10,nb,#127' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x0,#1,nB' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x1,#3,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x1,#3,Nb' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x3,#777,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangef x7,#15,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangef x7,#15,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangef x15,#31 NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#63,nb' .*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,#127' @@ -33,17 +33,17 @@ .*: Error: constant expression required at operand 2 -- `tchangeb x0,x31' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,x3' .*: Error: comma expected between operands at operand 2 -- `tchangeb x7' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,x10' +.*: Error: unexpected comma before the omitted optional operand at operand 3 -- `tchangeb x15,x30,' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x30,x0,x10' .*: Error: comma expected between operands at operand 2 -- `tchangeb x10 x0' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb #1,#100' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb #10,x0' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,x1,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x0,x1,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangeb x1,x3 nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x3,x7,n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x3,x7,n' .*: Error: unexpected characters following instruction at operand 3 -- `tchangeb x7,x15,nb,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x15,x30,Nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x30,x0,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x15,x30,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x30,x0,nB' .*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,NB' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10' @@ -53,10 +53,10 @@ .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#15' .*: Error: constant expression required at operand 2 -- `tchangeb x10,nb,#127' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x0,#1,nB' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x1,#3,Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x0,#1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x1,#3,Nb' .*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x3,#777,nb' -.*: Error: the specified operand is not accepted in TCHANGE instruction at operand 3 -- `tchangeb x7,#15,nbb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 3 -- `tchangeb x7,#15,nbb' .*: Error: comma expected between operands at operand 3 -- `tchangeb x15,#31 NB' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#63,nb' .*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,#127' diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.d b/gas/testsuite/gas/aarch64/tev-invalid-1.d new file mode 100644 index 00000000000..f6a659e5888 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.d @@ -0,0 +1,4 @@ +#name: Invalid tev instructions. +#source: tev-invalid-1.s +#as: -march=armv8-a+tev +#error_output: tev-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.l b/gas/testsuite/gas/aarch64/tev-invalid-1.l new file mode 100644 index 00000000000..66d1b3b3492 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.l @@ -0,0 +1,21 @@ +.*: Assembler messages: +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #128' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #3111' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777' +.*: Error: constant expression required at operand 1 -- `tenter nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #-10,nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #1,nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #3,Nb' +.*: Error: immediate value out of range 0 to 127 at operand 1 -- `tenter #777,nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 2 -- `tenter #15,nbb' +.*: Error: comma expected between operands at operand 2 -- `tenter #31 NB' +.*: Error: immediate operand required at operand 1 -- `tenter x10,#127' +.*: Error: constant expression required at operand 1 -- `tenter NB,#128' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit x0' +.*: Error: operand 1 must be a 1-bit not_balanced optional operand -- `texit #10' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit n' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit nN' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit nB' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit Nb' +.*: Error: the specified operand is not accepted in TCHANGE/TENTER/TEXIT instructions at operand 1 -- `texit x0,nb' diff --git a/gas/testsuite/gas/aarch64/tev-invalid-1.s b/gas/testsuite/gas/aarch64/tev-invalid-1.s new file mode 100644 index 00000000000..44925fd19ba --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-1.s @@ -0,0 +1,25 @@ +#TENTER instructions + tenter #-10 + tenter #128 + tenter #3111 + tenter #777 + tenter nb, #127 + +#TENTER instructions with not_balanced + tenter #-10, nb + tenter #1, nB + tenter #3, Nb + tenter #777, nb + tenter #15, nbb + tenter #31 NB + tenter x10, #127 + tenter NB, #128 + +#TEXIT instructions + texit x0 + texit #10 + texit n + texit nN + texit nB + texit Nb + texit x0, nb diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.d b/gas/testsuite/gas/aarch64/tev-invalid-2.d new file mode 100644 index 00000000000..6d5c9c1b9aa --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-2.d @@ -0,0 +1,4 @@ +#name: TENTER and TEXIT instructions without +tev flag. +#source: tev.s +#as: -march=armv8-a +#error_output: tev-invalid-2.l diff --git a/gas/testsuite/gas/aarch64/tev-invalid-2.l b/gas/testsuite/gas/aarch64/tev-invalid-2.l new file mode 100644 index 00000000000..9f438e742ed --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev-invalid-2.l @@ -0,0 +1,20 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `tenter #0' +.*: Error: selected processor does not support `tenter #1' +.*: Error: selected processor does not support `tenter #3' +.*: Error: selected processor does not support `tenter #7' +.*: Error: selected processor does not support `tenter #15' +.*: Error: selected processor does not support `tenter #31' +.*: Error: selected processor does not support `tenter #63' +.*: Error: selected processor does not support `tenter #127' +.*: Error: selected processor does not support `tenter #0,nb' +.*: Error: selected processor does not support `tenter #1,nb' +.*: Error: selected processor does not support `tenter #3,nb' +.*: Error: selected processor does not support `tenter #7,nb' +.*: Error: selected processor does not support `tenter #15,nb' +.*: Error: selected processor does not support `tenter #31,NB' +.*: Error: selected processor does not support `tenter #63,nb' +.*: Error: selected processor does not support `tenter #127,NB' +.*: Error: selected processor does not support `texit' +.*: Error: selected processor does not support `texit nb' +.*: Error: selected processor does not support `texit NB' diff --git a/gas/testsuite/gas/aarch64/tev.d b/gas/testsuite/gas/aarch64/tev.d new file mode 100644 index 00000000000..a8d9f447617 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev.d @@ -0,0 +1,28 @@ +#objdump: -dr +#as: -march=armv8-a+tev + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d4e00000 tenter #0x0 +.*: d4e00020 tenter #0x1 +.*: d4e00060 tenter #0x3 +.*: d4e000e0 tenter #0x7 +.*: d4e001e0 tenter #0xf +.*: d4e003e0 tenter #0x1f +.*: d4e007e0 tenter #0x3f +.*: d4e00fe0 tenter #0x7f +.*: d4e20000 tenter #0x0, nb +.*: d4e20020 tenter #0x1, nb +.*: d4e20060 tenter #0x3, nb +.*: d4e200e0 tenter #0x7, nb +.*: d4e201e0 tenter #0xf, nb +.*: d4e203e0 tenter #0x1f, nb +.*: d4e207e0 tenter #0x3f, nb +.*: d4e20fe0 tenter #0x7f, nb +.*: d6ff03e0 texit +.*: d6ff07e0 texit nb +.*: d6ff07e0 texit nb diff --git a/gas/testsuite/gas/aarch64/tev.s b/gas/testsuite/gas/aarch64/tev.s new file mode 100644 index 00000000000..d6b1bfdb741 --- /dev/null +++ b/gas/testsuite/gas/aarch64/tev.s @@ -0,0 +1,26 @@ +#TENTER instruction + tenter #0 + tenter #1 + tenter #3 + tenter #7 + tenter #15 + tenter #31 + tenter #63 + tenter #127 + +#TENTER instruction with not_balanced + tenter #0, nb + tenter #1, nb + tenter #3, nb + tenter #7, nb + tenter #15, nb + tenter #31, NB + tenter #63, nb + tenter #127, NB + +#TEXIT instruction + texit + +#TEXIT instruction with not_balanced + texit nb + texit NB diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d4d2fab5d11..43af6f05ff5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -265,6 +265,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_MOP4, /* POE2 instructions. */ AARCH64_FEATURE_S1POE2, + /* TEV instructions. */ + AARCH64_FEATURE_TEV, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -675,7 +677,8 @@ enum aarch64_opnd AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ - AARCH64_OPND_NOT_BALANCED, /* a 1-bit not_balanced optional operand. */ + AARCH64_OPND_NOT_BALANCED, /* a 1-bit not_balanced optional operand. */ + AARCH64_OPND_NOT_BALANCED_1, /* a 1-bit not_balanced optional operand. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ @@ -1136,6 +1139,7 @@ enum aarch64_insn_class movewide, pcreladdr, s1poe2, + tev, ic_system, sme_fp_sd, sme_int_sd, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index c93447742f8..919b6669722 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -931,6 +931,7 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_PCREL9: case AARCH64_OPND_ADDR_PCREL14: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 657e1ec4f37..855d00d3c4f 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -26335,10 +26335,20 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 11010100x11xxxxxxxxxxxxxxxx0xx00. */ - return A64_OPID_d4600000_tcancel_TME_UIMM16; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11010100011xxxxxxxxxxxxxxxx0xx00. */ + return A64_OPID_d4600000_tcancel_TME_UIMM16; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11010100111xxxxxxxxxxxxxxxx0xx00. */ + return A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED; + } } } } @@ -26430,19 +26440,29 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10101100x1xxxxxxxxxxxxxxxx0xxxx. */ - return A64_OPID_d63f0000_blr_Rn; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010110001xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d63f0000_blr_Rn; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010110101xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d6bf03e0_drps; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x10101101x1xxxxxxxxxxxxxxxx0xxxx. */ - return A64_OPID_d6bf03e0_drps; + x1010110x11xxxxxxxxxxxxxxxx0xxxx. */ + return A64_OPID_d6ff03e0_texit_NOT_BALANCED_1; } } } @@ -37398,6 +37418,7 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_ADRP: case AARCH64_OPND_ADDR_PCREL9: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index fc88fe82ed3..de468488c08 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -105,6 +105,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_17}, "a 1-bit not_balanced optional operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10}, "a 1-bit not_balanced optional operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index fbefdd01933..0de4f2baf2d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5152,6 +5152,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; case AARCH64_OPND_NOT_BALANCED: + case AARCH64_OPND_NOT_BALANCED_1: if (opnd->imm.value) snprintf (buf, size, "%s", style_sub_mnem (styler, "nb")); break; diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 16b3448c828..fda9d456f3c 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -3999,5 +3999,7 @@ enum aarch64_opcode_idx A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED, A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED, A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED, + A64_OPID_d4e00000_tenter_UIMM7_NOT_BALANCED, + A64_OPID_d6ff03e0_texit_NOT_BALANCED_1, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 572385621db..f7b7d610563 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3066,6 +3066,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 = AARCH64_FEATURES (2, SME_MOP4, SME_I16I64); static const aarch64_feature_set aarch64_feature_s1poe2 = AARCH64_FEATURE (S1POE2); +static const aarch64_feature_set aarch64_feature_tev = + AARCH64_FEATURE (TEV); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3191,6 +3193,7 @@ static const aarch64_feature_set aarch64_feature_s1poe2 = #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32 #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64 #define S1POE2 &aarch64_feature_s1poe2 +#define TEV &aarch64_feature_tev #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } @@ -3522,6 +3525,8 @@ static const aarch64_feature_set aarch64_feature_s1poe2 = FLAGS | F_STRICT, 0, TIED, NULL } #define S1POE2_INSN(NAME,OPCODE,MASK,OPS,QUALS, FLAGS) \ { NAME, OPCODE, MASK, s1poe2, 0, S1POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } +#define TEV_INSN(NAME,OPCODE,MASK,OPS,QUALS, FLAGS) \ + { NAME, OPCODE, MASK, tev, 0, TEV, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7756,6 +7761,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = S1POE2_INSN("tchangeb", 0xd5840000, 0xfffdfc00, OP3 (Rd, Rn, NOT_BALANCED), QL_DST_X2, F_OPD2_OPT | F_DEFAULT (0x0)), S1POE2_INSN("tchangeb", 0xd5940000, 0xfffdf000, OP3 (Rd, UIMM7, NOT_BALANCED), QL_DST_X1, F_OPD2_OPT | F_DEFAULT (0x0)), + /* TEV instructions. */ + TEV_INSN("tenter", 0xd4e00000, 0xfffdf01f, OP2 (UIMM7, NOT_BALANCED), QL_PRFM_PCREL, F_OPD1_OPT | F_DEFAULT (0x0)), + TEV_INSN("texit", 0xd6ff03e0, 0xfffffbff, OP1 (NOT_BALANCED_1), {}, F_OPD0_OPT | F_DEFAULT (0x0)), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7910,6 +7919,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 5-bit signed immediate") \ Y(IMMEDIATE, imm, "NOT_BALANCED", 0, F(FLD_imm1_17), \ "a 1-bit not_balanced optional operand") \ + Y(IMMEDIATE, imm, "NOT_BALANCED_1", 0, F(FLD_imm1_10), \ + "a 1-bit not_balanced optional operand") \ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ "a flag bit specifier giving an alternative value for each flag") \ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \