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(unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJBxpeSuyy5pdXxEAQ--.50049S2; Tue, 02 Dec 2025 19:21:18 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, cailulu@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, hejinyang@loongson.cn, c@jia.je, mengqinggang@loongson.cn Subject: [PATCH v2 12/12] LoongArch32: Fixed several regression test failures in gas and ld Date: Tue, 2 Dec 2025 19:17:45 +0800 Message-Id: <20251202111745.1558349-13-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251202111745.1558349-1-mengqinggang@loongson.cn> References: <20251202111745.1558349-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowJBxpeSuyy5pdXxEAQ--.50049S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: Lulu Cai Fixed several test failures caused by the LoongArch32 assembler adding labels during assembly. Additionally, skipped tests specific to LoongArch64. --- gas/testsuite/gas/loongarch/macro_op_32.d | 72 ++++++++++--------- ld/testsuite/ld-loongarch-elf/disas-jirl-32.d | 14 ++-- ld/testsuite/ld-loongarch-elf/macro_op_32.d | 72 ++++++++++--------- ld/testsuite/ld-loongarch-elf/pic.exp | 4 +- 4 files changed, 88 insertions(+), 74 deletions(-) diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d index 8fd69922c14..2d6384dfeef 100644 --- a/gas/testsuite/gas/loongarch/macro_op_32.d +++ b/gas/testsuite/gas/loongarch/macro_op_32.d @@ -12,40 +12,46 @@ Disassembly of section .text: 4: 02bffc04 li.w \$a0, -1 8: 00150004 move \$a0, \$zero c: 02bffc04 li.w \$a0, -1 - 10: 1a000004 pcalau12i \$a0, 0 - 10: R_LARCH_GOT_PC_HI20 .L1 + +0+10 <.Lpcadd_hi0>: + 10: 1c000004 pcaddu12i \$a0, 0 + 10: R_LARCH_GOT_PCADD_HI20 .L1 10: R_LARCH_RELAX \*ABS\* 14: 28800084 ld.w \$a0, \$a0, 0 - 14: R_LARCH_GOT_PC_LO12 .L1 + 14: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi0 14: R_LARCH_RELAX \*ABS\* - 18: 1a000004 pcalau12i \$a0, 0 - 18: R_LARCH_GOT_PC_HI20 .L1 + +0+18 <.Lpcadd_hi1>: + 18: 1c000004 pcaddu12i \$a0, 0 + 18: R_LARCH_GOT_PCADD_HI20 .L1 18: R_LARCH_RELAX \*ABS\* 1c: 28800084 ld.w \$a0, \$a0, 0 - 1c: R_LARCH_GOT_PC_LO12 .L1 + 1c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi1 1c: R_LARCH_RELAX \*ABS\* - 20: 1a000004 pcalau12i \$a0, 0 - 20: R_LARCH_PCALA_HI20 .L1 - 20: R_LARCH_RELAX \*ABS\* + +0+20 <.Lpcadd_hi2>: + 20: 1c000004 pcaddu12i \$a0, 0 + 20: R_LARCH_PCADD_HI20 .L1 24: 02800084 addi.w \$a0, \$a0, 0 - 24: R_LARCH_PCALA_LO12 .L1 - 24: R_LARCH_RELAX \*ABS\* + 24: R_LARCH_PCADD_LO12 .Lpcadd_hi2 28: 14000004 lu12i.w \$a0, 0 28: R_LARCH_MARK_LA \*ABS\* 28: R_LARCH_ABS_HI20 .L1 2c: 03800084 ori \$a0, \$a0, 0x0 2c: R_LARCH_ABS_LO12 .L1 - 30: 1a000004 pcalau12i \$a0, 0 - 30: R_LARCH_PCALA_HI20 .L1 - 30: R_LARCH_RELAX \*ABS\* + +0+30 <.Lpcadd_hi3>: + 30: 1c000004 pcaddu12i \$a0, 0 + 30: R_LARCH_PCADD_HI20 .L1 34: 02800084 addi.w \$a0, \$a0, 0 - 34: R_LARCH_PCALA_LO12 .L1 - 34: R_LARCH_RELAX \*ABS\* - 38: 1a000004 pcalau12i \$a0, 0 - 38: R_LARCH_GOT_PC_HI20 .L1 + 34: R_LARCH_PCADD_LO12 .Lpcadd_hi3 + +0+38 <.Lpcadd_hi4>: + 38: 1c000004 pcaddu12i \$a0, 0 + 38: R_LARCH_GOT_PCADD_HI20 .L1 38: R_LARCH_RELAX \*ABS\* 3c: 28800084 ld.w \$a0, \$a0, 0 - 3c: R_LARCH_GOT_PC_LO12 .L1 + 3c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi4 3c: R_LARCH_RELAX \*ABS\* 40: 14000004 lu12i.w \$a0, 0 40: R_LARCH_TLS_LE_HI20 TLS1 @@ -53,21 +59,23 @@ Disassembly of section .text: 44: 03800084 ori \$a0, \$a0, 0x0 44: R_LARCH_TLS_LE_LO12 TLS1 44: R_LARCH_RELAX \*ABS\* - 48: 1a000004 pcalau12i \$a0, 0 - 48: R_LARCH_TLS_IE_PC_HI20 TLS1 + +0+48 <.Lpcadd_hi5>: + 48: 1c000004 pcaddu12i \$a0, 0 + 48: R_LARCH_TLS_IE_PCADD_HI20 TLS1 48: R_LARCH_RELAX \*ABS\* 4c: 28800084 ld.w \$a0, \$a0, 0 - 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 + 4c: R_LARCH_TLS_IE_PCADD_LO12 .Lpcadd_hi5 4c: R_LARCH_RELAX \*ABS\* - 50: 1a000004 pcalau12i \$a0, 0 - 50: R_LARCH_TLS_LD_PC_HI20 TLS1 - 50: R_LARCH_RELAX \*ABS\* + +0+50 <.Lpcadd_hi6>: + 50: 1c000004 pcaddu12i \$a0, 0 + 50: R_LARCH_TLS_LD_PCADD_HI20 TLS1 54: 02800084 addi.w \$a0, \$a0, 0 - 54: R_LARCH_GOT_PC_LO12 TLS1 - 54: R_LARCH_RELAX \*ABS\* - 58: 1a000004 pcalau12i \$a0, 0 - 58: R_LARCH_TLS_GD_PC_HI20 TLS1 - 58: R_LARCH_RELAX \*ABS\* + 54: R_LARCH_TLS_LD_PCADD_LO12 .Lpcadd_hi6 + +0+58 <.Lpcadd_hi7>: + 58: 1c000004 pcaddu12i \$a0, 0 + 58: R_LARCH_TLS_GD_PCADD_HI20 TLS1 5c: 02800084 addi.w \$a0, \$a0, 0 - 5c: R_LARCH_GOT_PC_LO12 TLS1 - 5c: R_LARCH_RELAX \*ABS\* + 5c: R_LARCH_TLS_GD_PCADD_LO12 .Lpcadd_hi7 diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d index cab7a5d4c99..a78bf24e7d3 100644 --- a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d +++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d @@ -7,11 +7,9 @@ Disassembly of section .text: -00000000.* <_start>: -[ ]+0:[ ]+1a000014[ ]+pcalau12i[ ]+\$t8,[ ]+0 -[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+_start -[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -[ ]+4:[ ]+02800294[ ]+addi.w[ ]+\$t8,[ ]+\$t8,[ ]+0 -[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+_start -[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -[ ]+8:[ ]+4c000281[ ]+jirl[ ]+\$ra,[ ]+\$t8,[ ]+0 +0+ <_start>: + 0: 1c000014 pcaddu12i \$t8, 0 + 0: R_LARCH_PCADD_HI20 _start + 4: 02800294 addi.w \$t8, \$t8, 0 + 4: R_LARCH_PCADD_LO12 .Lpcadd_hi0 + 8: 4c000281 jirl \$ra, \$t8, 0 diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d index 8fd69922c14..2d6384dfeef 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d @@ -12,40 +12,46 @@ Disassembly of section .text: 4: 02bffc04 li.w \$a0, -1 8: 00150004 move \$a0, \$zero c: 02bffc04 li.w \$a0, -1 - 10: 1a000004 pcalau12i \$a0, 0 - 10: R_LARCH_GOT_PC_HI20 .L1 + +0+10 <.Lpcadd_hi0>: + 10: 1c000004 pcaddu12i \$a0, 0 + 10: R_LARCH_GOT_PCADD_HI20 .L1 10: R_LARCH_RELAX \*ABS\* 14: 28800084 ld.w \$a0, \$a0, 0 - 14: R_LARCH_GOT_PC_LO12 .L1 + 14: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi0 14: R_LARCH_RELAX \*ABS\* - 18: 1a000004 pcalau12i \$a0, 0 - 18: R_LARCH_GOT_PC_HI20 .L1 + +0+18 <.Lpcadd_hi1>: + 18: 1c000004 pcaddu12i \$a0, 0 + 18: R_LARCH_GOT_PCADD_HI20 .L1 18: R_LARCH_RELAX \*ABS\* 1c: 28800084 ld.w \$a0, \$a0, 0 - 1c: R_LARCH_GOT_PC_LO12 .L1 + 1c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi1 1c: R_LARCH_RELAX \*ABS\* - 20: 1a000004 pcalau12i \$a0, 0 - 20: R_LARCH_PCALA_HI20 .L1 - 20: R_LARCH_RELAX \*ABS\* + +0+20 <.Lpcadd_hi2>: + 20: 1c000004 pcaddu12i \$a0, 0 + 20: R_LARCH_PCADD_HI20 .L1 24: 02800084 addi.w \$a0, \$a0, 0 - 24: R_LARCH_PCALA_LO12 .L1 - 24: R_LARCH_RELAX \*ABS\* + 24: R_LARCH_PCADD_LO12 .Lpcadd_hi2 28: 14000004 lu12i.w \$a0, 0 28: R_LARCH_MARK_LA \*ABS\* 28: R_LARCH_ABS_HI20 .L1 2c: 03800084 ori \$a0, \$a0, 0x0 2c: R_LARCH_ABS_LO12 .L1 - 30: 1a000004 pcalau12i \$a0, 0 - 30: R_LARCH_PCALA_HI20 .L1 - 30: R_LARCH_RELAX \*ABS\* + +0+30 <.Lpcadd_hi3>: + 30: 1c000004 pcaddu12i \$a0, 0 + 30: R_LARCH_PCADD_HI20 .L1 34: 02800084 addi.w \$a0, \$a0, 0 - 34: R_LARCH_PCALA_LO12 .L1 - 34: R_LARCH_RELAX \*ABS\* - 38: 1a000004 pcalau12i \$a0, 0 - 38: R_LARCH_GOT_PC_HI20 .L1 + 34: R_LARCH_PCADD_LO12 .Lpcadd_hi3 + +0+38 <.Lpcadd_hi4>: + 38: 1c000004 pcaddu12i \$a0, 0 + 38: R_LARCH_GOT_PCADD_HI20 .L1 38: R_LARCH_RELAX \*ABS\* 3c: 28800084 ld.w \$a0, \$a0, 0 - 3c: R_LARCH_GOT_PC_LO12 .L1 + 3c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi4 3c: R_LARCH_RELAX \*ABS\* 40: 14000004 lu12i.w \$a0, 0 40: R_LARCH_TLS_LE_HI20 TLS1 @@ -53,21 +59,23 @@ Disassembly of section .text: 44: 03800084 ori \$a0, \$a0, 0x0 44: R_LARCH_TLS_LE_LO12 TLS1 44: R_LARCH_RELAX \*ABS\* - 48: 1a000004 pcalau12i \$a0, 0 - 48: R_LARCH_TLS_IE_PC_HI20 TLS1 + +0+48 <.Lpcadd_hi5>: + 48: 1c000004 pcaddu12i \$a0, 0 + 48: R_LARCH_TLS_IE_PCADD_HI20 TLS1 48: R_LARCH_RELAX \*ABS\* 4c: 28800084 ld.w \$a0, \$a0, 0 - 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 + 4c: R_LARCH_TLS_IE_PCADD_LO12 .Lpcadd_hi5 4c: R_LARCH_RELAX \*ABS\* - 50: 1a000004 pcalau12i \$a0, 0 - 50: R_LARCH_TLS_LD_PC_HI20 TLS1 - 50: R_LARCH_RELAX \*ABS\* + +0+50 <.Lpcadd_hi6>: + 50: 1c000004 pcaddu12i \$a0, 0 + 50: R_LARCH_TLS_LD_PCADD_HI20 TLS1 54: 02800084 addi.w \$a0, \$a0, 0 - 54: R_LARCH_GOT_PC_LO12 TLS1 - 54: R_LARCH_RELAX \*ABS\* - 58: 1a000004 pcalau12i \$a0, 0 - 58: R_LARCH_TLS_GD_PC_HI20 TLS1 - 58: R_LARCH_RELAX \*ABS\* + 54: R_LARCH_TLS_LD_PCADD_LO12 .Lpcadd_hi6 + +0+58 <.Lpcadd_hi7>: + 58: 1c000004 pcaddu12i \$a0, 0 + 58: R_LARCH_TLS_GD_PCADD_HI20 TLS1 5c: 02800084 addi.w \$a0, \$a0, 0 - 5c: R_LARCH_GOT_PC_LO12 TLS1 - 5c: R_LARCH_RELAX \*ABS\* + 5c: R_LARCH_TLS_GD_PCADD_LO12 .Lpcadd_hi7 diff --git a/ld/testsuite/ld-loongarch-elf/pic.exp b/ld/testsuite/ld-loongarch-elf/pic.exp index 510c3fd8c0d..177ce89313f 100644 --- a/ld/testsuite/ld-loongarch-elf/pic.exp +++ b/ld/testsuite/ld-loongarch-elf/pic.exp @@ -111,7 +111,7 @@ set link_tests [list \ run_ld_link_tests $link_tests - +if [istarget "loongarch64-*-*"] { set link_tests_libc [list \ [list \ "$testname readelf -s/-r nopic-global-so" \ @@ -208,6 +208,6 @@ set link_exec_tests [list \ # 8:linker warning (optional) # 9:ld trailing options, placed after object files (optional) run_ld_link_exec_tests $link_exec_tests - +} #set verbose old_verbose