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Tue, 2 Dec 2025 06:19:46 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 4arb5savbw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 02 Dec 2025 06:19:46 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 5B26Jf4a28180976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 2 Dec 2025 06:19:42 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 31FCE20043; Tue, 2 Dec 2025 06:19:41 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8916C20040; Tue, 2 Dec 2025 06:19:40 +0000 (GMT) Received: from kubota.pok.stglabs.ibm.com (unknown [9.114.39.181]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 2 Dec 2025 06:19:40 +0000 (GMT) From: Abhay Kandpal To: binutils@sourceware.org Cc: jskumari@linux.ibm.com, abhay.k@ibm.com, Abhay Kandpal Subject: [PATCH v4] PowerPC: Support for eTCE (RFC02662) Date: Tue, 2 Dec 2025 01:19:26 -0500 Message-ID: <20251202061926.13864-1-abhay@linux.ibm.com> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: msLA6p08KOSDTpNfNoHwwDA-jOFuLHI7 X-Proofpoint-ORIG-GUID: msLA6p08KOSDTpNfNoHwwDA-jOFuLHI7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI5MDAyMCBTYWx0ZWRfX5/mBxRKxSCEw PzSocRTnb8fVTGoAfrj1+zzCiU/peyKh4F+IkjFMDhe1XEpziDRKAcCll6fAEGQzNOB3a1Ng/Cg NoxbfTCMcZHsVcMXSaGbw0zStU5x+ePzqFlyMSJ5TA6VAH2aPw0x1Jo688XhFStk0fbWJFMhDHl /Zp1b+OuiA5jS5KhdGXJFXGaGCoWs2jNH/Ml+syMJng9lJG7U92unrVtt2EE7N51DI//unyE2wF oOoGeM/T8O1GyrhcKPFIUs70xUrygeXxGxok6wZy6teCiquqWVWzBmn2AMDvwxlgg9ELaaZTdQW qS5Q3BvJBIQNXRN/aGeKo8ann5QtwMVpF7PmRSLSLPPhGTqwdkhkOqSpF4EViapWwVrNh0k9GR6 bO3NkCq9jV1EqZ+lGqkXAjxGCONq+g== X-Authority-Analysis: v=2.4 cv=dYGNHHXe c=1 sm=1 tr=0 ts=692e8503 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=KW-6jIEpZpNE6rUeGo8A:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511290020 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org opcodes/ * ppc-opc.c (XTLBIE_MASK, XTLBIEIO_MASK): New macros. (powerpc_opcodes): Add tlbiep, tlbieio, tlbsyncio, ptesyncio. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise. --- This patch is reg tested. Changes from v3->v4 XTLBIE_MASK)> gas/testsuite/gas/ppc/future.d | 5 +++++ gas/testsuite/gas/ppc/future.s | 5 +++++ opcodes/ppc-opc.c | 13 +++++++++++++ 3 files changed, 23 insertions(+) diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d index efb3ee8428d..629cae637f1 100644 --- a/gas/testsuite/gas/ppc/future.d +++ b/gas/testsuite/gas/ppc/future.d @@ -109,4 +109,9 @@ Disassembly of section \.text: .*: (4c 06 00 7c|7c 00 06 4c) ccmclean .*: (cc 06 00 7c|7c 00 06 cc) ccmrl .*: (26 22 40 7c|7c 40 22 26) mtlpl r4,r2 +.*: (64 10 8f 7c|7c 8f 10 64) tlbiep r2,r4,3,1,1 +.*: (64 10 60 7c|7c 60 10 64) tlbiep r2,r3 +.*: (24 38 c8 7c|7c c8 38 24) tlbieio r7,r6,2 +.*: (68 04 20 7d|7d 20 04 68) tlbsyncio r9 +.*: (a8 04 a0 7c|7c a0 04 a8) ptesyncio r5 #pass diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s index e66465a7418..c7b42688a40 100644 --- a/gas/testsuite/gas/ppc/future.s +++ b/gas/testsuite/gas/ppc/future.s @@ -83,4 +83,9 @@ _start: ccmclean ccmrl mtlpl 4, 2 + tlbiep 2, 4, 3, 1, 1 + tlbiep 2, 3 + tlbieio 7, 6, 2 + tlbsyncio 9 + ptesyncio 5 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 867801a83d2..2305e07051b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4628,6 +4628,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); field. */ #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) +/* The mask of TLB invalidate Entry with 20th bit specified */ +#define XTLBIE_MASK (X_MASK | (1<<20)) + +/* The mask of TLB invalidate Entry for I/O device */ +#define XTLBIEIO_MASK (XTLBIE_MASK | (3<<16)) + /* An X form wait instruction with everything filled in except the WC and PL fields. */ #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK) @@ -7238,6 +7244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"iseleq", XISEL(31,15,2), X_MASK, PPCISEL, EXT, {RT, RA0, RB}}, {"isel", XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, BC}}, +{"tlbieio", X(31,18), XTLBIEIO_MASK, FUTURE, 0, {RB, RS, RIC}}, {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, @@ -7297,6 +7304,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, +{"tlbiep", X(31,50), XTLBIE_MASK, FUTURE, TITAN, {RB, RS, RIC, PRS, X_R}}, + {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, @@ -8605,6 +8614,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxvrll", X(31,557), XX1_MASK, PPCVSXF, 0, {XT6, RA0, RB}}, +{"tlbsyncio", X(31,564), XRARB_MASK, FUTURE, 0, {RS}}, + {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, @@ -8630,6 +8641,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, +{"ptesyncio", X(31,596), XRARB_MASK, FUTURE, 0, {RS}}, + {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},