@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for AMD Zen6 processor.
+
* Emit an SFrame FRE with zero offsets to convey an undefined return address
in the SFrame stack trace format.
@@ -1091,6 +1091,7 @@ static const arch_entry cpu_arch[] =
ARCH (znver3, ZNVER, ZNVER3, false),
ARCH (znver4, ZNVER, ZNVER4, false),
ARCH (znver5, ZNVER, ZNVER5, false),
+ ARCH (znver6, ZNVER, ZNVER6, false),
ARCH (btver1, BT, BTVER1, false),
ARCH (btver2, BT, BTVER2, false),
@@ -1208,6 +1209,7 @@ static const arch_entry cpu_arch[] =
VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
ANY_AVX512_VP2INTERSECT, reset),
+ VECARCH (avx512_bmm, AVX512_BMM, ANY_AVX512_BMM, reset),
SUBARCH (tdx, TDX, TDX, false),
SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
@@ -126,6 +126,7 @@ processor names are recognized:
@code{znver3},
@code{znver4},
@code{znver5},
+@code{znver6},
@code{btver1},
@code{btver2},
@code{generic32} and
@@ -198,6 +199,7 @@ accept various extension mnemonics. For example,
@code{avx512_bf16},
@code{avx_vnni},
@code{avx512_fp16},
+@code{avx512_bmm},
@code{prefetchi},
@code{avx_ifma},
@code{avx_vnni_int8},
@@ -1691,9 +1693,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
-@item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
-@item @samp{generic32}
-@item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
+@item @samp{znver4} @tab @samp{znver5} @tab @samp{znver6} @tab @samp{btver1}
+@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
+@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
@@ -1710,9 +1712,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
-@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{.avx10.1}
-@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
-@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
+@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{avx512_bmm}
+@item @samp{.avx10.1} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
+@item @samp{.ibt} @tab @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
new file mode 100644
@@ -0,0 +1,16 @@
+#source: arch-16.s
+#as: -march=znver6
+#objdump: -dw
+#name: i386 arch 16 (znver6)
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
+[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
+#pass
new file mode 100644
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: i386 arch 6
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
+#pass
new file mode 100644
@@ -0,0 +1,8 @@
+# Test -march=
+ .text
+
+ vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
+ vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
+ vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
+ vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
+ vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
new file mode 100644
@@ -0,0 +1,23 @@
+#objdump: -dw
+#name: i386 AVX512_BMM insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <bmm>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
+[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,21 @@
+# Check 32bit AVX512_BMM instructions
+
+ .text
+bmm:
+ .arch .noavx512vl
+ vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
+ vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
+ vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
+ vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
+
+ vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
+ vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
+ vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
+ vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
+
+ vbitrevb %zmm1, %zmm2 # AVX512_BMM
+ vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
+ vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
new file mode 100644
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:5: Error: operand .* `vbmacor16x16x16'
+.*:6: Error: operand .* `vbmacxor16x16x16'
new file mode 100644
@@ -0,0 +1,6 @@
+# Check illegal 32bit AVX512_BMM,AVX512VL instructions
+
+ .text
+_start:
+ vbmacor16x16x16 %xmm1, %xmm2, %xmm3
+ vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
new file mode 100644
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: i386 AVX512_BMM,AVX512VL insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <bmm>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,26 @@
+# Check 32bit AVX512_BMM,AVX512VL instructions
+
+ .text
+bmm:
+ vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
+
+ vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
+
+ vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL
+ vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
+ vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
@@ -215,6 +215,7 @@ if [gas_32_check] then {
run_dump_test "arch-14-znver3"
run_dump_test "arch-14-znver4"
run_dump_test "arch-15-znver5"
+ run_dump_test "arch-16-znver6"
run_dump_test "arch-10-btver1"
run_dump_test "arch-10-btver2"
run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
@@ -229,6 +230,7 @@ if [gas_32_check] then {
run_dump_test "arch-14"
run_dump_test "arch-14-1"
run_dump_test "arch-15"
+ run_dump_test "arch-16"
run_list_test "arch-dflt" "-march=generic32 -al"
run_list_test "arch-stk" "-march=generic32 -al"
run_dump_test "8087"
@@ -479,6 +481,9 @@ if [gas_32_check] then {
run_dump_test "avx512vnni-intel"
run_dump_test "avx512vnni_vl"
run_dump_test "avx512vnni_vl-intel"
+ run_dump_test "avx512_bmm"
+ run_dump_test "avx512_bmm_vl"
+ run_list_test "avx512_bmm_vl-inval"
run_dump_test "avx512bitalg"
run_dump_test "avx512bitalg-intel"
run_dump_test "avx512bitalg_vl"
new file mode 100644
@@ -0,0 +1,16 @@
+#source: x86-64-arch-6.s
+#as: -march=znver6
+#objdump: -dw
+#name: x86-64 arch 6 (znver6)
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
+[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
+#pass
new file mode 100644
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: x86-64 arch 6
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
+#pass
new file mode 100644
@@ -0,0 +1,8 @@
+# Test -march=
+ .text
+
+ vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
+ vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
+ vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
+ vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
+ vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
new file mode 100644
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: x86_64 AVX512_BMM BAD insns
+#source: x86-64-avx512_bmm-bad.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <\.text>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 08 80[\s]*\(bad\)
+[\s]*[a-f0-9]+:[\s]*c7[\s]*\(bad\)
+[\s]*[a-f0-9]+:[\s]*62 f6 ec 08 80[\s]*\(bad\)
+[\s]*[a-f0-9]+:[\s]*c7[\s]*.*
+#pass
new file mode 100644
@@ -0,0 +1,8 @@
+# Check Illegal 64-bit AVX512_BMM instructions
+
+ .text
+ #vbmacor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value).
+ .insn EVEX.128.NP.M6.W0 0x80, %xmm7, %xmm2, %xmm0
+
+ #vbmacxor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value).
+ .insn EVEX.128.NP.M6.W1 0x80, %xmm7, %xmm2, %xmm0
new file mode 100644
@@ -0,0 +1,23 @@
+#objdump: -dw
+#name: x86-64 AVX512_BMM insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <bmm>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,21 @@
+# Check 64bit AVX512_BMM instructions
+
+ .text
+bmm:
+ .arch .noavx512vl
+ vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
+ vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
+ vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
+ vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
+
+ vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
+ vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
+ vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
+ vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
+
+ vbitrevb %zmm1, %zmm2 # AVX512_BMM
+ vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
+ vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
+ vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
new file mode 100644
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:5: Error: operand .* `vbmacor16x16x16'
+.*:6: Error: operand .* `vbmacxor16x16x16'
new file mode 100644
@@ -0,0 +1,6 @@
+# Check illegal 64bit AVX512_BMM,AVX512VL instructions
+
+ .text
+_start:
+ vbmacor16x16x16 %xmm1, %xmm2, %xmm3
+ vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
new file mode 100644
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: x86-64 AVX512_BMM,AVX512VL insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <bmm>:
+[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2
+[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,26 @@
+# Check 64bit AVX512_BMM,AVX512VL instructions
+
+ .text
+bmm:
+ vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
+
+ vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
+
+ vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL
+ vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
+ vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL
+ vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL
+ vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
+ vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
@@ -182,6 +182,7 @@ run_dump_test "x86-64-arch-4"
run_dump_test "x86-64-arch-4-1"
run_dump_test "rmpquery"
run_dump_test "x86-64-arch-5"
+run_dump_test "x86-64-arch-6"
run_dump_test "x86-64-arch-2-lzcnt"
run_dump_test "x86-64-arch-2-prefetchw"
run_dump_test "x86-64-arch-2-bdver1"
@@ -193,6 +194,7 @@ run_dump_test "x86-64-arch-3-znver2"
run_dump_test "x86-64-arch-4-znver3"
run_dump_test "x86-64-arch-4-znver4"
run_dump_test "x86-64-arch-5-znver5"
+run_dump_test "x86-64-arch-6-znver6"
run_dump_test "x86-64-arch-2-btver1"
run_dump_test "x86-64-arch-2-btver2"
run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
@@ -441,6 +443,10 @@ run_dump_test "x86-64-avx512vnni"
run_dump_test "x86-64-avx512vnni-intel"
run_dump_test "x86-64-avx512vnni_vl"
run_dump_test "x86-64-avx512vnni_vl-intel"
+run_dump_test "x86-64-avx512_bmm"
+run_dump_test "x86-64-avx512_bmm_vl"
+run_list_test "x86-64-avx512_bmm_vl-inval"
+run_dump_test "x86-64-avx512_bmm-bad"
run_dump_test "x86-64-avx512bitalg"
run_dump_test "x86-64-avx512bitalg-intel"
run_dump_test "x86-64-avx512bitalg_vl"
@@ -193,4 +193,18 @@ static const struct dis386 evex_len_table[][3] = {
{
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7E_L_0) },
},
+
+ /* EVEX_LEN_MAP6_80_W_0 */
+ {
+ { Bad_Opcode },
+ { "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
+ { "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
+ },
+
+ /* EVEX_LEN_MAP6_80_W_1 */
+ {
+ { Bad_Opcode },
+ { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
+ { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
+ },
};
@@ -524,3 +524,13 @@
{
{ "vmovw", { EXwS, XMScalar }, 0 },
},
+ /* EVEX_W_MAP6_80 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_MAP6_80_W_0) },
+ { EVEX_LEN_TABLE (EVEX_LEN_MAP6_80_W_1) },
+ },
+ /* EVEX_W_MAP6_81 */
+ {
+ { "vbitrevb", { XM, EXx }, NO_PREFIX },
+ { Bad_Opcode }
+ }
@@ -1601,8 +1601,8 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_MAP6_80) },
+ { VEX_W_TABLE (EVEX_W_MAP6_81) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1602,6 +1602,8 @@ enum
EVEX_LEN_MAP5_6E,
EVEX_LEN_MAP5_7E,
+ EVEX_LEN_MAP6_80_W_0,
+ EVEX_LEN_MAP6_80_W_1,
};
enum
@@ -1855,6 +1857,8 @@ enum
EVEX_W_MAP5_6E_P_1,
EVEX_W_MAP5_7A_P_3,
EVEX_W_MAP5_7E_P_1,
+ EVEX_W_MAP6_80,
+ EVEX_W_MAP6_81,
};
typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
@@ -98,6 +98,8 @@ static const dependency isa_dependencies[] =
"ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
{ "ZNVER5",
"ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" },
+ { "ZNVER6",
+ "ZNVER5|AVX512_BMM|AVX_NE_CONVERT|AVX_IFMA|AVX_VNNI_INT8|AVX512_FP16" },
{ "BTVER1",
"GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
{ "BTVER2",
@@ -208,6 +210,8 @@ static const dependency isa_dependencies[] =
"AVX512BW" },
{ "AVX512_VP2INTERSECT",
"AVX512F" },
+ { "AVX512_BMM",
+ "AVX512BW" },
{ "AVX512_BF16",
"AVX512BW" },
{ "AVX512_FP16",
@@ -417,6 +421,7 @@ static bitfield cpu_flags[] =
BITFIELD (AVX512_BITALG),
BITFIELD (AVX512_BF16),
BITFIELD (AVX512_VP2INTERSECT),
+ BITFIELD (AVX512_BMM),
BITFIELD (TDX),
BITFIELD (AVX_VNNI),
BITFIELD (AVX512_FP16),
@@ -205,6 +205,8 @@ enum i386_cpu
CpuAVX512_BF16,
/* Intel AVX-512 VP2INTERSECT Instructions support required. */
CpuAVX512_VP2INTERSECT,
+ /* AMD AVX-512 BMM Instructions support required. */
+ CpuAVX512_BMM,
/* TDX Instructions support required. */
CpuTDX,
/* Intel AVX VNNI Instructions support required. */
@@ -497,6 +499,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx512_bitalg:1;
unsigned int cpuavx512_bf16:1;
unsigned int cpuavx512_vp2intersect:1;
+ unsigned int cpuavx512_bmm:1;
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
@@ -3145,6 +3145,14 @@ vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSu
// AVX-NE-CONVERT instructions end.
+// AVX512_BMM instructions.
+
+vbmacor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW0|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+vbmacxor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW1|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+vbitrevb, 0x81, AVX512_BMM, Modrm|EVexDYN|VexW0|Masking|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+
+// AVX512_BMM instructions end.
+
// ENQCMD instructions.
enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }