[v3] RISC-V: Add support for svvptc extension.
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Commit Message
This implements the svvptc extensons, version 1.0[1].
[1] https://github.com/riscv/riscv-svvptc
Changes for v3:
- Delete the INSN_CLASS_* of svvptc.
Changes for v2:
- Add the github link of svvptc.
bfd/ChangeLog:
* elfxx-riscv.c: Handle svvptc.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
---
bfd/elfxx-riscv.c | 1 +
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
3 files changed, 4 insertions(+)
--
2.43.0
@@ -1479,6 +1479,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"svvptc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssqosid", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssnpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smnpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -16,6 +16,8 @@
* Add support for the x86 Zhaoxin PadLock XMODX instructions.
+* Add support for the RISC-V svvptc extension, version 1.0.
+
Changes in 2.44:
* Add support for the x86 Intel Diamond Rapids AMX instructions, including
@@ -139,6 +139,7 @@ All available -march extensions for RISC-V:
svinval 1.0
svnapot 1.0
svpbmt 1.0
+ svvptc 1.0
ssqosid 1.0
ssnpm 1.0
smnpm 1.0