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(unknown [8.129.0.173]) by APP-05 (Coremail) with SMTP id zQCowADXEwwKxvxnfSLpCA--.281S2; Mon, 14 Apr 2025 16:23:40 +0800 (CST) From: Dongyan Chen To: binutils@sourceware.org Cc: kito.cheng@gmail.com, nelson@rivosinc.com, jbeulich@suse.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.ac.cn, shiyulong@iscas.ac.cn, cyy@cyyself.name, Dongyan Chen Subject: [PATCH] RISC-V: Add support for zvfbfa and zvfofp8min extensions. Date: Mon, 14 Apr 2025 16:23:28 +0800 Message-ID: <20250414082328.1917659-1-chendongyan@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CM-TRANSID: zQCowADXEwwKxvxnfSLpCA--.281S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZrW8Kw1DJr1xAw1rCFy3Jwb_yoWrZFWDpF s7ua1DAr98tFn7tFn3uF17K3y3ZwsrKry8KFW093s8Z3y3Jrs8Jrn3Aa45AFs5ZFs7KFnx ua13XrW5ua15u3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9014x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v n2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7x kEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E 67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCw CI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1x MIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIda VFxhVjvjDU0xZFpf9x0JUd-B_UUUUU= X-Originating-IP: [8.129.0.173] X-CM-SenderInfo: hfkh0v5rqj5tnq6l223fol2u1dvotugofq/ X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This implements the zvfbfa extension, version 0.1.0 and zvfofp8min extension, version 0.2.1[1] [1]https://github.com/aswaterman/riscv-misc/blob/e515758c24504cf3c16145bc763a76c59425ed1b/isa/zvfbfa.adoc bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle zvfbfa and zvfofp8min. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): New operand. --- bfd/elfxx-riscv.c | 12 ++++++++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 2 ++ include/opcode/riscv.h | 2 ++ 4 files changed, 18 insertions(+) -- 2.43.0 diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ec254915c76..02d1a8e1c5d 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1194,8 +1194,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "+zve64d,+zvl128b", check_implicit_always}, {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always}, {"zvfhmin", "+zve32f", check_implicit_always}, + {"zvfbfa", "+zve32f,+zfbfmin", check_implicit_always}, {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always}, {"zvfbfmin", "+zve32f", check_implicit_always}, + {"zvfofp8min", "+zve32f", check_implicit_always}, {"zve64d", "+d,+zve64f", check_implicit_always}, {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always}, {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always}, @@ -1404,8 +1406,10 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfofp8min", ISA_SPEC_CLASS_DRAFT, 0, 2, 1 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2764,10 +2768,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFA: + return riscv_subset_supports (rps, "zvfbfa"); case INSN_CLASS_ZVFBFMIN: return riscv_subset_supports (rps, "zvfbfmin"); case INSN_CLASS_ZVFBFWMA: return riscv_subset_supports (rps, "zvfbfwma"); + case INSN_CLASS_ZVFOFP8MIN: + return riscv_subset_supports (rps, "zvfofp8min"); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: @@ -3078,10 +3086,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVFBFA: + return "zvfbfa"; case INSN_CLASS_ZVFBFMIN: return "zvfbfmin"; case INSN_CLASS_ZVFBFWMA: return "zvfbfwma"; + case INSN_CLASS_ZVFOFP8MIN: + return "zvfofp8min"; case INSN_CLASS_ZVKB: return _("zvkb"); case INSN_CLASS_ZVKG: diff --git a/gas/NEWS b/gas/NEWS index b4fc2e9e9be..f73d76d08ea 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for RISC-V zvfbfa extension with version 0.1 and and zvfofp8min extension with version 0.2.1. + * Support for x86 AVX10.2 256 bit rounding has been dropped, as all the hardware would directly support 512 bit vecotr width. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index d77472fda9c..eed3a90f214 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -69,10 +69,12 @@ All available -march extensions for RISC-V: zve64d 1.0 zvbb 1.0 zvbc 1.0 + zvfbfa 0.1 zvfbfmin 1.0 zvfbfwma 1.0 zvfh 1.0 zvfhmin 1.0 + zvfofp8min 0.2 zvkb 1.0 zvkg 1.0 zvkn 1.0 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d76bcdb295c..5932ea189d8 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -507,8 +507,10 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFA, INSN_CLASS_ZVFBFMIN, INSN_CLASS_ZVFBFWMA, + INSN_CLASS_ZVFOFP8MIN, INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED,