diff mbox series

RISC-V: Add support for zvfbfa and zvfofp8min extensions.

Message ID 20250414082328.1917659-1-chendongyan@isrc.iscas.ac.cn
State New
Headers
Series RISC-V: Add support for zvfbfa and zvfofp8min extensions. |

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Commit Message

Dongyan Chen April 14, 2025, 8:23 a.m. UTC 
  This implements the zvfbfa extension, version 0.1.0 and zvfofp8min extension, version 0.2.1[1]

[1]https://github.com/aswaterman/riscv-misc/blob/e515758c24504cf3c16145bc763a76c59425ed1b/isa/zvfbfa.adoc

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle zvfbfa and zvfofp8min.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): New operand.

---
 bfd/elfxx-riscv.c                    | 12 ++++++++++++
 gas/NEWS                             |  2 ++
 gas/testsuite/gas/riscv/march-help.l |  2 ++
 include/opcode/riscv.h               |  2 ++
 4 files changed, 18 insertions(+)

--
2.43.0
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ec254915c76..02d1a8e1c5d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1194,8 +1194,10 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "+zve64d,+zvl128b", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
+  {"zvfbfa", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
+  {"zvfofp8min", "+zve32f", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
   {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
   {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
@@ -1404,8 +1406,10 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfbfa",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfofp8min",	ISA_SPEC_CLASS_DRAFT,		0, 2,  1 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2764,10 +2768,14 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVFBFA:
+      return riscv_subset_supports (rps, "zvfbfa");
     case INSN_CLASS_ZVFBFMIN:
       return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVFBFWMA:
       return riscv_subset_supports (rps, "zvfbfwma");
+    case INSN_CLASS_ZVFOFP8MIN:
+      return riscv_subset_supports (rps, "zvfofp8min");
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
@@ -3078,10 +3086,14 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbb");
     case INSN_CLASS_ZVBC:
       return _("zvbc");
+    case INSN_CLASS_ZVFBFA:
+      return "zvfbfa";
     case INSN_CLASS_ZVFBFMIN:
       return "zvfbfmin";
     case INSN_CLASS_ZVFBFWMA:
       return "zvfbfwma";
+    case INSN_CLASS_ZVFOFP8MIN:
+      return "zvfofp8min";
     case INSN_CLASS_ZVKB:
       return _("zvkb");
     case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index b4fc2e9e9be..f73d76d08ea 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-

+* Add support for RISC-V zvfbfa extension with version 0.1 and and zvfofp8min extension with version 0.2.1.
+
 * Support for x86 AVX10.2 256 bit rounding has been dropped, as all the
   hardware would directly support 512 bit vecotr width.

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d77472fda9c..eed3a90f214 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -69,10 +69,12 @@  All available -march extensions for RISC-V:
 	zve64d                                  1.0
 	zvbb                                    1.0
 	zvbc                                    1.0
+    zvfbfa                                  0.1
 	zvfbfmin                                1.0
 	zvfbfwma                                1.0
 	zvfh                                    1.0
 	zvfhmin                                 1.0
+    zvfofp8min                              0.2
 	zvkb                                    1.0
 	zvkg                                    1.0
 	zvkn                                    1.0
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d76bcdb295c..5932ea189d8 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -507,8 +507,10 @@  enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVFBFA,
   INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVFBFWMA,
+  INSN_CLASS_ZVFOFP8MIN,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,