diff mbox series

[15/21] Accept MCU mapped string operands as constants

Message ID 20250402121759.1962001-16-jovan.dmitrovic@htecgroup.com
State New
Headers
Series Integrate MIPS-Specific Support |

Commit Message

Jovan Dmitrovic April 2, 2025, 12:18 p.m. UTC 
  From: Faraz Shahbazker <fshahbazker@wavecomp.com>

This update improves support for the MIPS architecture within the
assembler tools and tests. In the file mips-opc.c, the function
decode_mips_operand has been modified to now accept constant values
as operands, enhancing the handling of MIPS instructions. Additionally,
new tests have been added, and the output for MIPS architecture tests
in the mxu.s file has been updated, including various operations with
operands. These changes enable better testing and broader functionality
coverage for MIPS processors, including constant values as input
parameters for instructions.

Cherry-picked 248e8bc
from https://github.com/MIPS/binutils-gdb

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>

opcodes/
	* mips-opc.c (decode_mips_operand): Accept constant
	integers in places of mapped string operands.

gas/
	* testsuite/gas/mips/mxu.s: Add test cases.
	* testsuite/gas/mips/mxu.s: Update reference output.
---
 gas/testsuite/gas/mips/mxu.d | 141 +++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/mips/mxu.s |  73 ++++++++++++++++--
 opcodes/mips-opc.c           |  12 +--
 3 files changed, 212 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/gas/testsuite/gas/mips/mxu.d b/gas/testsuite/gas/mips/mxu.d
index 507bd9b6b3a..e21494a7f96 100644
--- a/gas/testsuite/gas/mips/mxu.d
+++ b/gas/testsuite/gas/mips/mxu.d
@@ -46,6 +46,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7350c84a 	d16mac	xr1,xr2,xr3,xr4,SS,LW
 [0-9a-f]+ <[^>]*> 7390c84a 	d16mac	xr1,xr2,xr3,xr4,SS,HW
 [0-9a-f]+ <[^>]*> 73d0c84a 	d16mac	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84a 	d16mac	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84a 	d16mac	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84a 	d16mac	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84a 	d16mac	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84a 	d16mac	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84a 	d16mac	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84a 	d16mac	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84a 	d16mac	xr1,xr2,xr3,xr4,SS,XW
 [0-9a-f]+ <[^>]*> 7010c84b 	d16macf	xr1,xr2,xr3,xr4,AA,WW
 [0-9a-f]+ <[^>]*> 7050c84b 	d16macf	xr1,xr2,xr3,xr4,AA,LW
 [0-9a-f]+ <[^>]*> 7090c84b 	d16macf	xr1,xr2,xr3,xr4,AA,HW
@@ -78,6 +86,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7350c84b 	d16macf	xr1,xr2,xr3,xr4,SS,LW
 [0-9a-f]+ <[^>]*> 7390c84b 	d16macf	xr1,xr2,xr3,xr4,SS,HW
 [0-9a-f]+ <[^>]*> 73d0c84b 	d16macf	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84b 	d16macf	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84b 	d16macf	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84b 	d16macf	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84b 	d16macf	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84b 	d16macf	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84b 	d16macf	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84b 	d16macf	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84b 	d16macf	xr1,xr2,xr3,xr4,SS,XW
 [0-9a-f]+ <[^>]*> 7010c84c 	d16madl	xr1,xr2,xr3,xr4,AA,WW
 [0-9a-f]+ <[^>]*> 7050c84c 	d16madl	xr1,xr2,xr3,xr4,AA,LW
 [0-9a-f]+ <[^>]*> 7090c84c 	d16madl	xr1,xr2,xr3,xr4,AA,HW
@@ -110,6 +126,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7350c84c 	d16madl	xr1,xr2,xr3,xr4,SS,LW
 [0-9a-f]+ <[^>]*> 7390c84c 	d16madl	xr1,xr2,xr3,xr4,SS,HW
 [0-9a-f]+ <[^>]*> 73d0c84c 	d16madl	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84c 	d16madl	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84c 	d16madl	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84c 	d16madl	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84c 	d16madl	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84c 	d16madl	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84c 	d16madl	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84c 	d16madl	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84c 	d16madl	xr1,xr2,xr3,xr4,SS,XW
 [0-9a-f]+ <[^>]*> 7010c84e 	q16add	xr1,xr2,xr3,xr4,AA,WW
 [0-9a-f]+ <[^>]*> 7050c84e 	q16add	xr1,xr2,xr3,xr4,AA,LW
 [0-9a-f]+ <[^>]*> 7090c84e 	q16add	xr1,xr2,xr3,xr4,AA,HW
@@ -142,6 +166,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7350c84e 	q16add	xr1,xr2,xr3,xr4,SS,LW
 [0-9a-f]+ <[^>]*> 7390c84e 	q16add	xr1,xr2,xr3,xr4,SS,HW
 [0-9a-f]+ <[^>]*> 73d0c84e 	q16add	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84e 	q16add	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84e 	q16add	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84e 	q16add	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84e 	q16add	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84e 	q16add	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84e 	q16add	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84e 	q16add	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84e 	q16add	xr1,xr2,xr3,xr4,SS,XW
 [0-9a-f]+ <[^>]*> 7010c84f 	d16mace	xr1,xr2,xr3,xr4,AA,WW
 [0-9a-f]+ <[^>]*> 7050c84f 	d16mace	xr1,xr2,xr3,xr4,AA,LW
 [0-9a-f]+ <[^>]*> 7090c84f 	d16mace	xr1,xr2,xr3,xr4,AA,HW
@@ -174,6 +206,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7350c84f 	d16mace	xr1,xr2,xr3,xr4,SS,LW
 [0-9a-f]+ <[^>]*> 7390c84f 	d16mace	xr1,xr2,xr3,xr4,SS,HW
 [0-9a-f]+ <[^>]*> 73d0c84f 	d16mace	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84f 	d16mace	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84f 	d16mace	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84f 	d16mace	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84f 	d16mace	xr1,xr2,xr3,xr4,SS,XW
+[0-9a-f]+ <[^>]*> 7010c84f 	d16mace	xr1,xr2,xr3,xr4,AA,WW
+[0-9a-f]+ <[^>]*> 7150c84f 	d16mace	xr1,xr2,xr3,xr4,AS,LW
+[0-9a-f]+ <[^>]*> 7290c84f 	d16mace	xr1,xr2,xr3,xr4,SA,HW
+[0-9a-f]+ <[^>]*> 73d0c84f 	d16mace	xr1,xr2,xr3,xr4,SS,XW
 [0-9a-f]+ <[^>]*> 7010c848 	d16mul	xr1,xr2,xr3,xr4,WW
 [0-9a-f]+ <[^>]*> 7050c848 	d16mul	xr1,xr2,xr3,xr4,LW
 [0-9a-f]+ <[^>]*> 7090c848 	d16mul	xr1,xr2,xr3,xr4,HW
@@ -214,6 +254,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7150c84d 	s16mad	xr1,xr2,xr3,xr4,S,LW
 [0-9a-f]+ <[^>]*> 7190c84d 	s16mad	xr1,xr2,xr3,xr4,S,HW
 [0-9a-f]+ <[^>]*> 71d0c84d 	s16mad	xr1,xr2,xr3,xr4,S,XW
+[0-9a-f]+ <[^>]*> 7010c84d 	s16mad	xr1,xr2,xr3,xr4,A,WW
+[0-9a-f]+ <[^>]*> 7050c84d 	s16mad	xr1,xr2,xr3,xr4,A,LW
+[0-9a-f]+ <[^>]*> 7190c84d 	s16mad	xr1,xr2,xr3,xr4,S,HW
+[0-9a-f]+ <[^>]*> 71d0c84d 	s16mad	xr1,xr2,xr3,xr4,S,XW
+[0-9a-f]+ <[^>]*> 7010c84d 	s16mad	xr1,xr2,xr3,xr4,A,WW
+[0-9a-f]+ <[^>]*> 7050c84d 	s16mad	xr1,xr2,xr3,xr4,A,LW
+[0-9a-f]+ <[^>]*> 7190c84d 	s16mad	xr1,xr2,xr3,xr4,S,HW
+[0-9a-f]+ <[^>]*> 71d0c84d 	s16mad	xr1,xr2,xr3,xr4,S,XW
 [0-9a-f]+ <[^>]*> 7010c878 	q8mul	xr1,xr2,xr3,xr4
 [0-9a-f]+ <[^>]*> 7090c878 	q8mulsu	xr1,xr2,xr3,xr4
 [0-9a-f]+ <[^>]*> 7000c879 	q8movz	xr1,xr2,xr3
@@ -226,15 +274,31 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7210c87a 	q8mac	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c87a 	q8mac	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c87a 	q8mac	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c87a 	q8mac	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c87a 	q8mac	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c87a 	q8mac	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c87a 	q8mac	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7090c87a 	q8macsu	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7290c87a 	q8macsu	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7190c87a 	q8macsu	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7390c87a 	q8macsu	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c87a 	q8macsu	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7190c87a 	q8macsu	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7290c87a 	q8macsu	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7390c87a 	q8macsu	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7010c87b 	q16scop	xr1,xr2,xr3,xr4
 [0-9a-f]+ <[^>]*> 7010c87c 	q8madl	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7210c87c 	q8madl	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c87c 	q8madl	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c87c 	q8madl	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c87c 	q8madl	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c87c 	q8madl	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c87c 	q8madl	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c87c 	q8madl	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn0
+[0-9a-f]+ <[^>]*> 7110c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn1
+[0-9a-f]+ <[^>]*> 7210c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn2
+[0-9a-f]+ <[^>]*> 7310c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn3
 [0-9a-f]+ <[^>]*> 7010c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn0
 [0-9a-f]+ <[^>]*> 7110c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn1
 [0-9a-f]+ <[^>]*> 7210c87d 	s32sfl	xr1,xr2,xr3,xr4,ptn2
@@ -244,41 +308,77 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7210c858 	d32add	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c858 	d32add	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c858 	d32add	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c858 	d32add	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c858 	d32add	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c858 	d32add	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c858 	d32add	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7050c858 	d32addc	xr1,xr2,xr3,xr4
 [0-9a-f]+ <[^>]*> 7010c859 	d32acc	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7210c859 	d32acc	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c859 	d32acc	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c859 	d32acc	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c859 	d32acc	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c859 	d32acc	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c859 	d32acc	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c859 	d32acc	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7050c859 	d32accm	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7250c859 	d32accm	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7150c859 	d32accm	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7350c859 	d32accm	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7050c859 	d32accm	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7150c859 	d32accm	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7250c859 	d32accm	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7350c859 	d32accm	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7090c859 	d32asum	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7290c859 	d32asum	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7190c859 	d32asum	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7390c859 	d32asum	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c859 	d32asum	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7190c859 	d32asum	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7290c859 	d32asum	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7390c859 	d32asum	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7010c85b 	q16acc	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7210c85b 	q16acc	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c85b 	q16acc	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c85b 	q16acc	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c85b 	q16acc	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c85b 	q16acc	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c85b 	q16acc	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c85b 	q16acc	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7050c85b 	q16accm	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7250c85b 	q16accm	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7150c85b 	q16accm	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7350c85b 	q16accm	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7050c85b 	q16accm	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7150c85b 	q16accm	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7250c85b 	q16accm	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7350c85b 	q16accm	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7090c85b 	d16asum	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7290c85b 	d16asum	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7190c85b 	d16asum	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7390c85b 	d16asum	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7090c85b 	d16asum	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7190c85b 	d16asum	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7290c85b 	d16asum	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7390c85b 	d16asum	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7010c85c 	q8adde	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7210c85c 	q8adde	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c85c 	q8adde	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c85c 	q8adde	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c85c 	q8adde	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c85c 	q8adde	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c85c 	q8adde	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c85c 	q8adde	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7040c85c 	d8sum	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7080c85c 	d8sumc	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7010c85d 	q8acce	xr1,xr2,xr3,xr4,AA
 [0-9a-f]+ <[^>]*> 7210c85d 	q8acce	xr1,xr2,xr3,xr4,SA
 [0-9a-f]+ <[^>]*> 7110c85d 	q8acce	xr1,xr2,xr3,xr4,AS
 [0-9a-f]+ <[^>]*> 7310c85d 	q8acce	xr1,xr2,xr3,xr4,SS
+[0-9a-f]+ <[^>]*> 7010c85d 	q8acce	xr1,xr2,xr3,xr4,AA
+[0-9a-f]+ <[^>]*> 7110c85d 	q8acce	xr1,xr2,xr3,xr4,AS
+[0-9a-f]+ <[^>]*> 7210c85d 	q8acce	xr1,xr2,xr3,xr4,SA
+[0-9a-f]+ <[^>]*> 7310c85d 	q8acce	xr1,xr2,xr3,xr4,SS
 [0-9a-f]+ <[^>]*> 7000c847 	s32cps	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7008c847 	d16cps	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7010c847 	q8abd	xr1,xr2,xr3
@@ -293,6 +393,10 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 711cc846 	q8add	xr1,xr2,xr3,AS
 [0-9a-f]+ <[^>]*> 721cc846 	q8add	xr1,xr2,xr3,SA
 [0-9a-f]+ <[^>]*> 731cc846 	q8add	xr1,xr2,xr3,SS
+[0-9a-f]+ <[^>]*> 701cc846 	q8add	xr1,xr2,xr3,AA
+[0-9a-f]+ <[^>]*> 711cc846 	q8add	xr1,xr2,xr3,AS
+[0-9a-f]+ <[^>]*> 721cc846 	q8add	xr1,xr2,xr3,SA
+[0-9a-f]+ <[^>]*> 731cc846 	q8add	xr1,xr2,xr3,SS
 [0-9a-f]+ <[^>]*> 7000c843 	s32max	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7004c843 	s32min	xr1,xr2,xr3
 [0-9a-f]+ <[^>]*> 7008c843 	d16max	xr1,xr2,xr3
@@ -329,6 +433,11 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 7108c867 	s32alni	xr1,xr2,xr3,ptn2
 [0-9a-f]+ <[^>]*> 7188c867 	s32alni	xr1,xr2,xr3,ptn3
 [0-9a-f]+ <[^>]*> 7208c867 	s32alni	xr1,xr2,xr3,ptn4
+[0-9a-f]+ <[^>]*> 7008c867 	s32alni	xr1,xr2,xr3,ptn0
+[0-9a-f]+ <[^>]*> 7088c867 	s32alni	xr1,xr2,xr3,ptn1
+[0-9a-f]+ <[^>]*> 7108c867 	s32alni	xr1,xr2,xr3,ptn2
+[0-9a-f]+ <[^>]*> 7188c867 	s32alni	xr1,xr2,xr3,ptn3
+[0-9a-f]+ <[^>]*> 7208c867 	s32alni	xr1,xr2,xr3,ptn4
 [0-9a-f]+ <[^>]*> 700dfc67 	s32lui	xr1,127,ptn0
 [0-9a-f]+ <[^>]*> 708dfc67 	s32lui	xr1,127,ptn1
 [0-9a-f]+ <[^>]*> 710dfc67 	s32lui	xr1,127,ptn2
@@ -378,6 +487,10 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 704c006a 	s16ldd	xr1,v0,-512,ptn1
 [0-9a-f]+ <[^>]*> 7054006a 	s16ldd	xr1,v0,-512,ptn2
 [0-9a-f]+ <[^>]*> 705c006a 	s16ldd	xr1,v0,-512,ptn3
+[0-9a-f]+ <[^>]*> 7043fc6a 	s16ldd	xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6a 	s16ldd	xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7054006a 	s16ldd	xr1,v0,-512,ptn2
+[0-9a-f]+ <[^>]*> 705c006a 	s16ldd	xr1,v0,-512,ptn3
 [0-9a-f]+ <[^>]*> 7043fc6c 	s16ldi	xr1,v0,510,ptn0
 [0-9a-f]+ <[^>]*> 704bfc6c 	s16ldi	xr1,v0,510,ptn1
 [0-9a-f]+ <[^>]*> 7053fc6c 	s16ldi	xr1,v0,510,ptn2
@@ -386,6 +499,10 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 704c006c 	s16ldi	xr1,v0,-512,ptn1
 [0-9a-f]+ <[^>]*> 7054006c 	s16ldi	xr1,v0,-512,ptn2
 [0-9a-f]+ <[^>]*> 705c006c 	s16ldi	xr1,v0,-512,ptn3
+[0-9a-f]+ <[^>]*> 7043fc6c 	s16ldi	xr1,v0,510,ptn0
+[0-9a-f]+ <[^>]*> 704bfc6c 	s16ldi	xr1,v0,510,ptn1
+[0-9a-f]+ <[^>]*> 7054006c 	s16ldi	xr1,v0,-512,ptn2
+[0-9a-f]+ <[^>]*> 705c006c 	s16ldi	xr1,v0,-512,ptn3
 [0-9a-f]+ <[^>]*> 7004006e 	s32m2i	xr1,a0
 [0-9a-f]+ <[^>]*> 7004006f 	s32i2m	xr1,a0
 [0-9a-f]+ <[^>]*> 70028052 	s32lddv	xr1,zero,v0,2
@@ -428,6 +545,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 70560062 	s8ldd	xr1,v0,-128,ptn5
 [0-9a-f]+ <[^>]*> 705a0062 	s8ldd	xr1,v0,-128,ptn6
 [0-9a-f]+ <[^>]*> 705e0062 	s8ldd	xr1,v0,-128,ptn7
+[0-9a-f]+ <[^>]*> 7041fc62 	s8ldd	xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc62 	s8ldd	xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc62 	s8ldd	xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc62 	s8ldd	xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 70520062 	s8ldd	xr1,v0,-128,ptn4
+[0-9a-f]+ <[^>]*> 70560062 	s8ldd	xr1,v0,-128,ptn5
+[0-9a-f]+ <[^>]*> 705a0062 	s8ldd	xr1,v0,-128,ptn6
+[0-9a-f]+ <[^>]*> 705e0062 	s8ldd	xr1,v0,-128,ptn7
 [0-9a-f]+ <[^>]*> 7041fc64 	s8ldi	xr1,v0,127,ptn0
 [0-9a-f]+ <[^>]*> 7045fc64 	s8ldi	xr1,v0,127,ptn1
 [0-9a-f]+ <[^>]*> 7049fc64 	s8ldi	xr1,v0,127,ptn2
@@ -444,6 +569,14 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 70560064 	s8ldi	xr1,v0,-128,ptn5
 [0-9a-f]+ <[^>]*> 705a0064 	s8ldi	xr1,v0,-128,ptn6
 [0-9a-f]+ <[^>]*> 705e0064 	s8ldi	xr1,v0,-128,ptn7
+[0-9a-f]+ <[^>]*> 7041fc64 	s8ldi	xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc64 	s8ldi	xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 7049fc64 	s8ldi	xr1,v0,127,ptn2
+[0-9a-f]+ <[^>]*> 704dfc64 	s8ldi	xr1,v0,127,ptn3
+[0-9a-f]+ <[^>]*> 70520064 	s8ldi	xr1,v0,-128,ptn4
+[0-9a-f]+ <[^>]*> 70560064 	s8ldi	xr1,v0,-128,ptn5
+[0-9a-f]+ <[^>]*> 705a0064 	s8ldi	xr1,v0,-128,ptn6
+[0-9a-f]+ <[^>]*> 705e0064 	s8ldi	xr1,v0,-128,ptn7
 [0-9a-f]+ <[^>]*> 7041fc63 	s8std	xr1,v0,127,ptn0
 [0-9a-f]+ <[^>]*> 7045fc63 	s8std	xr1,v0,127,ptn1
 [0-9a-f]+ <[^>]*> 7049fc63 	s8std	xr1,v0,127,ptn2
@@ -452,6 +585,10 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 70460063 	s8std	xr1,v0,-128,ptn1
 [0-9a-f]+ <[^>]*> 704a0063 	s8std	xr1,v0,-128,ptn2
 [0-9a-f]+ <[^>]*> 704e0063 	s8std	xr1,v0,-128,ptn3
+[0-9a-f]+ <[^>]*> 7041fc63 	s8std	xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc63 	s8std	xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 704a0063 	s8std	xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0063 	s8std	xr1,v0,-128,ptn3
 [0-9a-f]+ <[^>]*> 7041fc65 	s8sdi	xr1,v0,127,ptn0
 [0-9a-f]+ <[^>]*> 7045fc65 	s8sdi	xr1,v0,127,ptn1
 [0-9a-f]+ <[^>]*> 7049fc65 	s8sdi	xr1,v0,127,ptn2
@@ -459,5 +596,9 @@  Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 70420065 	s8sdi	xr1,v0,-128,ptn0
 [0-9a-f]+ <[^>]*> 70460065 	s8sdi	xr1,v0,-128,ptn1
 [0-9a-f]+ <[^>]*> 704a0065 	s8sdi	xr1,v0,-128,ptn2
+[0-9a-f]+ <[^>]*> 704e0065 	s8sdi	xr1,v0,-128,ptn3
+[0-9a-f]+ <[^>]*> 7041fc65 	s8sdi	xr1,v0,127,ptn0
+[0-9a-f]+ <[^>]*> 7045fc65 	s8sdi	xr1,v0,127,ptn1
+[0-9a-f]+ <[^>]*> 704a0065 	s8sdi	xr1,v0,-128,ptn2
 [0-9a-f]+ <[^>]*> 704e0065 	s8sdi	xr1,v0,-128,ptn3
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/mxu.s b/gas/testsuite/gas/mips/mxu.s
index f9643d0624c..26b70f41217 100644
--- a/gas/testsuite/gas/mips/mxu.s
+++ b/gas/testsuite/gas/mips/mxu.s
@@ -44,6 +44,16 @@  test_mxu:
 	\insn	xr1, xr2, xr3, xr4,SS,1
 	\insn	xr1, xr2, xr3, xr4,SS,2
 	\insn	xr1, xr2, xr3, xr4,SS,3
+
+	\insn	xr1, xr2, xr3, xr4, 0, WW
+	\insn	xr1, xr2, xr3, xr4, 1, LW
+	\insn	xr1, xr2, xr3, xr4, 2, HW
+	\insn	xr1, xr2, xr3, xr4, 3, XW
+
+	\insn	xr1, xr2, xr3, xr4, 0, 0
+	\insn	xr1, xr2, xr3, xr4, 1, 1
+	\insn	xr1, xr2, xr3, xr4, 2, 2
+	\insn	xr1, xr2, xr3, xr4, 3, 3
 .endm
 
 .macro test2	insn
@@ -51,6 +61,11 @@  test_mxu:
 	\insn	xr1, xr2, xr3, xr4, SA
 	\insn	xr1, xr2, xr3, xr4, AS
 	\insn	xr1, xr2, xr3, xr4, SS
+
+	\insn	xr1, xr2, xr3, xr4, 0
+	\insn	xr1, xr2, xr3, xr4, 1
+	\insn	xr1, xr2, xr3, xr4, 2
+	\insn	xr1, xr2, xr3, xr4, 3
 .endm
 
 .macro test3 insn
@@ -71,6 +86,11 @@  test_mxu:
 	\insn xr1, $2,-512, ptn1
 	\insn xr1, $2,-512, ptn2
 	\insn xr1, $2,-512, ptn3
+
+	\insn xr1, $2, 510, 0
+	\insn xr1, $2, 510, 1
+	\insn xr1, $2, -512, 2
+	\insn xr1, $2, -512, 3
 .endm
 
 .macro test5 insn
@@ -91,6 +111,15 @@  test_mxu:
 	\insn xr1, $2,-128, ptn5
 	\insn xr1, $2,-128, ptn6
 	\insn xr1, $2,-128, ptn7
+
+	\insn xr1, $2, 127, 0
+	\insn xr1, $2, 127, 1
+	\insn xr1, $2, 127, 2
+	\insn xr1, $2, 127, 3
+	\insn xr1, $2, -128, 4
+	\insn xr1, $2, -128, 5
+	\insn xr1, $2, -128, 6
+	\insn xr1, $2, -128, 7
 .endm
 
 .macro test6 insn
@@ -103,6 +132,11 @@  test_mxu:
 	\insn xr1, $2,-128, ptn1
 	\insn xr1, $2,-128, ptn2
 	\insn xr1, $2,-128, ptn3
+
+	\insn xr1, $2, 127, 0
+	\insn xr1, $2, 127, 1
+	\insn xr1, $2, -128, 2
+	\insn xr1, $2, -128, 3
 .endm
 	mfc1	$2, $2
 	mfc1	$2, $f1
@@ -168,6 +202,16 @@  test_mxu:
 	s16mad	xr1, xr2, xr3, xr4,S,2
 	s16mad	xr1, xr2, xr3, xr4,S,3
 
+	s16mad	xr1, xr2, xr3, xr4,0,0
+	s16mad	xr1, xr2, xr3, xr4,0,1
+	s16mad	xr1, xr2, xr3, xr4,1,2
+	s16mad	xr1, xr2, xr3, xr4,1,3
+
+	s16mad	xr1, xr2, xr3, xr4,0,WW
+	s16mad	xr1, xr2, xr3, xr4,0,LW
+	s16mad	xr1, xr2, xr3, xr4,1,HW
+	s16mad	xr1, xr2, xr3, xr4,1,XW
+
 	q8mul	xr1, xr2, xr3, xr4
 	q8mulsu	xr1, xr2, xr3, xr4
 	q8movz	xr1, xr2, xr3
@@ -188,6 +232,10 @@  test_mxu:
 	s32sfl	xr1, xr2, xr3, xr4, ptn1
 	s32sfl	xr1, xr2, xr3, xr4, ptn2
 	s32sfl	xr1, xr2, xr3, xr4, ptn3
+	s32sfl	xr1, xr2, xr3, xr4, 0
+	s32sfl	xr1, xr2, xr3, xr4, 1
+	s32sfl	xr1, xr2, xr3, xr4, 2
+	s32sfl	xr1, xr2, xr3, xr4, 3
 
 	q8sad	xr1, xr2, xr3, xr4
 
@@ -222,6 +270,10 @@  test_mxu:
 	q8add	xr1, xr2, xr3,AS
 	q8add	xr1, xr2, xr3,SA
 	q8add	xr1, xr2, xr3,SS
+	q8add	xr1, xr2, xr3, 0
+	q8add	xr1, xr2, xr3, 1
+	q8add	xr1, xr2, xr3, 2
+	q8add	xr1, xr2, xr3, 3
 
 	s32max	xr1, xr2, xr3
 	s32min	xr1, xr2, xr3
@@ -263,6 +315,11 @@  test_mxu:
 	s32alni	xr1, xr2, xr3, ptn2
 	s32alni	xr1, xr2, xr3, ptn3
 	s32alni	xr1, xr2, xr3, ptn4
+	s32alni	xr1, xr2, xr3, 0
+	s32alni	xr1, xr2, xr3, 1
+	s32alni	xr1, xr2, xr3, 2
+	s32alni	xr1, xr2, xr3, 3
+	s32alni	xr1, xr2, xr3, 4
 	s32lui xr1, 127, ptn0
 	s32lui xr1, 127, ptn1
 	s32lui xr1, 127, ptn2
@@ -279,14 +336,14 @@  test_mxu:
 	s32lui xr1, -128, ptn5
 	s32lui xr1, -128, ptn6
 	s32lui xr1, -128, ptn7
-	s32lui xr1, 255, ptn0
-	s32lui xr1, 255, ptn1
-	s32lui xr1, 255, ptn2
-	s32lui xr1, 255, ptn3
-	s32lui xr1, 255, ptn4
-	s32lui xr1, 255, ptn5
-	s32lui xr1, 255, ptn6
-	s32lui xr1, 255, ptn7
+	s32lui xr1, 255, 0
+	s32lui xr1, 255, 1
+	s32lui xr1, 255, 2
+	s32lui xr1, 255, 3
+	s32lui xr1, 255, 4
+	s32lui xr1, 255, 5
+	s32lui xr1, 255, 6
+	s32lui xr1, 255, 7
 	s32nor	xr1, xr2, xr3
 	s32and	xr1, xr2, xr3
 	s32or	xr1, xr2, xr3
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6a4fd20a9da..90d7f494f6f 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -89,25 +89,25 @@  decode_mips_operand (const char *p)
 	{
 	case 'm': REG (5, 6, MXU);
 	case '=': REG (4, 6, MXU);
-	case 'a': MAPPED_STRING (2, 24, mxu_aptn, 0);
+	case 'a': MAPPED_STRING (2, 24, mxu_aptn, 1);
 	case 'b': REG (4, 10, MXU_GP);
 	case 'c': REG (4, 14, MXU_GP);
 	case 'd': REG (4, 18, MXU_GP);
 	case 'e': MAPPED_STRING (3, 18, mxu_ptn_7, 1)
-	case 'g': MAPPED_STRING (3, 18, mxu_ptn_3, 0)
+	case 'g': MAPPED_STRING (3, 18, mxu_ptn_3, 1)
 	case 'f': UINT (4, 22);
 	case 'i': INT_ADJ (10, 10, 511, 2, false);
 	case 'o': MAPPED_STRING (2, 22, mxu_optn, 1);
-	case 'P': MAPPED_STRING (2, 19, mxu_ptn_3, 0);
+	case 'P': MAPPED_STRING (2, 19, mxu_ptn_3, 1);
 	case 'p': MAPPED_STRING (2, 19, mxu_ptn_1, 0);
 	case 'r': SPECIAL (2, 14, MXU_STRIDE);
 	case 'R': SPECIAL (2, 9, MXU_STRIDE);
-	case 'A': MAPPED_STRING (1, 24, mxu_s32mad, 0);
+	case 'A': MAPPED_STRING (1, 24, mxu_s32mad, 1);
 	case 'B': SINT (8, 10);
 	case 'U': UINT (8, 10);
-	case 'E': MAPPED_STRING (2, 24, mxu_ptn_3, 0);
+	case 'E': MAPPED_STRING (2, 24, mxu_ptn_3, 1);
 	case 'I': INT_ADJ (9, 10, 255, 1, false);
-	case 'S': MAPPED_STRING (3, 23, mxu_ptn_4, 0);
+	case 'S': MAPPED_STRING (3, 23, mxu_ptn_4, 1);
 	case 'O': MAPPED_STRING (3, 23, mxu_ptn_7, 1);
 	case 'T': UINT (5, 16);
 	}