diff mbox series

[14/21] Re-arrange MXU code blocks and add comments

Message ID 20250402121759.1962001-15-jovan.dmitrovic@htecgroup.com
State New
Headers
Series Integrate MIPS-Specific Support |

Commit Message

Jovan Dmitrovic April 2, 2025, 12:18 p.m. UTC 
  From: Faraz Shahbazker <fshahbazker@wavecomp.com>

The commit reorganizes the MXU code blocks and adds comments without
changing functionality. The changes include reordering the MXU options
in the enum options and the convert_reg_type function in
gas/config/tc-mips.c, as well as adjusting the printing of MXU
registers and operations in opcodes/mips-dis.c, where the MXU cases
are now grouped together. In include/opcode/mips.h, comments were
added to explain the MXU registers and operands, while a merge
artifact was removed from gas/doc/c-mips.texi. These changes improve
the readability and maintainability of the code without altering its
functionality.

Cherry-picked a3dc766
from https://github.com/MIPS/binutils-gdb

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>

gas/
	* config/tc-mips.c (options): Re-order MXU cases.
	(convert_reg_type): Likewise.
	* gas/doc/c-mips.texi: Remove stray merge artefact.

include/
	* opcode/mips.h: Add comments.

opcodes/
	* mips-dis.c (print_reg): Re-oder MXU cases.
	(print_insn_arg): Likewise.
---
 gas/config/tc-mips.c  | 24 +++++++++++-------------
 gas/doc/c-mips.texi   |  1 -
 include/opcode/mips.h |  7 +++++++
 opcodes/mips-dis.c    | 32 +++++++++++++++++---------------
 4 files changed, 35 insertions(+), 29 deletions(-)
diff mbox series

Patch

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index bcd1961f31c..87fad61c7a4 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1495,8 +1495,6 @@  enum options
     OPTION_NO_EVA,
     OPTION_XPA,
     OPTION_NO_XPA,
-    OPTION_MXU,
-    OPTION_NO_MXU,
     OPTION_MICROMIPS,
     OPTION_NO_MICROMIPS,
     OPTION_MCU,
@@ -1578,6 +1576,8 @@  enum options
     OPTION_NO_ODD_SPREG,
     OPTION_GINV,
     OPTION_NO_GINV,
+    OPTION_MXU,
+    OPTION_NO_MXU,
     OPTION_LOONGSON_MMI,
     OPTION_NO_LOONGSON_MMI,
     OPTION_LOONGSON_CAM,
@@ -5114,12 +5114,6 @@  convert_reg_type (const struct mips_opcode *opcode,
 {
   switch (type)
     {
-    case OP_REG_MXU:
-      return RTYPE_NUM | RTYPE_MXU;
-
-    case OP_REG_MXU_GP:
-      return RTYPE_GP | RTYPE_MXU;
-
     case OP_REG_GP:
       return RTYPE_NUM | RTYPE_GP;
 
@@ -5181,6 +5175,12 @@  convert_reg_type (const struct mips_opcode *opcode,
 
     case OP_REG_MSA_CTRL:
       return RTYPE_NUM;
+
+    case OP_REG_MXU:
+      return RTYPE_NUM | RTYPE_MXU;
+
+    case OP_REG_MXU_GP:
+      return RTYPE_GP | RTYPE_MXU;
     }
   abort ();
 }
@@ -5458,7 +5458,6 @@  match_msb_operand (struct mips_arg_info *arg,
   return true;
 }
 
-
 /* OP_MAPPED_STRING matcher.  */
 
 static bfd_boolean
@@ -5516,7 +5515,6 @@  match_string_operand (struct mips_arg_info *arg,
   return true;
 }
 
-
 /* OP_REG matcher.  */
 
 static bool
@@ -6431,9 +6429,6 @@  match_operand (struct mips_arg_info *arg,
     case OP_MSB:
       return match_msb_operand (arg, operand);
 
-    case OP_MAPPED_STRING:
-      return match_string_operand (arg, operand);
-
     case OP_REG:
     case OP_OPTIONAL_REG:
       return match_reg_operand (arg, operand);
@@ -6498,6 +6493,9 @@  match_operand (struct mips_arg_info *arg,
     case OP_NON_ZERO_REG:
       return match_non_zero_reg_operand (arg, operand);
 
+    case OP_MAPPED_STRING:
+      return match_string_operand (arg, operand);
+
     case OP_MXU_STRIDE:
       return match_mxu_stride_operand (arg, operand);
     }
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 878bf02752b..650924f31a0 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -1180,7 +1180,6 @@  The directive @code{.set xpa} makes the assembler accept instructions
 from the XPA Extension from that point on in the assembly.  The 
 @code{.set noxpa} directive prevents XPA instructions from being accepted.
 
-<<<<<<< HEAD
 @cindex MIPS16e2 instruction generation override
 @kindex @code{.set mips16e2}
 @kindex @code{.set nomips16e2}
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index af07cac44f2..a87b786e437 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -184,7 +184,10 @@  enum mips_operand_type {
   /* A register operand that must not be zero.  */
   OP_NON_ZERO_REG,
 
+  /* A named MXU operation pattern represented as a string or integer.  */
   OP_MAPPED_STRING,
+
+  /* 2-bit immediate MXU stride operand.  */
   OP_MXU_STRIDE
 };
 
@@ -238,8 +241,10 @@  enum mips_reg_operand_type {
   /* MSA control registers $0-$31.  */
   OP_REG_MSA_CTRL,
 
+  /* MXU registers xr0-xr16, mxu_cr.  */
   OP_REG_MXU,
 
+  /* MXU general purpose registers xr0-xr16.  */
   OP_REG_MXU_GP
 };
 
@@ -298,12 +303,14 @@  struct mips_mapped_int_operand
   bool print_hex;
 };
 
+/*  Uses a lookup table to map MXU operation patterns to integer encodings.  */
 struct mips_mapped_string_operand
 {
   struct mips_operand root;
   const char ** strings;
   int allow_constants;
 };
+
 /* An operand that encodes the most significant bit position of a bitfield.
    Given a bitfield that spans bits [MSB, LSB], some operands of this type
    encode MSB directly while others encode MSB - LSB.  Each operand of this
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 3c8e56f47ca..3b987d4d2b6 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1208,11 +1208,6 @@  print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
 
   switch (type)
     {
-    case OP_REG_MXU:
-    case OP_REG_MXU_GP:
-      info->fprintf_func (info->stream, "%s", mips_gpr_names_xr[regno]);
-      break;
-
     case OP_REG_GP:
       infprintf (info->stream, dis_style_register, "%s",
 		 mips_gpr_names[regno]);
@@ -1292,6 +1287,10 @@  print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
 		 msa_control_names[regno]);
       break;
 
+    case OP_REG_MXU:
+    case OP_REG_MXU_GP:
+      info->fprintf_func (info->stream, "%s", mips_gpr_names_xr[regno]);
+      break;
     }
 }
 
@@ -1466,13 +1465,6 @@  print_insn_arg (struct disassemble_info *info,
 
   switch (operand->type)
     {
-    case OP_MAPPED_STRING:
-      {
-	const struct mips_mapped_string_operand *string_op;
-	string_op = (const struct mips_mapped_string_operand *) operand;
-	infprintf (is, dis_style_immediate, "%s", string_op->strings[uval]);
-      }
-      break;
     case OP_INT:
       {
 	const struct mips_int_operand *int_op;
@@ -1785,15 +1777,25 @@  print_insn_arg (struct disassemble_info *info,
       infprintf (is, dis_style_text, "]");
       break;
 
-    case OP_MXU_STRIDE:
-  	  infprintf (is, dis_style_immediate, "%d", uval);
-      break;
 
     case OP_REG_INDEX:
       infprintf (is, dis_style_text, "[");
       print_reg (info, opcode, OP_REG_GP, uval);
       infprintf (is, dis_style_text, "]");
       break;
+
+    case OP_MAPPED_STRING:
+      {
+	const struct mips_mapped_string_operand *string_op;
+	string_op = (const struct mips_mapped_string_operand *) operand;
+	infprintf (is, dis_style_immediate, "%s", string_op->strings[uval]);
+      }
+      break;
+
+    case OP_MXU_STRIDE:
+      infprintf (is, dis_style_immediate, "%d", uval);
+      break;
+   
     }
 }