diff mbox series

[v2] RISC-V: Add missing disassembler option `max`

Message ID 20250401154316.2117202-1-m.pikula@partner.samsung.com
State New
Headers
Series [v2] RISC-V: Add missing disassembler option `max` |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Marek Pikula April 1, 2025, 3:43 p.m. UTC 
  The flag already exists but it's not been exposed to user.

Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
---
 binutils/doc/binutils.texi | 8 ++++++++
 opcodes/riscv-dis.c        | 6 +++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

--
2.49.0

Comments

Nelson Chu April 15, 2025, 3:04 a.m. UTC | #1 
Okay, I think I missed this, so committed.

Thanks
Nelson

On Tue, Apr 1, 2025 at 11:43 PM Marek Pikuła <m.pikula@partner.samsung.com>
wrote:

> The flag already exists but it's not been exposed to user.
>
> Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
> ---
>  binutils/doc/binutils.texi | 8 ++++++++
>  opcodes/riscv-dis.c        | 6 +++++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
> index 5bf5d80b85b..b7803398222 100644
> --- a/binutils/doc/binutils.texi
> +++ b/binutils/doc/binutils.texi
> @@ -2704,6 +2704,14 @@ but the result again may not be as you expect.
>  For RISC-V, the following options are supported:
>
>  @table @code
> +@item max
> +Disassemble without checking architecture string. This is a best effort
> mode, so
> +for overlapping ISA extensions the first match (possibly incorrect in a
> given
> +context) will be used to decode the instruction. It's useful, if the ELF
> file
> +doesn't expose ISA string, preventing automatic ISA subset deduction, and
> the
> +default fallback ISA string (@code{rv64gc}) doesn't cover all
> instructions in
> +the binary.
> +
>  @item numeric
>  Print numeric register names, rather than ABI names (e.g., print @code{x2}
>  instead of @code{sp}).
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index f862ef28a16..277b8fd4737 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -69,7 +69,7 @@ struct riscv_private_data
>    const char (*riscv_fpr_names)[NRC];
>    /* If set, disassemble as most general instruction.  */
>    bool no_aliases;
> -  /* If set, disassemble without checking architectire string, just like
> what
> +  /* If set, disassemble without checking architecture string, just like
> what
>       we did at the beginning.  */
>    bool all_ext;
>  };
> @@ -83,6 +83,7 @@ set_default_riscv_dis_options (struct disassemble_info
> *info)
>    pd->riscv_gpr_names = riscv_gpr_names_abi;
>    pd->riscv_fpr_names = riscv_fpr_names_abi;
>    pd->no_aliases = false;
> +  pd->all_ext = false;
>  }
>
>  /* Parse RISC-V disassembler option (without arguments).  */
> @@ -1580,6 +1581,9 @@ static struct
>    riscv_option_arg_t arg;
>  } riscv_options[] =
>  {
> +  { "max",
> +    N_("Disassemble without checking architecture string."),
> +    RISCV_OPTION_ARG_NONE },
>    { "numeric",
>      N_("Print numeric register names, rather than ABI names."),
>      RISCV_OPTION_ARG_NONE },
> --
> 2.49.0
>
diff mbox series

Patch

diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 5bf5d80b85b..b7803398222 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2704,6 +2704,14 @@  but the result again may not be as you expect.
 For RISC-V, the following options are supported:

 @table @code
+@item max
+Disassemble without checking architecture string. This is a best effort mode, so
+for overlapping ISA extensions the first match (possibly incorrect in a given
+context) will be used to decode the instruction. It's useful, if the ELF file
+doesn't expose ISA string, preventing automatic ISA subset deduction, and the
+default fallback ISA string (@code{rv64gc}) doesn't cover all instructions in
+the binary.
+
 @item numeric
 Print numeric register names, rather than ABI names (e.g., print @code{x2}
 instead of @code{sp}).
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f862ef28a16..277b8fd4737 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -69,7 +69,7 @@  struct riscv_private_data
   const char (*riscv_fpr_names)[NRC];
   /* If set, disassemble as most general instruction.  */
   bool no_aliases;
-  /* If set, disassemble without checking architectire string, just like what
+  /* If set, disassemble without checking architecture string, just like what
      we did at the beginning.  */
   bool all_ext;
 };
@@ -83,6 +83,7 @@  set_default_riscv_dis_options (struct disassemble_info *info)
   pd->riscv_gpr_names = riscv_gpr_names_abi;
   pd->riscv_fpr_names = riscv_fpr_names_abi;
   pd->no_aliases = false;
+  pd->all_ext = false;
 }

 /* Parse RISC-V disassembler option (without arguments).  */
@@ -1580,6 +1581,9 @@  static struct
   riscv_option_arg_t arg;
 } riscv_options[] =
 {
+  { "max",
+    N_("Disassemble without checking architecture string."),
+    RISCV_OPTION_ARG_NONE },
   { "numeric",
     N_("Print numeric register names, rather than ABI names."),
     RISCV_OPTION_ARG_NONE },