diff mbox series

[2/4] s390: Do not omit vector index register 0 in disassembly

Message ID 20250124115209.3287742-3-jremus@linux.ibm.com
State Committed
Headers
Series [1/4] s390: Additional tests for omitted base register operands |

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Commit Message

Jens Remus Jan. 24, 2025, 11:52 a.m. UTC 
  Vector index registers are currently only used in the VRV instruction
format.  Unlike general purpose index registers an operand value of
zero (e.g. %v0, 0, or omitted) does not imply a zero value:

"For VRV format instructions, a vector element is used in the formation
of the intermediate value.  This vector element is an unsigned binary
integer value that is added to the base address and 12-bit displacement
to form a 64-bit intermediate sum.  The vector element is designated by
a vector register and an element index.  A zero V field accesses the
element in vector register zero and does not imply a zero value." [1]

Therefore do not omit vector index register 0 in disassembly, that is
disassemble D(VX,B) with VX=0 as D(VX,B) instead of D(B).  Also do not
disassemble index register 0 as "0", that is disassemble D(VX,B) with
VX=0 as D(%v0,B) instead of D(0,B).  Note that a base register 0 still
still gets disassembled as "0", that is D(VX,B) with B=0 disassembles
into D(VX,0).

[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
     https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf

opcodes/
	* s390-dis.c (s390_print_insn_with_opcode): Do not omit vector
	index register 0 in disassembly.  Disassemble it as %v0.

gas/testsuite/
	* gas/s390/zarch-base-index-0.d (vgef): Expect vector index
	register 0 in disassembly.
	* gas/s390/zarch-omitted-base-index.d (vgef): Likewise.

Suggested-by: Florian Krohm <flo2030@eich-krohm.de>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 gas/testsuite/gas/s390/zarch-base-index-0.d   | 32 +++++++++----------
 .../gas/s390/zarch-omitted-base-index.d       |  6 ++--
 opcodes/s390-dis.c                            | 13 +++-----
 3 files changed, 24 insertions(+), 27 deletions(-)
diff mbox series

Patch

diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d
index 717eaac2423b..95d12cfc1f25 100644
--- a/gas/testsuite/gas/s390/zarch-base-index-0.d
+++ b/gas/testsuite/gas/s390/zarch-base-index-0.d
@@ -81,23 +81,23 @@  Disassembly of section .text:
 .*:	f3 01 00 10 00 20 [	 ]*unpk	16\(1,0\),32\(2,0\)
 .*:	f3 01 00 00 00 00 [	 ]*unpk	0\(1,0\),0\(2,0\)
 .*:	e7 12 30 10 00 13 [	 ]*vgef	%v1,16\(%v2,%r3\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
 .*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
 .*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
 .*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
-.*:	e7 00 00 10 00 13 [	 ]*vgef	%v0,16,0
-.*:	e7 00 00 10 00 13 [	 ]*vgef	%v0,16,0
-.*:	e7 00 00 00 00 13 [	 ]*vgef	%v0,0,0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
+.*:	e7 00 00 10 00 13 [	 ]*vgef	%v0,16\(%v0,0\),0
+.*:	e7 00 00 10 00 13 [	 ]*vgef	%v0,16\(%v0,0\),0
+.*:	e7 00 00 00 00 13 [	 ]*vgef	%v0,0\(%v0,0\),0
 .*:	07 07 [	 ]*nopr	%r7
diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d
index 2795a9d095cb..c57a0ebffb27 100644
--- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d
+++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d
@@ -15,9 +15,9 @@  Disassembly of section .text:
 .*:	5a 10 00 10 [	 ]*a	%r1,16
 .*:	e7 12 30 10 00 13 [	 ]*vgef	%v1,16\(%v2,%r3\),0
 .*:	e7 12 00 10 00 13 [	 ]*vgef	%v1,16\(%v2,0\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
-.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%r3\),0
-.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16,0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
+.*:	e7 10 30 10 00 13 [	 ]*vgef	%v1,16\(%v0,%r3\),0
+.*:	e7 10 00 10 00 13 [	 ]*vgef	%v1,16\(%v0,0\),0
 .*:	d2 00 10 10 20 20 [	 ]*mvc	16\(1,%r1\),32\(%r2\)
 .*:	d2 00 10 10 00 20 [	 ]*mvc	16\(1,%r1\),32
 .*:	d2 00 00 10 20 20 [	 ]*mvc	16\(1,0\),32\(%r2\)
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index cc2012529492..98383658c47a 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -267,8 +267,9 @@  s390_print_insn_with_opcode (bfd_vma memaddr,
       union operand_value val = s390_extract_operand (buffer, operand);
       unsigned long flags = operand->flags;
 
-      /* Omit index register 0.  */
-      if ((flags & S390_OPERAND_INDEX) && val.u == 0)
+      /* Omit index register 0, except for vector index register 0.  */
+      if ((flags & S390_OPERAND_INDEX) && !(flags & S390_OPERAND_VR)
+	  && val.u == 0)
 	continue;
       /* Omit base register 0, if no or omitted index register 0.  */
       if ((flags & S390_OPERAND_BASE) && val.u == 0 && separator == '(')
@@ -310,12 +311,8 @@  s390_print_insn_with_opcode (bfd_vma memaddr,
 	{
 	  info->fprintf_styled_func (info->stream, dis_style_text,
 				     "%c", separator);
-	  if ((flags & S390_OPERAND_INDEX) && val.u == 0)
-	    info->fprintf_styled_func (info->stream, dis_style_register,
-				       "%u", val.u);
-	  else
-	    info->fprintf_styled_func (info->stream, dis_style_register,
-				       "%%v%i", val.u);
+	  info->fprintf_styled_func (info->stream, dis_style_register,
+				     "%%v%i", val.u);
 	}
       else if (flags & S390_OPERAND_AR)
 	{