diff mbox series

[2/2] RISC-V: Update testcases with new vector check.

Message ID 20250121152332.797970-2-jiawei@iscas.ac.cn
State New
Headers
Series None |

Commit Message

Jiawei Jan. 21, 2025, 3:23 p.m. UTC 
  gas/ChangeLog:

	* testsuite/gas/riscv/dw-regnums.d: Add m in march.
	* testsuite/gas/riscv/imply.d: Ditto.
	* testsuite/gas/riscv/imply.s: Ditto.
	* testsuite/gas/riscv/insn-na.d: Ditto.
	* testsuite/gas/riscv/insn.d: Ditto.
	* testsuite/gas/riscv/sifive-insns.s: Ditto.
	* testsuite/gas/riscv/vector-insns-fail-vsew.d: Ditto.
	* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Ditto.
	* testsuite/gas/riscv/vector-insns-zero-imm.d: Ditto.
	* testsuite/gas/riscv/vector-insns.d: Ditto.
	* testsuite/gas/riscv/zvfbfmin.d: Ditto.
	* testsuite/gas/riscv/zvfbfwma.d: Ditto.

---
 gas/testsuite/gas/riscv/dw-regnums.d             | 2 +-
 gas/testsuite/gas/riscv/imply.d                  | 2 +-
 gas/testsuite/gas/riscv/imply.s                  | 2 +-
 gas/testsuite/gas/riscv/insn-na.d                | 2 +-
 gas/testsuite/gas/riscv/insn.d                   | 2 +-
 gas/testsuite/gas/riscv/sifive-insns.s           | 2 +-
 gas/testsuite/gas/riscv/vector-insns-fail-vsew.d | 2 +-
 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d   | 2 +-
 gas/testsuite/gas/riscv/vector-insns-zero-imm.d  | 2 +-
 gas/testsuite/gas/riscv/vector-insns.d           | 2 +-
 gas/testsuite/gas/riscv/zvfbfmin.d               | 2 +-
 gas/testsuite/gas/riscv/zvfbfwma.d               | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

Comments

Jan Beulich Jan. 21, 2025, 3:49 p.m. UTC | #1 
On 21.01.2025 16:23, Jiawei wrote:
> gas/ChangeLog:
> 
> 	* testsuite/gas/riscv/dw-regnums.d: Add m in march.
> 	* testsuite/gas/riscv/imply.d: Ditto.
> 	* testsuite/gas/riscv/imply.s: Ditto.
> 	* testsuite/gas/riscv/insn-na.d: Ditto.
> 	* testsuite/gas/riscv/insn.d: Ditto.
> 	* testsuite/gas/riscv/sifive-insns.s: Ditto.
> 	* testsuite/gas/riscv/vector-insns-fail-vsew.d: Ditto.
> 	* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Ditto.
> 	* testsuite/gas/riscv/vector-insns-zero-imm.d: Ditto.
> 	* testsuite/gas/riscv/vector-insns.d: Ditto.
> 	* testsuite/gas/riscv/zvfbfmin.d: Ditto.
> 	* testsuite/gas/riscv/zvfbfwma.d: Ditto.

Doesn't this change need to come first, to avoid breaking the testsuite
intermediately?

Jan
Nelson Chu Jan. 22, 2025, 12:04 a.m. UTC | #2 
On Tue, Jan 21, 2025 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:

> On 21.01.2025 16:23, Jiawei wrote:
> > gas/ChangeLog:
> >
> >       * testsuite/gas/riscv/dw-regnums.d: Add m in march.
> >       * testsuite/gas/riscv/imply.d: Ditto.
> >       * testsuite/gas/riscv/imply.s: Ditto.
> >       * testsuite/gas/riscv/insn-na.d: Ditto.
> >       * testsuite/gas/riscv/insn.d: Ditto.
> >       * testsuite/gas/riscv/sifive-insns.s: Ditto.
> >       * testsuite/gas/riscv/vector-insns-fail-vsew.d: Ditto.
> >       * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Ditto.
> >       * testsuite/gas/riscv/vector-insns-zero-imm.d: Ditto.
> >       * testsuite/gas/riscv/vector-insns.d: Ditto.
> >       * testsuite/gas/riscv/zvfbfmin.d: Ditto.
> >       * testsuite/gas/riscv/zvfbfwma.d: Ditto.
>
> Doesn't this change need to come first, to avoid breaking the testsuite
> intermediately?
>

I think only the imply testcase is needed, since previous patch v implies
m, so adding m into the architecture string is redundant.  And it would be
better to update the imply testcase with the previous change.

Nelson
Jiawei Jan. 22, 2025, 12:59 a.m. UTC | #3 
在 2025/1/21 23:49, Jan Beulich 写道:
> On 21.01.2025 16:23, Jiawei wrote:
>> gas/ChangeLog:
>>
>> 	* testsuite/gas/riscv/dw-regnums.d: Add m in march.
>> 	* testsuite/gas/riscv/imply.d: Ditto.
>> 	* testsuite/gas/riscv/imply.s: Ditto.
>> 	* testsuite/gas/riscv/insn-na.d: Ditto.
>> 	* testsuite/gas/riscv/insn.d: Ditto.
>> 	* testsuite/gas/riscv/sifive-insns.s: Ditto.
>> 	* testsuite/gas/riscv/vector-insns-fail-vsew.d: Ditto.
>> 	* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Ditto.
>> 	* testsuite/gas/riscv/vector-insns-zero-imm.d: Ditto.
>> 	* testsuite/gas/riscv/vector-insns.d: Ditto.
>> 	* testsuite/gas/riscv/zvfbfmin.d: Ditto.
>> 	* testsuite/gas/riscv/zvfbfwma.d: Ditto.
> Doesn't this change need to come first, to avoid breaking the testsuite
> intermediately?
>
> Jan

Okay, will merge it in one in the next version, thanks.

Jiawei
diff mbox series

Patch

diff --git a/gas/testsuite/gas/riscv/dw-regnums.d b/gas/testsuite/gas/riscv/dw-regnums.d
index 57f8a01ea01..13f54bdc232 100644
--- a/gas/testsuite/gas/riscv/dw-regnums.d
+++ b/gas/testsuite/gas/riscv/dw-regnums.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32iv
+#as: -march=rv32imv
 #objdump: --dwarf=frames
 
 
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 78ff200e810..af45f47b70d 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -22,7 +22,7 @@  SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_m2p0_f2p2_d2p2_v1p0_zicsr2p0_zmmul1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index d696b52655a..c9e118cd428 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -25,7 +25,7 @@  imply xsfvqmaccqoq
 imply xsfvqmaccdod
 imply xsfvfnrclipxfqf
 
-imply v
+imply mv
 imply zvfh
 imply zvfhmin
 imply zvfbfwma
diff --git a/gas/testsuite/gas/riscv/insn-na.d b/gas/testsuite/gas/riscv/insn-na.d
index 55bf301656b..6c66f544c04 100644
--- a/gas/testsuite/gas/riscv/insn-na.d
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32ifcv
+#as: -march=rv32imfcv
 #source: insn.s
 #objdump: -dw -Mno-aliases
 
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 9411a6b1e19..19c52a2fe85 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32ifcv
+#as: -march=rv32imfcv
 #objdump: -dr
 
 .*:[ 	]+file format .*
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
index 5005fb3b128..34ff675f255 100644
--- a/gas/testsuite/gas/riscv/sifive-insns.s
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -1,4 +1,4 @@ 
-	.attribute arch, "rv32iv"
+	.attribute arch, "rv32imv"
 	# xsfvcp
 	.option push
 	.option arch, +xsfvcp
diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d
index e0354d18392..ca4f9d87f24 100644
--- a/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d
+++ b/gas/testsuite/gas/riscv/vector-insns-fail-vsew.d
@@ -1,3 +1,3 @@ 
-#as: -march=rv32iv
+#as: -march=rv32imv
 #source: vector-insns-fail-vsew.s
 #error_output: vector-insns-fail-vsew.l
diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
index aa633e357c9..a1312eee65e 100644
--- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32iv
+#as: -march=rv32imv
 #objdump: -dr
 
 .*:[ 	]+file format .*
diff --git a/gas/testsuite/gas/riscv/vector-insns-zero-imm.d b/gas/testsuite/gas/riscv/vector-insns-zero-imm.d
index 88a3cfdee44..bfda7a3370b 100644
--- a/gas/testsuite/gas/riscv/vector-insns-zero-imm.d
+++ b/gas/testsuite/gas/riscv/vector-insns-zero-imm.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32iv
+#as: -march=rv32imv
 #objdump: -dr
 
 .*:[ 	]+file format .*
diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
index 71764aa1f34..36cd9f8a376 100644
--- a/gas/testsuite/gas/riscv/vector-insns.d
+++ b/gas/testsuite/gas/riscv/vector-insns.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv32ifv
+#as: -march=rv32imfv
 #objdump: -dr
 
 .*:[ 	]+file format .*
diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d
index ce973812fe1..3d6b717f0c5 100644
--- a/gas/testsuite/gas/riscv/zvfbfmin.d
+++ b/gas/testsuite/gas/riscv/zvfbfmin.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv64iv_zvfbfmin
+#as: -march=rv64imv_zvfbfmin
 #objdump: -d
 
 .*:[ 	]+file format .*
diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d
index 05da1328eea..ae3917e8f4d 100644
--- a/gas/testsuite/gas/riscv/zvfbfwma.d
+++ b/gas/testsuite/gas/riscv/zvfbfwma.d
@@ -1,4 +1,4 @@ 
-#as: -march=rv64iv_zvfbfwma
+#as: -march=rv64imv_zvfbfwma
 #objdump: -d
 
 .*:[ 	]+file format .*