diff mbox series

[2/2] RISC-V: Use t2 for tail if Zicfilp enabled

Message ID 20250110101733.1532513-2-kito.cheng@sifive.com
State New
Headers
Series [1/2] RISC-V: Support extension Zicfiss and Zicfilp |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Kito Cheng Jan. 10, 2025, 10:17 a.m. UTC 
  This change is to make tail conform with software guarded jump of Zicfilp. The
reason to not choose t1 as the label register is that t1 is also as .got.plt
offset of _dl_runtime_resolve in PLT.

See more: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93
---
 gas/testsuite/gas/riscv/tail.d | 13 +++++++++++++
 gas/testsuite/gas/riscv/tail.s |  9 +++++++++
 opcodes/riscv-opc.c            |  1 +
 3 files changed, 23 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/tail.d
 create mode 100644 gas/testsuite/gas/riscv/tail.s
diff mbox series

Patch

diff --git a/gas/testsuite/gas/riscv/tail.d b/gas/testsuite/gas/riscv/tail.d
new file mode 100644
index 00000000000..6e5db231061
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tail.d
@@ -0,0 +1,13 @@ 
+#as: -march=rv32gc_zicfiss_zicfilp
+#objdump: -d
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+[0-9a-f]+:[ 	]+00000317[ 	]+auipc[ 	]+t1,0x0
+[ 	]+[0-9a-f]+:[ 	]+00030067[ 	]+jr[ 	]+t1 # 0 <foo>
+[ 	]+[0-9a-f]+:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+[0-9a-f]+:[ 	]+00038067[ 	]+jr[ 	]+t2 # 8 <foo\+0x8>
diff --git a/gas/testsuite/gas/riscv/tail.s b/gas/testsuite/gas/riscv/tail.s
new file mode 100644
index 00000000000..8058244367b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tail.s
@@ -0,0 +1,9 @@ 
+foo:
+.option push
+.option arch, rv32i
+	tail foo
+.option pop
+.option push
+.option arch, rv32i_zicfilp
+	tail foo
+.option pop
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 948125800db..d91094ab702 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -472,6 +472,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
 {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, NULL, INSN_MACRO },
+{"tail",        0, INSN_CLASS_ZICFILP, "c",   (X_T2 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"jump",        0, INSN_CLASS_I, "c,s",       0, (int) M_CALL, match_rs1_nonzero, INSN_MACRO },
 {"nop",         0, INSN_CLASS_C, "",          MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },