@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for the x86 Intel MOVRS instructions.
+
* Add support for the x86 Intel AVX10.2 instructions.
* Add support for the x86 Intel SM4 AVX10.2 instructions.
@@ -1225,6 +1225,7 @@ static const arch_entry cpu_arch[] =
VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
SUBARCH (gmi, GMI, GMI, false),
SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
+ SUBARCH (movrs, MOVRS, MOVRS, false),
};
#undef SUBARCH
@@ -224,6 +224,7 @@ accept various extension mnemonics. For example,
@code{avx10.2/512},
@code{avx10.2/256},
@code{avx10.2/128},
+@code{movrs},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1699,6 +1700,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2}
+@item @samp{.movrs}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -541,6 +541,9 @@ if [gas_32_check] then {
run_dump_test "avx10_2-512-sm4"
run_dump_test "avx10_2-512-sm4-intel"
run_list_test "avx10_2-sm4-inval"
+ run_dump_test "movrs"
+ run_dump_test "movrs-intel"
+ run_list_test "movrs-inval"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -33,6 +33,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%ebp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%ebp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%ebp\)
+ +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%ebp\)
+[a-f0-9]+: 1f pop %ds
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
@@ -20,6 +20,7 @@ _start:
prefetcht1 (%ebp)
prefetcht2 (%ebp)
prefetchw (%ebp)
+ prefetchrst2 (%ebp)
pop %ds
popf
popa
new file mode 100644
@@ -0,0 +1,15 @@
+#objdump: -dw -Mintel
+#name: i386 MOVRS insns (Intel disassembly)
+#source: movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 BYTE PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 BYTE PTR \[ecx\]
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[ecx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[edx-0x80\]
+#pass
new file mode 100644
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:5: Error: `movrs' is only supported in 64-bit mode
+.*:6: Error: `movrs' is only supported in 64-bit mode
+.*:7: Error: `movrs' is only supported in 64-bit mode
+.*:8: Error: `movrs' is only supported in 64-bit mode
+.*:9: Error: `vmovrsb' is only supported in 64-bit mode
+.*:10: Error: `vmovrsd' is only supported in 64-bit mode
+.*:11: Error: `vmovrsq' is only supported in 64-bit mode
+.*:12: Error: `vmovrsw' is only supported in 64-bit mode
new file mode 100644
@@ -0,0 +1,12 @@
+# Check Illegal 32bit MOVRS instructions
+
+ .text
+_start:
+ movrs 0x10000000(%esp, %esi, 8), %dx
+ movrs 0x10000000(%esp, %esi, 8), %edx
+ movrs 0x10000000(%esp, %esi, 8), %r12
+ movrs 0x10000000(%esp, %esi, 8), %bl
+ vmovrsb 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsd 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsq 0x10000000(%esp, %esi, 8), %zmm6{%k7}
+ vmovrsw 0x10000000(%esp, %esi, 8), %zmm6{%k7}
new file mode 100644
@@ -0,0 +1,13 @@
+#objdump: -dw
+#name: i386 MOVRS insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 18 a4 f4 00 00 00 10\s+prefetchrst2 0x10000000\(%esp,%esi,8\)
+\s*[a-f0-9]+:\s*0f 18 21\s+prefetchrst2 \(%ecx\)
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%ecx\)
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%edx\)
+#pass
new file mode 100644
@@ -0,0 +1,15 @@
+# Check 32bit MOVRS instructions
+
+ .text
+_start:
+ prefetchrst2 0x10000000(%esp, %esi, 8)
+ prefetchrst2 (%ecx)
+ prefetchrst2 127(%ecx)
+ prefetchrst2 -128(%edx)
+
+_intel:
+ .intel_syntax noprefix
+ prefetchrst2 BYTE PTR [esp+esi*8+0x10000000]
+ prefetchrst2 BYTE PTR [ecx]
+ prefetchrst2 BYTE PTR [ecx+127]
+ prefetchrst2 BYTE PTR [edx-128]
@@ -74,7 +74,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\)
+[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\)
+[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\)
- +[a-f0-9]+: 0f 18 20 nopl \(%eax\)
+ +[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\)
+[a-f0-9]+: 0f 18 28 nopl \(%eax\)
+[a-f0-9]+: 0f 18 30 nopl \(%eax\)
+[a-f0-9]+: 0f 18 38 nopl \(%eax\)
@@ -146,7 +146,7 @@ Disassembly of section .text:
+[a-f0-9]+: 66 0f 18 08 data16 prefetcht0 \(%eax\)
+[a-f0-9]+: 66 0f 18 10 data16 prefetcht1 \(%eax\)
+[a-f0-9]+: 66 0f 18 18 data16 prefetcht2 \(%eax\)
- +[a-f0-9]+: 66 0f 18 20 nopw \(%eax\)
+ +[a-f0-9]+: 66 0f 18 20 data16 prefetchrst2 \(%eax\)
+[a-f0-9]+: 66 0f 18 28 nopw \(%eax\)
+[a-f0-9]+: 66 0f 18 30 nopw \(%eax\)
+[a-f0-9]+: 66 0f 18 38 nopw \(%eax\)
@@ -218,7 +218,7 @@ Disassembly of section .text:
+[a-f0-9]+: f3 0f 18 08 repz prefetcht0 \(%eax\)
+[a-f0-9]+: f3 0f 18 10 repz prefetcht1 \(%eax\)
+[a-f0-9]+: f3 0f 18 18 repz prefetcht2 \(%eax\)
- +[a-f0-9]+: f3 0f 18 20 repz nopl \(%eax\)
+ +[a-f0-9]+: f3 0f 18 20 repz prefetchrst2 \(%eax\)
+[a-f0-9]+: f3 0f 18 28 repz nopl \(%eax\)
+[a-f0-9]+: f3 0f 18 30 repz nopl \(%eax\)
+[a-f0-9]+: f3 0f 18 38 repz nopl \(%eax\)
@@ -290,7 +290,7 @@ Disassembly of section .text:
+[a-f0-9]+: f2 0f 18 08 repnz prefetcht0 \(%eax\)
+[a-f0-9]+: f2 0f 18 10 repnz prefetcht1 \(%eax\)
+[a-f0-9]+: f2 0f 18 18 repnz prefetcht2 \(%eax\)
- +[a-f0-9]+: f2 0f 18 20 repnz nopl \(%eax\)
+ +[a-f0-9]+: f2 0f 18 20 repnz prefetchrst2 \(%eax\)
+[a-f0-9]+: f2 0f 18 28 repnz nopl \(%eax\)
+[a-f0-9]+: f2 0f 18 30 repnz nopl \(%eax\)
+[a-f0-9]+: f2 0f 18 38 repnz nopl \(%eax\)
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[eax\]
-\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[eax\]
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[eax\]
\s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[eax\]
\s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[eax\]
\s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[eax\]
@@ -21,7 +21,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\)
\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\)
\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\)
-\s*[a-f0-9]+: 0f 18 20 nopl \(%eax\)
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%eax\)
\s*[a-f0-9]+: 0f 18 28 nopl \(%eax\)
\s*[a-f0-9]+: 0f 18 30 nopl \(%eax\)
\s*[a-f0-9]+: 0f 18 38 nopl \(%eax\)
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+r31,\[r31\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],r25d
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r31
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+r16b,BYTE PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+r18w,WORD PTR \[r16\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+r31,QWORD PTR \[r16\+rax\*4\+0x123\]
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+r10d,edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+r11,r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+edx,r25d,DWORD PTR \[r31\+rax\*4\+0x123\]
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc fc 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c .d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc fc 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -118,6 +118,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -253,6 +257,10 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 4c 7d 08 f8 bc 87 23 01 00 00[ ]+movdir64b[ ]+0x123\(%r31,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 f9 8c 87 23 01 00 00[ ]+movdiri[ ]+%r25d,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 4c fc 08 f9 bc 87 23 01 00 00[ ]+movdiri[ ]+%r31,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 cc 7c 08 8a 84 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r16b
+[ ]*[a-f0-9]+:[ ]*62 ec 7d 08 8b 94 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r18w
+[ ]*[a-f0-9]+:[ ]*62 4c 7c 08 8b 8c 87 23 01 00 00[ ]+movrs[ ]+0x123\(%r31,%rax,4\),%r25d
+[ ]*[a-f0-9]+:[ ]*62 6c fc 08 8b bc 80 23 01 00 00[ ]+movrs[ ]+0x123\(%r16,%rax,4\),%r31
[ ]*[a-f0-9]+:[ ]*62 5a 6f 08 f5 d1[ ]+pdep[ ]+%r25d,%edx,%r10d
[ ]*[a-f0-9]+:[ ]*62 5a 87 08 f5 df[ ]+pdep[ ]+%r31,%r15,%r11
[ ]*[a-f0-9]+:[ ]*62 da 37 00 f5 94 87 23 01 00 00[ ]+pdep[ ]+0x123\(%r31,%rax,4\),%r25d,%edx
@@ -112,6 +112,10 @@ _start:
movdir64b 0x123(%r31,%rax,4),%r31
movdiri %r25d,0x123(%r31,%rax,4)
movdiri %r31,0x123(%r31,%rax,4)
+ movrs 0x123(%r31,%rax,4),%r16b
+ movrs 0x123(%r16,%rax,4),%r18w
+ movrs 0x123(%r31,%rax,4),%r25d
+ movrs 0x123(%r16,%rax,4),%r31
pdep %r25d,%edx,%r10d
pdep %r31,%r15,%r11
pdep 0x123(%r31,%rax,4),%r25d,%edx
@@ -249,6 +253,10 @@ _start:
movdir64b r31,[r31+rax*4+0x123]
movdiri DWORD PTR [r31+rax*4+0x123],r25d
movdiri QWORD PTR [r31+rax*4+0x123],r31
+ movrs r16b,BYTE PTR [r31+rax*4+0x123]
+ movrs r18w,WORD PTR [r16+rax*4+0x123]
+ movrs r25d,DWORD PTR [r31+rax*4+0x123]
+ movrs r31,QWORD PTR [r16+rax*4+0x123]
pdep r10d,edx,r25d
pdep r11,r15,r31
pdep edx,r25d,DWORD PTR [r31+rax*4+0x123]
@@ -35,6 +35,7 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+: 0f 18 65 00 prefetchrst2 0x0\(%rbp\)
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
@@ -22,6 +22,7 @@ _start:
prefetchw (%rbp)
prefetchit0 0x12345678(%rip)
prefetchit1 0x12345678(%rip)
+ prefetchrst2 (%rbp)
pop %fs
popf
xlatb (%rbx)
new file mode 100644
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS, AVX10.2/256 insns (Intel disassembly)
+#source: x86-64-movrs-avx10_2-256.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw xmm30\{k7\},XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw xmm30,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw xmm30,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw xmm30\{k7\}\{z\},XMMWORD PTR \[rdx-0x800\]
+#pass
new file mode 100644
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: x86_64 MOVRS, AVX10.2/256 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 25 7f 0f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7f 08 6f 31\s+vmovrsb \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7f 08 6f 71 7f\s+vmovrsb 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7f 8f 6f 72 80\s+vmovrsb -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 7e 0f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7e 08 6f 31\s+vmovrsd \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7e 08 6f 71 7f\s+vmovrsd 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 7e 8f 6f 72 80\s+vmovrsd -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 fe 0f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 fe 08 6f 31\s+vmovrsq \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 fe 08 6f 71 7f\s+vmovrsq 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 fe 8f 6f 72 80\s+vmovrsq -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 ff 0f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 ff 08 6f 31\s+vmovrsw \(%r9\),%xmm30
+\s*[a-f0-9]+:\s*62 65 ff 08 6f 71 7f\s+vmovrsw 0x7f0\(%rcx\),%xmm30
+\s*[a-f0-9]+:\s*62 65 ff 8f 6f 72 80\s+vmovrsw -0x800\(%rdx\),%xmm30\{%k7\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,41 @@
+# Check 64bit MOVRS, AVX10.2/256 instructions
+
+ .arch generic64
+ .arch .avx10.2/256
+ .arch .movrs
+_start:
+ vmovrsb 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsb (%r9), %xmm30
+ vmovrsb 2032(%rcx), %xmm30
+ vmovrsb -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsd 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsd (%r9), %xmm30
+ vmovrsd 2032(%rcx), %xmm30
+ vmovrsd -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsq 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsq (%r9), %xmm30
+ vmovrsq 2032(%rcx), %xmm30
+ vmovrsq -2048(%rdx), %xmm30{%k7}{z}
+ vmovrsw 0x10000000(%rbp, %r14, 8), %xmm30{%k7}
+ vmovrsw (%r9), %xmm30
+ vmovrsw 2032(%rcx), %xmm30
+ vmovrsw -2048(%rdx), %xmm30{%k7}{z}
+
+_intel:
+ .intel_syntax noprefix
+ vmovrsb xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsb xmm30, XMMWORD PTR [r9]
+ vmovrsb xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsb xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsd xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsd xmm30, XMMWORD PTR [r9]
+ vmovrsd xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsd xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsq xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsq xmm30, XMMWORD PTR [r9]
+ vmovrsq xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsq xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
+ vmovrsw xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsw xmm30, XMMWORD PTR [r9]
+ vmovrsw xmm30, XMMWORD PTR [rcx+2032]
+ vmovrsw xmm30{k7}{z}, XMMWORD PTR [rdx-2048]
new file mode 100644
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS, AVX10.2/512 insns (Intel disassembly)
+#source: x86-64-movrs-avx10_2-512.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw zmm30\{k7\},ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw zmm30,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw zmm30,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw zmm30\{k7\}\{z\},ZMMWORD PTR \[rdx-0x2000\]
+#pass
new file mode 100644
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: x86_64 MOVRS, AVX10.2/512 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 25 7f 4f 6f b4 f5 00 00 00 10\s+vmovrsb 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7f 48 6f 31\s+vmovrsb \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7f 48 6f 71 7f\s+vmovrsb 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7f cf 6f 72 80\s+vmovrsb -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 7e 4f 6f b4 f5 00 00 00 10\s+vmovrsd 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 7e 48 6f 31\s+vmovrsd \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7e 48 6f 71 7f\s+vmovrsd 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 7e cf 6f 72 80\s+vmovrsd -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 fe 4f 6f b4 f5 00 00 00 10\s+vmovrsq 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 fe 48 6f 31\s+vmovrsq \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 fe 48 6f 71 7f\s+vmovrsq 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 fe cf 6f 72 80\s+vmovrsq -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 25 ff 4f 6f b4 f5 00 00 00 10\s+vmovrsw 0x10000000\(%rbp,%r14,8\),%zmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 45 ff 48 6f 31\s+vmovrsw \(%r9\),%zmm30
+\s*[a-f0-9]+:\s*62 65 ff 48 6f 71 7f\s+vmovrsw 0x1fc0\(%rcx\),%zmm30
+\s*[a-f0-9]+:\s*62 65 ff cf 6f 72 80\s+vmovrsw -0x2000\(%rdx\),%zmm30\{%k7\}\{z\}
+#pass
new file mode 100644
@@ -0,0 +1,41 @@
+# Check 64bit MOVRS, AVX10.2/512 instructions
+
+ .arch generic64
+ .arch .avx10.2/512
+ .arch .movrs
+_start:
+ vmovrsb 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsb (%r9), %zmm30
+ vmovrsb 8128(%rcx), %zmm30
+ vmovrsb -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsd 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsd (%r9), %zmm30
+ vmovrsd 8128(%rcx), %zmm30
+ vmovrsd -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsq 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsq (%r9), %zmm30
+ vmovrsq 8128(%rcx), %zmm30
+ vmovrsq -8192(%rdx), %zmm30{%k7}{z}
+ vmovrsw 0x10000000(%rbp, %r14, 8), %zmm30{%k7}
+ vmovrsw (%r9), %zmm30
+ vmovrsw 8128(%rcx), %zmm30
+ vmovrsw -8192(%rdx), %zmm30{%k7}{z}
+
+_intel:
+ .intel_syntax noprefix
+ vmovrsb zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsb zmm30, ZMMWORD PTR [r9]
+ vmovrsb zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsb zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsd zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsd zmm30, ZMMWORD PTR [r9]
+ vmovrsd zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsd zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsq zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsq zmm30, ZMMWORD PTR [r9]
+ vmovrsq zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsq zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
+ vmovrsw zmm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000]
+ vmovrsw zmm30, ZMMWORD PTR [r9]
+ vmovrsw zmm30, ZMMWORD PTR [rcx+8128]
+ vmovrsw zmm30{k7}{z}, ZMMWORD PTR [rdx-8192]
new file mode 100644
@@ -0,0 +1,31 @@
+#objdump: -dw -Mintel
+#name: x86_64 MOVRS insns (Intel disassembly)
+#source: x86-64-movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs dx,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs dx,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs dx,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs dx,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs edx,DWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs edx,DWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs edx,DWORD PTR \[rcx\+0x1fc\]
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs edx,DWORD PTR \[rdx-0x200\]
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs r12,QWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs r12,QWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs r12,QWORD PTR \[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs r12,QWORD PTR \[rdx-0x400\]
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs bl,BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs bl,BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs bl,BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs bl,BYTE PTR \[rdx-0x80\]
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[rdx-0x80\]
+#pass
new file mode 100644
@@ -0,0 +1,31 @@
+#objdump: -dwMsuffix -Mintel
+#name: x86_64 MOVRS insns (Intel disassembly w/ suffix)
+#source: x86-64-movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrsw dx,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrsw dx,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrsw dx,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw dx,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrsl edx,DWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrsl edx,DWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrsl edx,DWORD PTR \[rcx\+0x1fc\]
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl edx,DWORD PTR \[rdx-0x200\]
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrsq r12,QWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrsq r12,QWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrsq r12,QWORD PTR \[rcx\+0x3f8\]
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq r12,QWORD PTR \[rdx-0x400\]
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrsb bl,BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrsb bl,BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrsb bl,BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb bl,BYTE PTR \[rdx-0x80\]
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 BYTE PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 BYTE PTR \[r9\]
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 BYTE PTR \[rcx\+0x7f\]
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 BYTE PTR \[rdx-0x80\]
+#pass
new file mode 100644
@@ -0,0 +1,30 @@
+#objdump: -dwMsuffix
+#name: x86_64 MOVRS insns w/ suffix
+#source: x86-64-movrs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrsw 0x10000000\(%rbp,%r14,8\),%dx
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrsw \(%r9\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrsw 0xfe\(%rcx\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrsw -0x100\(%rdx\),%dx
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrsl 0x10000000\(%rbp,%r14,8\),%edx
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrsl \(%r9\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrsl 0x1fc\(%rcx\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrsl -0x200\(%rdx\),%edx
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrsq 0x10000000\(%rbp,%r14,8\),%r12
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrsq \(%r9\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrsq 0x3f8\(%rcx\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrsq -0x400\(%rdx\),%r12
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrsb 0x10000000\(%rbp,%r14,8\),%bl
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrsb \(%r9\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrsb 0x7f\(%rcx\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrsb -0x80\(%rdx\),%bl
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 \(%r9\)
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%rcx\)
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%rdx\)
+#pass
new file mode 100644
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: x86_64 MOVRS insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*66 42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%dx
+\s*[a-f0-9]+:\s*66 41 0f 38 8b 11\s+movrs \(%r9\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 91 fe 00 00 00\s+movrs 0xfe\(%rcx\),%dx
+\s*[a-f0-9]+:\s*66 0f 38 8b 92 00 ff ff ff\s+movrs -0x100\(%rdx\),%dx
+\s*[a-f0-9]+:\s*42 0f 38 8b 94 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%edx
+\s*[a-f0-9]+:\s*41 0f 38 8b 11\s+movrs \(%r9\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 91 fc 01 00 00\s+movrs 0x1fc\(%rcx\),%edx
+\s*[a-f0-9]+:\s*0f 38 8b 92 00 fe ff ff\s+movrs -0x200\(%rdx\),%edx
+\s*[a-f0-9]+:\s*4e 0f 38 8b a4 f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%r12
+\s*[a-f0-9]+:\s*4d 0f 38 8b 21\s+movrs \(%r9\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a1 f8 03 00 00\s+movrs 0x3f8\(%rcx\),%r12
+\s*[a-f0-9]+:\s*4c 0f 38 8b a2 00 fc ff ff\s+movrs -0x400\(%rdx\),%r12
+\s*[a-f0-9]+:\s*42 0f 38 8a 9c f5 00 00 00 10\s+movrs 0x10000000\(%rbp,%r14,8\),%bl
+\s*[a-f0-9]+:\s*41 0f 38 8a 19\s+movrs \(%r9\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 59 7f\s+movrs 0x7f\(%rcx\),%bl
+\s*[a-f0-9]+:\s*0f 38 8a 5a 80\s+movrs -0x80\(%rdx\),%bl
+\s*[a-f0-9]+:\s*42 0f 18 a4 f5 00 00 00 10\s+prefetchrst2 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*41 0f 18 21\s+prefetchrst2 \(%r9\)
+\s*[a-f0-9]+:\s*0f 18 61 7f\s+prefetchrst2 0x7f\(%rcx\)
+\s*[a-f0-9]+:\s*0f 18 62 80\s+prefetchrst2 -0x80\(%rdx\)
+#pass
new file mode 100644
@@ -0,0 +1,47 @@
+# Check 64bit MOVRS instructions
+
+ .text
+_start:
+ movrs 0x10000000(%rbp, %r14, 8), %dx
+ movrs (%r9), %dx
+ movrs 254(%rcx), %dx
+ movrs -256(%rdx), %dx
+ movrs 0x10000000(%rbp, %r14, 8), %edx
+ movrs (%r9), %edx
+ movrs 508(%rcx), %edx
+ movrs -512(%rdx), %edx
+ movrs 0x10000000(%rbp, %r14, 8), %r12
+ movrs (%r9), %r12
+ movrs 1016(%rcx), %r12
+ movrs -1024(%rdx), %r12
+ movrs 0x10000000(%rbp, %r14, 8), %bl
+ movrs (%r9), %bl
+ movrs 127(%rcx), %bl
+ movrs -128(%rdx), %bl
+ prefetchrst2 0x10000000(%rbp, %r14, 8)
+ prefetchrst2 (%r9)
+ prefetchrst2 127(%rcx)
+ prefetchrst2 -128(%rdx)
+
+_intel:
+ .intel_syntax noprefix
+ movrs dx, [rbp+r14*8+0x10000000]
+ movrs dx, [r9]
+ movrs dx, [rcx+254]
+ movrs dx, [rdx-256]
+ movrs edx, [rbp+r14*8+0x10000000]
+ movrs edx, [r9]
+ movrs edx, [rcx+508]
+ movrs edx, [rdx-512]
+ movrs r12, [rbp+r14*8+0x10000000]
+ movrs r12, [r9]
+ movrs r12, [rcx+1016]
+ movrs r12, [rdx-1024]
+ movrs bl, [rbp+r14*8+0x10000000]
+ movrs bl, [r9]
+ movrs bl, [rcx+127]
+ movrs bl, [rdx-128]
+ prefetchrst2 [rbp+r14*8+0x10000000]
+ prefetchrst2 [r9]
+ prefetchrst2 [rcx+127]
+ prefetchrst2 [rdx-128]
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[rax\]
-\s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[rax\]
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 BYTE PTR \[rax\]
\s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[rax\]
\s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[rax\]
\s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[rax\]
@@ -22,7 +22,7 @@ Disassembly of section .text:
\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%rax\)
\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%rax\)
\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%rax\)
-\s*[a-f0-9]+: 0f 18 20 nopl \(%rax\)
+\s*[a-f0-9]+: 0f 18 20 prefetchrst2 \(%rax\)
\s*[a-f0-9]+: 0f 18 28 nopl \(%rax\)
\s*[a-f0-9]+: 0f 18 30 nopl \(%rax\)
\s*[a-f0-9]+: 0f 18 38 nopl \(%rax\)
@@ -535,6 +535,12 @@ run_dump_test "x86-64-amx-fp8"
run_dump_test "x86-64-amx-fp8-intel"
run_list_test "x86-64-amx-fp8-inval"
run_dump_test "x86-64-amx-fp8-bad"
+run_dump_test "x86-64-movrs"
+run_dump_test "x86-64-movrs-intel"
+run_dump_test "x86-64-movrs-avx10_2-512"
+run_dump_test "x86-64-movrs-avx10_2-512-intel"
+run_dump_test "x86-64-movrs-avx10_2-256"
+run_dump_test "x86-64-movrs-avx10_2-256-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
@@ -8,6 +8,14 @@
{ "movbeS", { Mv, Gv }, PREFIX_NP_OR_DATA },
{ "%NEmovbeS", { Ev, Gv }, PREFIX_NP_OR_DATA },
},
+ /* MOD_EVEX_MAP4_8A */
+ {
+ { "movrsB", { Gb, Mb }, NO_PREFIX },
+ },
+ /* MOD_EVEX_MAP4_8B */
+ {
+ { "movrsS", { Gv, Mv }, PREFIX_NP_OR_DATA },
+ },
/* MOD_EVEX_MAP4_F8_P_1 */
{
{ "enqcmds", { Gva, M }, 0 },
@@ -18,3 +26,7 @@
{ "enqcmd", { Gva, M }, 0 },
{ VEX_W_TABLE (EVEX_W_MAP4_F8_P3_M_1) },
},
+ /* MOD_EVEX_MAP5_6F */
+ {
+ { X86_64_TABLE (X86_64_EVEX_MAP5_6F_M_0) },
+ },
@@ -580,6 +580,13 @@
{ VEX_W_TABLE (EVEX_W_MAP5_6E_P_1) },
{ "vmovwY", { XMScalar, Edw }, 0 },
},
+ /* PREFIX_EVEX_MAP5_6F_M_0_X86_64 */
+ {
+ { Bad_Opcode },
+ { "vmovrs%DQ", { XM, EXEvexXNoBcst }, 0 },
+ { Bad_Opcode },
+ { "vmovrs%BW", { XM, EXEvexXNoBcst }, 0 },
+ },
/* PREFIX_EVEX_MAP5_74 */
{
{ "vcvtbiasp%XH2bf8s", { XMxmmq, Vex, EXxh }, 0 },
new file mode 100644
@@ -0,0 +1,5 @@
+ /* X86_64_EVEX_MAP5_6F_M_0 */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_6F_M_0_X86_64) },
+ },
@@ -1030,8 +1030,8 @@ static const struct dis386 evex_table[][256] = {
/* 88 */
{ "%NFpopcntS", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_EVEX_MAP4_8A) },
+ { MOD_TABLE (MOD_EVEX_MAP4_8B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1290,7 +1290,7 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6D) },
{ EVEX_LEN_TABLE (EVEX_LEN_MAP5_6E) },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_EVEX_MAP5_6F) },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -942,6 +942,7 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
+ MOD_0F18_REG_4,
MOD_0F18_REG_6,
MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
@@ -959,6 +960,8 @@ enum
MOD_0FAE_REG_7,
MOD_0FC7_REG_6,
MOD_0FC7_REG_7,
+ MOD_0F388A,
+ MOD_0F388B,
MOD_0F38DC_PREFIX_1,
MOD_0F38F8,
@@ -968,8 +971,12 @@ enum
MOD_EVEX_MAP4_60,
MOD_EVEX_MAP4_61,
+ MOD_EVEX_MAP4_8A,
+ MOD_EVEX_MAP4_8B,
MOD_EVEX_MAP4_F8_P_1,
MOD_EVEX_MAP4_F8_P_3,
+
+ MOD_EVEX_MAP5_6F,
};
enum
@@ -1258,6 +1265,7 @@ enum
PREFIX_EVEX_MAP5_6C,
PREFIX_EVEX_MAP5_6D,
PREFIX_EVEX_MAP5_6E_L_0,
+ PREFIX_EVEX_MAP5_6F_M_0_X86_64,
PREFIX_EVEX_MAP5_74,
PREFIX_EVEX_MAP5_78,
PREFIX_EVEX_MAP5_79,
@@ -1346,6 +1354,8 @@ enum
X86_64_0F18_REG_7_MOD_0,
X86_64_0F24,
X86_64_0F26,
+ X86_64_0F388A_M_0,
+ X86_64_0F388B_M_0,
X86_64_0F38F8_M_1,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -1364,6 +1374,8 @@ enum
X86_64_VEX_MAP5_FD,
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
+
+ X86_64_EVEX_MAP5_6F_M_0,
};
enum
@@ -2865,7 +2877,7 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_1) },
{ MOD_TABLE (MOD_0F18_REG_2) },
{ MOD_TABLE (MOD_0F18_REG_3) },
- { "nopQ", { Ev }, 0 },
+ { MOD_TABLE (MOD_0F18_REG_4) },
{ "nopQ", { Ev }, 0 },
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
@@ -4615,6 +4627,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "movZ", { Td, Em }, 0 },
},
+ {
+ /* X86_64_0F388A_M_0 */
+ { Bad_Opcode },
+ { "movrsB", { Gb, Mb }, PREFIX_OPCODE },
+ },
+
+ {
+ /* X86_64_0F388B_M_0 */
+ { Bad_Opcode },
+ { "movrsS", { Gv, Mv }, PREFIX_OPCODE },
+ },
+
{
/* X86_64_0F38F8_M_1 */
{ Bad_Opcode },
@@ -4710,6 +4734,8 @@ static const struct dis386 x86_64_table[][2] = {
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
},
+
+#include "i386-dis-evex-x86-64.h"
};
static const struct dis386 three_byte_table[][256] = {
@@ -4872,8 +4898,8 @@ static const struct dis386 three_byte_table[][256] = {
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F388A) },
+ { MOD_TABLE (MOD_0F388B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -8392,6 +8418,11 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F18_REG_4 */
+ { "prefetchrst2", { Mb }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
{
/* MOD_0F18_REG_6 */
{ X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
@@ -8477,6 +8508,14 @@ static const struct dis386 mod_table[][2] = {
{ "vmptrst", { Mq }, 0 },
{ PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
+ {
+ /* MOD_0F388A */
+ { X86_64_TABLE (X86_64_0F388A_M_0) },
+ },
+ {
+ /* MOD_0F388B */
+ { X86_64_TABLE (X86_64_0F388B_M_0) },
+ },
{
/* MOD_0F38DC_PREFIX_1 */
{ "aesenc128kl", { XM, M }, 0 },
@@ -417,6 +417,7 @@ static bitfield cpu_flags[] =
BITFIELD (MSR_IMM),
BITFIELD (APX_F),
BITFIELD (AVX10_2),
+ BITFIELD (MOVRS),
BITFIELD (MWAITX),
BITFIELD (CLZERO),
BITFIELD (OSPKE),
@@ -229,6 +229,8 @@ enum i386_cpu
CpuUSER_MSR,
/* Intel MSR_IMM Instructions support required. */
CpuMSR_IMM,
+ /* Intel MOVRS Instructions support required. */
+ CpuMOVRS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -493,6 +495,7 @@ typedef union i386_cpu_flags
unsigned int cpulkgs:1;
unsigned int cpuuser_msr:1;
unsigned int cpumsr_imm:1;
+ unsigned int cpumovrs:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -3554,3 +3554,15 @@ vcomxs<sdh>, 0x<sdh:spfx>2f, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8M
vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
// AVX10.2 instructions end.
+
+// MOVRS instructions.
+
+prefetchrst2, 0xf18/4, MOVRS, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }
+
+movrs, 0x8a, MOVRS&x64, D|W|Modrm|Space0F38|CheckOperandSize|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+movrs, 0x8a, MOVRS&APX_F, D|W|Modrm|EVexMap4|EVex128|CheckOperandSize|No_sSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+
+// MOVRS instructions end.