@@ -1184,6 +1184,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false),
SUBARCH (amx_transpose, AMX_TRANSPOSE, ANY_AMX_TRANSPOSE, false),
SUBARCH (amx_tf32, AMX_TF32, ANY_AMX_TF32, false),
+ SUBARCH (amx_fp8, AMX_FP8, ANY_AMX_FP8, false),
SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
SUBARCH (movdiri, MOVDIRI, MOVDIRI, false),
SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false),
@@ -4227,6 +4228,7 @@ build_vex_prefix (const insn_template *t)
case SPACE_0F:
case SPACE_0F38:
case SPACE_0F3A:
+ case SPACE_MAP5:
case SPACE_MAP7:
i.vex.bytes[0] = 0xc4;
break;
@@ -230,6 +230,7 @@ accept various extension mnemonics. For example,
@code{amx_complex},
@code{amx_transpose},
@code{amx_tf32},
+@code{amx_fp8}
@code{amx_tile},
@code{vmx},
@code{vmfunc},
@@ -1703,7 +1704,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
@item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_tf32}
-@item @samp{.amx_tile}
+@item @samp{.amx_fp8} @tab @samp{.amx_tile}
@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
new file mode 100644
@@ -0,0 +1,22 @@
+#objdump: -drw
+#name: x86_64 AMX_FP8 bad insns
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+\s*[a-f0-9]+:\s*c4 e5 70 fd d1\s+tdpbf8ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
+\s*[a-f0-9]+:\s*c4 e5 68 fd c9\s+tdpbf8ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 70 fd ca\s+tdpbf8ps %tmm1/\(bad\),%tmm2,%tmm1\/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 73 fd d1\s+tdpbhf8ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
+\s*[a-f0-9]+:\s*c4 e5 6b fd c9\s+tdpbhf8ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 73 fd ca\s+tdpbhf8ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 72 fd d1\s+tdphbf8ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
+\s*[a-f0-9]+:\s*c4 e5 6a fd c9\s+tdphbf8ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 72 fd ca\s+tdphbf8ps %tmm1/\(bad\),%tmm2,%tmm1\/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 71 fd d1\s+tdphf8ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
+\s*[a-f0-9]+:\s*c4 e5 69 fd c9\s+tdphf8ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
+\s*[a-f0-9]+:\s*c4 e5 71 fd ca\s+tdphf8ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
+#pass
new file mode 100644
@@ -0,0 +1,36 @@
+ .text
+ # tdpbf8ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
+ .insn VEX.128.NP.M5.W0 0xfd, %tmm1, %tmm1, %tmm2
+
+ # tdpbf8ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.NP.M5.W0 0xfd, %tmm1, %tmm2, %tmm1
+
+ # tdpbf8ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.NP.M5.W0 0xfd, %tmm2, %tmm1, %tmm1
+
+ # tdpbhf8ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
+ .insn VEX.128.f2.M5.W0 0xfd, %tmm1, %tmm1, %tmm2
+
+ # tdpbhf8ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.f2.M5.W0 0xfd, %tmm1, %tmm2, %tmm1
+
+ # tdpbhf8ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.f2.M5.W0 0xfd, %tmm2, %tmm1, %tmm1
+
+ # tdphbf8ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
+ .insn VEX.128.f3.M5.W0 0xfd, %tmm1, %tmm1, %tmm2
+
+ # tdphbf8ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.f3.M5.W0 0xfd, %tmm1, %tmm2, %tmm1
+
+ # tdphbf8ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.f3.M5.W0 0xfd, %tmm2, %tmm1, %tmm1
+
+ # tdphf8ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
+ .insn VEX.128.66.M5.W0 0xfd, %tmm1, %tmm1, %tmm2
+
+ # tdphf8ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.66.M5.W0 0xfd, %tmm1, %tmm2, %tmm1
+
+ # tdphf8ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
+ .insn VEX.128.66.M5.W0 0xfd, %tmm2, %tmm1, %tmm1
new file mode 100644
@@ -0,0 +1,19 @@
+#objdump: -dw -Mintel
+#name: x86_64 AMX-FP8 insns (Intel disassembly)
+#source: x86-64-amx-fp8.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*c4 e5 58 fd f5\s+tdpbf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 70 fd da\s+tdpbf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 5b fd f5\s+tdpbhf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 73 fd da\s+tdpbhf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 5a fd f5\s+tdphbf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 72 fd da\s+tdphbf8ps tmm3,tmm2,tmm1
+\s*[a-f0-9]+:\s*c4 e5 59 fd f5\s+tdphf8ps tmm6,tmm5,tmm4
+\s*[a-f0-9]+:\s*c4 e5 71 fd da\s+tdphf8ps tmm3,tmm2,tmm1
+#pass
new file mode 100644
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:5: Error: all tmm registers must be distinct for `tdpbf8ps'
+.*:6: Error: all tmm registers must be distinct for `tdpbf8ps'
+.*:7: Error: all tmm registers must be distinct for `tdpbhf8ps'
+.*:8: Error: all tmm registers must be distinct for `tdpbhf8ps'
+.*:9: Error: all tmm registers must be distinct for `tdphbf8ps'
+.*:10: Error: all tmm registers must be distinct for `tdphbf8ps'
+.*:11: Error: all tmm registers must be distinct for `tdphf8ps'
+.*:12: Error: all tmm registers must be distinct for `tdphf8ps'
new file mode 100644
@@ -0,0 +1,12 @@
+# Check Illegal AMX-FP8 instructions
+
+ .text
+_start:
+ tdpbf8ps %tmm1, %tmm1, %tmm2
+ tdpbf8ps %tmm1, %tmm2, %tmm2
+ tdpbhf8ps %tmm1, %tmm1, %tmm2
+ tdpbhf8ps %tmm1, %tmm2, %tmm2
+ tdphbf8ps %tmm1, %tmm1, %tmm2
+ tdphbf8ps %tmm1, %tmm2, %tmm2
+ tdphf8ps %tmm1, %tmm1, %tmm2
+ tdphf8ps %tmm1, %tmm2, %tmm2
new file mode 100644
@@ -0,0 +1,17 @@
+#objdump: -dw
+#name: x86_64 AMX-FP8 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e5 58 fd f5\s+tdpbf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 70 fd da\s+tdpbf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 5b fd f5\s+tdpbhf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 73 fd da\s+tdpbhf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 5a fd f5\s+tdphbf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 72 fd da\s+tdphbf8ps %tmm1,%tmm2,%tmm3
+\s*[a-f0-9]+:\s*c4 e5 59 fd f5\s+tdphf8ps %tmm4,%tmm5,%tmm6
+\s*[a-f0-9]+:\s*c4 e5 71 fd da\s+tdphf8ps %tmm1,%tmm2,%tmm3
+#pass
new file mode 100644
@@ -0,0 +1,23 @@
+# Check 64bit AMX-FP8 instructions
+
+ .text
+_start:
+ tdpbf8ps %tmm4, %tmm5, %tmm6
+ tdpbf8ps %tmm1, %tmm2, %tmm3
+ tdpbhf8ps %tmm4, %tmm5, %tmm6
+ tdpbhf8ps %tmm1, %tmm2, %tmm3
+ tdphbf8ps %tmm4, %tmm5, %tmm6
+ tdphbf8ps %tmm1, %tmm2, %tmm3
+ tdphf8ps %tmm4, %tmm5, %tmm6
+ tdphf8ps %tmm1, %tmm2, %tmm3
+
+_intel:
+ .intel_syntax noprefix
+ tdpbf8ps tmm6, tmm5, tmm4
+ tdpbf8ps tmm3, tmm2, tmm1
+ tdpbhf8ps tmm6, tmm5, tmm4
+ tdpbhf8ps tmm3, tmm2, tmm1
+ tdphbf8ps tmm6, tmm5, tmm4
+ tdphbf8ps tmm3, tmm2, tmm1
+ tdphf8ps tmm6, tmm5, tmm4
+ tdphf8ps tmm3, tmm2, tmm1
@@ -531,6 +531,10 @@ run_dump_test "x86-64-amx-tf32"
run_dump_test "x86-64-amx-tf32-intel"
run_list_test "x86-64-amx-tf32-inval"
run_dump_test "x86-64-amx-tf32-bad"
+run_dump_test "x86-64-amx-fp8"
+run_dump_test "x86-64-amx-fp8-intel"
+run_list_test "x86-64-amx-fp8-inval"
+run_dump_test "x86-64-amx-fp8-bad"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
@@ -1159,6 +1159,7 @@ enum
PREFIX_VEX_0F38F6_L_0,
PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0,
+ PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0,
PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
@@ -1360,6 +1361,7 @@ enum
X86_64_VEX_0F386F,
X86_64_VEX_0F38Ex,
+ X86_64_VEX_MAP5_FD,
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
};
@@ -1382,6 +1384,7 @@ enum
VEX_0F = 0,
VEX_0F38,
VEX_0F3A,
+ VEX_MAP5,
VEX_MAP7,
};
@@ -1480,6 +1483,7 @@ enum
VEX_LEN_0F3ADE_W_0,
VEX_LEN_0F3ADF,
VEX_LEN_0F3AF0,
+ VEX_LEN_MAP5_FD_X86_64,
VEX_LEN_MAP7_F6,
VEX_LEN_MAP7_F8,
VEX_LEN_XOP_08_85,
@@ -1652,6 +1656,7 @@ enum
VEX_W_0F3ACE,
VEX_W_0F3ACF,
VEX_W_0F3ADE,
+ VEX_W_MAP5_FD_X86_64_L_0,
VEX_W_MAP7_F6_L_0,
VEX_W_MAP7_F8_L_0,
@@ -4278,6 +4283,14 @@ static const struct dis386 prefix_table[][4] = {
{ "%XErorxS", { Gdq, Edq, Ib }, 0 },
},
+ /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */
+ {
+ { "tdpbf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdphbf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdphf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdpbhf8ps", { TMM, Rtmm, VexTmm }, 0 },
+ },
+
/* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
{
{ Bad_Opcode },
@@ -4680,6 +4693,12 @@ static const struct dis386 x86_64_table[][2] = {
{ "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
},
+ /* X86_64_VEX_MAP5_FD */
+ {
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_MAP5_FD_X86_64) },
+ },
+
/* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
{
{ Bad_Opcode },
@@ -7468,6 +7487,11 @@ static const struct dis386 vex_len_table[][2] = {
{ PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
},
+ /* VEX_LEN_MAP5_FD_X86_64 */
+ {
+ { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) },
+ },
+
/* VEX_LEN_MAP7_F6 */
{
{ VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
@@ -8104,6 +8128,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3ADE */
{ VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
},
+ {
+ /* VEX_W_MAP5_FD_X86_64 */
+ { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) },
+ },
{
/* VEX_W_MAP7_F6_L_0 */
{ REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
@@ -8861,6 +8889,7 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
/* Fetch error indicator. */
static const struct dis386 err_opcode = { NULL, { XX }, 0 };
+static const struct dis386 map5_fd_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_FD) };
static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) };
static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
@@ -9135,6 +9164,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
case 0x3:
vex_table_index = VEX_0F3A;
break;
+ case 0x5:
+ vex_table_index = VEX_MAP5;
+ break;
case 0x7:
vex_table_index = VEX_MAP7;
break;
@@ -9173,12 +9205,14 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
ins->codep++;
vindex = *ins->codep++;
ins->condition_code = vindex & 0xf;
- if (vex_table_index != VEX_MAP7)
+ if (vex_table_index != VEX_MAP7 && vex_table_index != VEX_MAP5)
dp = &vex_table[vex_table_index][vindex];
else if (vindex == 0xf6)
dp = &map7_f6_opcode;
else if (vindex == 0xf8)
dp = &map7_f8_opcode;
+ else if (vindex == 0xfd)
+ dp = &map5_fd_opcode;
else
dp = &bad_opcode;
ins->end_codep = ins->codep;
@@ -269,6 +269,8 @@ static const dependency isa_dependencies[] =
"AMX_TILE" },
{ "AMX_TF32",
"AMX_TILE" },
+ { "AMX_FP8",
+ "AMX_TILE" },
{ "KL",
"SSE2" },
{ "WIDEKL",
@@ -437,6 +439,7 @@ static bitfield cpu_flags[] =
BITFIELD (AMX_COMPLEX),
BITFIELD (AMX_TRANSPOSE),
BITFIELD (AMX_TF32),
+ BITFIELD (AMX_FP8),
BITFIELD (AMX_TILE),
BITFIELD (MOVDIRI),
BITFIELD (MOVDIR64B),
@@ -252,6 +252,8 @@ enum i386_cpu
CpuAMX_COMPLEX,
/* AMX-TF32 Instructions support required. */
CpuAMX_TF32,
+ /* AMX-FP8 instructions required */
+ CpuAMX_FP8,
/* AMX-TILE instructions required */
CpuAMX_TILE,
/* GFNI instructions required */
@@ -503,6 +505,7 @@ typedef union i386_cpu_flags
unsigned int cpuamx_fp16:1;
unsigned int cpuamx_complex:1;
unsigned int cpuamx_tf32:1;
+ unsigned int cpuamx_fp8:1;
unsigned int cpuamx_tile:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
@@ -3233,6 +3233,11 @@ ttransposed, 0xf35f, AMX_TRANSPOSE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM
tmmultf32ps, 0x6648, AMX_TF32, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
ttmmultf32ps, 0x48, AMX_TF32&AMX_TRANSPOSE, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdpbf8ps, 0xfd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+
// AMX instructions end.
// KEYLOCKER instructions.