| Message ID | 20241213-upstream-intelgt-mvp-v2-4-5c4caeb7b33d@intel.com |
|---|---|
| State | New |
| Headers |
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| Series |
[v2,01/47] gdb, intelgt: add intelgt as a basic machine
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Commit Message
Aktemur, Tankut Baris
Dec. 13, 2024, 3:59 p.m. UTC
Intel GT does not use the opcodes lib for disassembling instructions. Therefore, add the simplest configuration to satisfy building without errors. To: <binutils@sourceware.org> --- opcodes/configure | 1 + opcodes/configure.ac | 1 + 2 files changed, 2 insertions(+)
Comments
On 13.12.2024 16:59, Tankut Baris Aktemur wrote:
> Intel GT does not use the opcodes lib for disassembling instructions.
How else is disassembly going to work?
Jan
On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: > On 13.12.2024 16:59, Tankut Baris Aktemur wrote: > > Intel GT does not use the opcodes lib for disassembling instructions. > > How else is disassembly going to work? > > Jan For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. The patch that adds disassembly support is https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html Regards -Baris [1]: https://github.com/intel/intel-graphics-compiler Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928
On 17.12.2024 19:47, Aktemur, Tankut Baris wrote: > On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: >> On 13.12.2024 16:59, Tankut Baris Aktemur wrote: >>> Intel GT does not use the opcodes lib for disassembling instructions. >> >> How else is disassembly going to work? > > For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. > The patch that adds disassembly support is > > https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html That's (a) interesting and (b) covering only gdb; what about objdump? Jan
On Wednesday, December 18, 2024 8:22 AM, Jan Beulich wrote: > On 17.12.2024 19:47, Aktemur, Tankut Baris wrote: > > On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: > >> On 13.12.2024 16:59, Tankut Baris Aktemur wrote: > >>> Intel GT does not use the opcodes lib for disassembling instructions. > >> > >> How else is disassembly going to work? > > > > For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. > > The patch that adds disassembly support is > > > > https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html > > That's (a) interesting and (b) covering only gdb; what about objdump? > > Jan Our case is similar to AMD GPU (ROCm) debugging, for which there is already support in upstream GDB. For disassembling, the amdgpu target also uses a separate disassembler that is part of their debug API library: https://inbox.sourceware.org/binutils/20220315194303.3716792-3-simon.marchi@polymtl.ca/ https://rocm.docs.amd.com/projects/ROCdbgapi/en/latest/doxygen/html/group__architecture__group.html#ga1958899dde4a98c13980e1cb7d657acd I believe the amdgpu target has similar configuration restrictions with our target. Adding Simon to Cc to confirm. Thanks, -Baris Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928
On 2024-12-20 04:47, Aktemur, Tankut Baris wrote: > On Wednesday, December 18, 2024 8:22 AM, Jan Beulich wrote: >> On 17.12.2024 19:47, Aktemur, Tankut Baris wrote: >>> On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: >>>> On 13.12.2024 16:59, Tankut Baris Aktemur wrote: >>>>> Intel GT does not use the opcodes lib for disassembling instructions. >>>> >>>> How else is disassembly going to work? >>> >>> For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. >>> The patch that adds disassembly support is >>> >>> https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html >> >> That's (a) interesting and (b) covering only gdb; what about objdump? >> >> Jan > > Our case is similar to AMD GPU (ROCm) debugging, for which there is > already support in upstream GDB. For disassembling, the amdgpu target > also uses a separate disassembler that is part of their debug API > library: > > https://inbox.sourceware.org/binutils/20220315194303.3716792-3-simon.marchi@polymtl.ca/ > https://rocm.docs.amd.com/projects/ROCdbgapi/en/latest/doxygen/html/group__architecture__group.html#ga1958899dde4a98c13980e1cb7d657acd > > I believe the amdgpu target has similar configuration restrictions > with our target. Adding Simon to Cc to confirm. > > Thanks, > -Baris As far as I know, what Baris says is true. Simon
Hello Jan, On Friday, January 3, 2025 5:46 AM, Simon Marchi wrote: > On 2024-12-20 04:47, Aktemur, Tankut Baris wrote: > > On Wednesday, December 18, 2024 8:22 AM, Jan Beulich wrote: > >> On 17.12.2024 19:47, Aktemur, Tankut Baris wrote: > >>> On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: > >>>> On 13.12.2024 16:59, Tankut Baris Aktemur wrote: > >>>>> Intel GT does not use the opcodes lib for disassembling instructions. > >>>> > >>>> How else is disassembly going to work? > >>> > >>> For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. > >>> The patch that adds disassembly support is > >>> > >>> https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html > >> > >> That's (a) interesting and (b) covering only gdb; what about objdump? > >> > >> Jan > > > > Our case is similar to AMD GPU (ROCm) debugging, for which there is > > already support in upstream GDB. For disassembling, the amdgpu target > > also uses a separate disassembler that is part of their debug API > > library: > > > > https://inbox.sourceware.org/binutils/20220315194303.3716792-3-simon.marchi@polymtl.ca/ > > > https://rocm.docs.amd.com/projects/ROCdbgapi/en/latest/doxygen/html/group__architecture__gro > up.html#ga1958899dde4a98c13980e1cb7d657acd > > > > I believe the amdgpu target has similar configuration restrictions > > with our target. Adding Simon to Cc to confirm. > > > > Thanks, > > -Baris > > As far as I know, what Baris says is true. > > Simon Any further comments on this? Regards, -Baris Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928
On 03.02.2025 18:13, Aktemur, Tankut Baris wrote: > Hello Jan, > > On Friday, January 3, 2025 5:46 AM, Simon Marchi wrote: >> On 2024-12-20 04:47, Aktemur, Tankut Baris wrote: >>> On Wednesday, December 18, 2024 8:22 AM, Jan Beulich wrote: >>>> On 17.12.2024 19:47, Aktemur, Tankut Baris wrote: >>>>> On Monday, December 16, 2024 8:44 AM, Jan Beulich wrote: >>>>>> On 13.12.2024 16:59, Tankut Baris Aktemur wrote: >>>>>>> Intel GT does not use the opcodes lib for disassembling instructions. >>>>>> >>>>>> How else is disassembly going to work? >>>>> >>>>> For disassembly, libiga (IGA library from Intel Graphics Compiler [1]) is used. >>>>> The patch that adds disassembly support is >>>>> >>>>> https://sourceware.org/pipermail/gdb-patches/2024-December/214036.html >>>> >>>> That's (a) interesting and (b) covering only gdb; what about objdump? >>>> >>>> Jan >>> >>> Our case is similar to AMD GPU (ROCm) debugging, for which there is >>> already support in upstream GDB. For disassembling, the amdgpu target >>> also uses a separate disassembler that is part of their debug API >>> library: >>> >>> https://inbox.sourceware.org/binutils/20220315194303.3716792-3-simon.marchi@polymtl.ca/ >>> >> https://rocm.docs.amd.com/projects/ROCdbgapi/en/latest/doxygen/html/group__architecture__gro >> up.html#ga1958899dde4a98c13980e1cb7d657acd >>> >>> I believe the amdgpu target has similar configuration restrictions >>> with our target. Adding Simon to Cc to confirm. >>> >>> Thanks, >>> -Baris >> >> As far as I know, what Baris says is true. >> >> Simon > > Any further comments on this? As with the other patch - since you copy pre-existing behavior, I'm okay(ish). Jan
diff --git a/opcodes/configure b/opcodes/configure index 547e5afc76657db80c08ee762d19fd8ff17fb4e0..262fdb25e3f8e17134a48f21cf62dbe856145b81 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -14470,6 +14470,7 @@ if test x${all_targets} = xfalse ; then bfd_i386_arch|bfd_iamcu_arch) ta="$ta i386-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_intelgt_arch) ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index 51045b6217815b2c29d802b94c49a69c1719b791..c9f6cabb9220cf6073df3a3de6efe9b57b7ef347 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -286,6 +286,7 @@ if test x${all_targets} = xfalse ; then bfd_i386_arch|bfd_iamcu_arch) ta="$ta i386-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_intelgt_arch) ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;