diff mbox series

Support Intel SM4 EVEX extension

Message ID 20241205070415.1868470-1-haochen.jiang@intel.com
State New
Headers
Series Support Intel SM4 EVEX extension |

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Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
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Commit Message

Jiang, Haochen Dec. 5, 2024, 7:04 a.m. UTC 
  Hi all,

As only one patch remaining, AVX10.2 is becoming stable. It is
the time to add the ISAs adjacent to it. This patch will focus
on the EVEX extension for SM4.

You could check the detail for SM4 in ISE055:
https://cdrdv2.intel.com/v1/dl/getContent/671368

Patch descrption are embedded below.

Tested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

Nit: When I send the patch, I found that the AVX10.2/256 and
AVX10.2/512 tests are combined with each other. I would split them.

---

In this patch, we will support SM4 EVEX extension part. It is
a promotion from VEX encoding to EVEX encoding. The EVEX encoding
is based on AVX10.2, which is the same as the upcoming MOVRS ISA.
Thus, we decide to pull AVX10.2 out to CPU_COMMON_FLAGS.

gas/ChangeLog:

	* NEWS: Support Intel SM4 EVEX instructions.
	* config/tc-i386.c (_is_cpu): Handle AVX10.2.
	* testsuite/gas/i386/i386.exp: Run SM4 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx10_2sm4-intel.d: Add SM4 tests.
	* testsuite/gas/i386/avx10_2sm4-inval.l: Ditto.
	* testsuite/gas/i386/avx10_2sm4-inval.s: Ditto.
	* testsuite/gas/i386/avx10_2sm4.d: Ditto.
	* testsuite/gas/i386/avx10_2sm4.s: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2sm4-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2sm4-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2sm4-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2sm4.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2sm4.s: Ditto.

opcodes/ChangeLog:

	* i386-dis-evex.h: Add evex table entry for SM4.
	* i386-dis.h: Ditto.
	* i386-opc.h: (i386_cpu): Move AVX10.2 to CPU_FLAGS_COMMON.
	* i386-opc.tbl: Add SM4 EVEX instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Ditto.
---
 gas/NEWS                                      |     2 +
 gas/config/tc-i386.c                          |     1 +
 gas/testsuite/gas/i386/avx10_2sm4-intel.d     |    41 +
 gas/testsuite/gas/i386/avx10_2sm4-inval.l     |     5 +
 gas/testsuite/gas/i386/avx10_2sm4-inval.s     |     9 +
 gas/testsuite/gas/i386/avx10_2sm4.d           |    39 +
 gas/testsuite/gas/i386/avx10_2sm4.s           |    67 +
 gas/testsuite/gas/i386/i386.exp               |     3 +
 .../gas/i386/x86-64-avx10_2sm4-intel.d        |    41 +
 .../gas/i386/x86-64-avx10_2sm4-inval.l        |     5 +
 .../gas/i386/x86-64-avx10_2sm4-inval.s        |     9 +
 gas/testsuite/gas/i386/x86-64-avx10_2sm4.d    |    39 +
 gas/testsuite/gas/i386/x86-64-avx10_2sm4.s    |    67 +
 gas/testsuite/gas/i386/x86-64.exp             |     3 +
 opcodes/i386-dis-evex.h                       |     2 +-
 opcodes/i386-dis.c                            |     4 +-
 opcodes/i386-init.h                           |   442 +-
 opcodes/i386-opc.h                            |     6 +-
 opcodes/i386-opc.tbl                          |     3 +
 opcodes/i386-tbl.h                            | 18358 ++++++++--------
 20 files changed, 9752 insertions(+), 9394 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/avx10_2sm4-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx10_2sm4-inval.l
 create mode 100644 gas/testsuite/gas/i386/avx10_2sm4-inval.s
 create mode 100644 gas/testsuite/gas/i386/avx10_2sm4.d
 create mode 100644 gas/testsuite/gas/i386/avx10_2sm4.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2sm4-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2sm4.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2sm4.s

Comments

Jan Beulich Dec. 10, 2024, 7:41 a.m. UTC | #1 
On 05.12.2024 08:04, Haochen Jiang wrote:
> Nit: When I send the patch, I found that the AVX10.2/256 and
> AVX10.2/512 tests are combined with each other. I would split them.

Yes please.

> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
>  -*- text -*-
>  
> +* Add support for the x86 Intel SM4 EVEX instructions.

For a NEWS entry I think EVEX is too technical. Imo it wants to mention
AVX10.2 instead.

> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -229,8 +229,6 @@ enum i386_cpu
>    CpuUSER_MSR,
>    /* Intel MSR_IMM Instructions support required.  */
>    CpuMSR_IMM,
> -  /* Intel AVX10.2 Instructions support required.  */
> -  CpuAVX10_2,
>    /* mwaitx instruction required */
>    CpuMWAITX,
>    /* Clzero instruction required */
> @@ -337,6 +335,8 @@ enum i386_cpu
>    CpuAPX_F,
>    /* Intel AMX-TRANSPOSE Instructions support required.  */
>    CpuAMX_TRANSPOSE,
> +  /* Intel AVX10.2 Instructions support required.  */
> +  CpuAVX10_2,
>    /* Not supported in the 64bit mode  */
>    CpuNo64,

I was going to ask to put this ahead of AMX-TRANSPOSE, but there's no
AMX-TRANSPOSE in the upstream file at all so far. Did you forget to
re-base onto the plain upstream tree?

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -2196,6 +2196,9 @@ vsm3msg2, 0x66da, SM3, Modrm|Space0F38|Vex128|Src1VVVV|VexW0|NoSuf, { RegXMM|Uns
>  vsm4key4, 0xf3da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>  vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>  
> +vsm4key4, 0xf3da, SM4&AVX10_2, Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +vsm4rnds4, 0xf2da, SM4&AVX10_2, Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> +
>  // SM4 instructions end.

Hmm, why is it that these can't be merged together, just like we merge
other AVX(-like) templates with their AVX512 ones? One question of course
is going to be whether this will be outliers, in which case the logic
needed in tc-i386.c may not be worth to add.

If they can't be merged, I think they would want at least templatizing,
though.

Jan
Jiang, Haochen Dec. 10, 2024, 8:23 a.m. UTC | #2 
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, December 10, 2024 3:42 PM
> 
> > --- a/opcodes/i386-opc.h
> > +++ b/opcodes/i386-opc.h
> > @@ -229,8 +229,6 @@ enum i386_cpu
> >    CpuUSER_MSR,
> >    /* Intel MSR_IMM Instructions support required.  */
> >    CpuMSR_IMM,
> > -  /* Intel AVX10.2 Instructions support required.  */
> > -  CpuAVX10_2,
> >    /* mwaitx instruction required */
> >    CpuMWAITX,
> >    /* Clzero instruction required */
> > @@ -337,6 +335,8 @@ enum i386_cpu
> >    CpuAPX_F,
> >    /* Intel AMX-TRANSPOSE Instructions support required.  */
> >    CpuAMX_TRANSPOSE,
> > +  /* Intel AVX10.2 Instructions support required.  */  CpuAVX10_2,
> >    /* Not supported in the 64bit mode  */
> >    CpuNo64,
> 
> I was going to ask to put this ahead of AMX-TRANSPOSE, but there's no AMX-
> TRANSPOSE in the upstream file at all so far. Did you forget to re-base onto the
> plain upstream tree?

The patch is based on where AMX-TRANSPOSE is there in my tree. I will send the patch
on plain upstream tree for v2.

> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -2196,6 +2196,9 @@ vsm3msg2, 0x66da, SM3,
> > Modrm|Space0F38|Vex128|Src1VVVV|VexW0|NoSuf, { RegXMM|Uns
> vsm4key4,
> > 0xf3da, SM4,
> > Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, {
> > RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,
> RegXMM|RegYMM }
> > vsm4rnds4, 0xf2da, SM4,
> > Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, {
> > RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,
> RegXMM|RegYMM }
> >
> > +vsm4key4, 0xf3da, SM4&AVX10_2,
> >
> +Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|N
> oSuf, {
> > +RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> > +RegXMM|RegYMM|RegZMM } vsm4rnds4, 0xf2da, SM4&AVX10_2,
> >
> +Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|N
> oSuf, {
> > +RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> > +RegXMM|RegYMM|RegZMM }
> > +
> >  // SM4 instructions end.
> 
> Hmm, why is it that these can't be merged together, just like we merge other
> AVX(-like) templates with their AVX512 ones? One question of course is going
> to be whether this will be outliers, in which case the logic needed in tc-i386.c
> may not be worth to add.
> 
> If they can't be merged, I think they would want at least templatizing, though.
> 

SM4 should be the only ISA under AVX10.2 needs this special handling if we choose
to merge them since MOVRS does not need that. I am ok with both way. Let me see
which is better.

Thx,
Haochen
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 90a83c83ea2..20216dc6d59 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for the x86 Intel SM4 EVEX instructions.
+
 * Add support for the x86 Intel Diamond Rapids AMX instructions,
   including AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32 and AMX-TRANSPOSE.
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d54813c451e..19466c10529 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1873,6 +1873,7 @@  _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
     case CpuAVX512VL: return a->bitfield.cpuavx512vl;
     case CpuAPX_F:    return a->bitfield.cpuapx_f;
     case CpuAMX_TRANSPOSE:  return a->bitfield.cpuamx_transpose;
+    case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
     case Cpu64:       return a->bitfield.cpu64;
     case CpuNo64:     return a->bitfield.cpuno64;
     default:
diff --git a/gas/testsuite/gas/i386/avx10_2sm4-intel.d b/gas/testsuite/gas/i386/avx10_2sm4-intel.d
new file mode 100644
index 00000000000..ae69a169eef
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2sm4-intel.d
@@ -0,0 +1,41 @@ 
+#objdump: -dw -Mintel
+#name: i386 AVX10_2, SM4 insns (Intel disassembly)
+#source: avx10_2sm4.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 f2 56 48 da f4\s+vsm4key4 zmm6,zmm5,zmm4
+\s*[a-f0-9]+:\s*62 f2 56 28 da f4\s+{evex} vsm4key4 ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*62 f2 56 08 da f4\s+{evex} vsm4key4 xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*62 f2 56 48 da b4 f4 00 00 00 10\s+vsm4key4 zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 56 48 da 31\s+vsm4key4 zmm6,zmm5,ZMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 56 48 da 71 7f\s+vsm4key4 zmm6,zmm5,ZMMWORD PTR \[ecx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 f2 56 48 da 72 80\s+vsm4key4 zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
+\s*[a-f0-9]+:\s*62 f2 56 28 da b4 f4 00 00 00 10\s+{evex} vsm4key4 ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 56 28 da 31\s+{evex} vsm4key4 ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 56 28 da 71 7f\s+{evex} vsm4key4 ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 56 28 da 72 80\s+{evex} vsm4key4 ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 56 08 da b4 f4 00 00 00 10\s+{evex} vsm4key4 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 56 08 da 31\s+{evex} vsm4key4 xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 56 08 da 71 7f\s+{evex} vsm4key4 xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 56 08 da 72 80\s+{evex} vsm4key4 xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 57 48 da f4\s+vsm4rnds4 zmm6,zmm5,zmm4
+\s*[a-f0-9]+:\s*62 f2 57 28 da f4\s+{evex} vsm4rnds4 ymm6,ymm5,ymm4
+\s*[a-f0-9]+:\s*62 f2 57 08 da f4\s+{evex} vsm4rnds4 xmm6,xmm5,xmm4
+\s*[a-f0-9]+:\s*62 f2 57 48 da b4 f4 00 00 00 10\s+vsm4rnds4 zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 57 48 da 31\s+vsm4rnds4 zmm6,zmm5,ZMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 57 48 da 71 7f\s+vsm4rnds4 zmm6,zmm5,ZMMWORD PTR \[ecx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 f2 57 48 da 72 80\s+vsm4rnds4 zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
+\s*[a-f0-9]+:\s*62 f2 57 28 da b4 f4 00 00 00 10\s+{evex} vsm4rnds4 ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 57 28 da 31\s+{evex} vsm4rnds4 ymm6,ymm5,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 57 28 da 71 7f\s+{evex} vsm4rnds4 ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 57 28 da 72 80\s+{evex} vsm4rnds4 ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 57 08 da b4 f4 00 00 00 10\s+{evex} vsm4rnds4 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 57 08 da 31\s+{evex} vsm4rnds4 xmm6,xmm5,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 57 08 da 71 7f\s+{evex} vsm4rnds4 xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 57 08 da 72 80\s+{evex} vsm4rnds4 xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx10_2sm4-inval.l b/gas/testsuite/gas/i386/avx10_2sm4-inval.l
new file mode 100644
index 00000000000..b5410c2770f
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2sm4-inval.l
@@ -0,0 +1,5 @@ 
+.* Assembler messages:
+.*:6: Error: operand size mismatch for `vsm4key4'
+.*:7: Error: operand size mismatch for `vsm4rnds4'
+.*:8: Error: no EVEX encoding for `vsm4key4'
+.*:9: Error: no EVEX encoding for `vsm4rnds4'
diff --git a/gas/testsuite/gas/i386/avx10_2sm4-inval.s b/gas/testsuite/gas/i386/avx10_2sm4-inval.s
new file mode 100644
index 00000000000..8bd6aea3637
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2sm4-inval.s
@@ -0,0 +1,9 @@ 
+# Check Illegal 32bit SM4 instructions
+
+	.text
+	.arch .noavx10.2
+_start:
+	vsm4key4	%zmm4, %zmm5, %zmm6 
+	vsm4rnds4	%zmm4, %zmm5, %zmm6
+	{evex} vsm4key4	%ymm4, %ymm5, %ymm6 
+	{evex} vsm4rnds4	%xmm4, %xmm5, %xmm6
diff --git a/gas/testsuite/gas/i386/avx10_2sm4.d b/gas/testsuite/gas/i386/avx10_2sm4.d
new file mode 100644
index 00000000000..227662f6fd5
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2sm4.d
@@ -0,0 +1,39 @@ 
+#objdump: -dw
+#name: i386 AVX10_2, SM4 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f2 56 48 da f4\s+vsm4key4 %zmm4,%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 56 28 da f4\s+{evex} vsm4key4 %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 56 08 da f4\s+{evex} vsm4key4 %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 56 48 da b4 f4 00 00 00 10\s+vsm4key4 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 56 48 da 31\s+vsm4key4 \(%ecx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 56 48 da 71 7f\s+vsm4key4 0x1fc0\(%ecx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 56 48 da 72 80\s+vsm4key4 -0x2000\(%edx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 56 28 da b4 f4 00 00 00 10\s+{evex} vsm4key4 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 56 28 da 31\s+{evex} vsm4key4 \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 56 28 da 71 7f\s+{evex} vsm4key4 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 56 28 da 72 80\s+{evex} vsm4key4 -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 56 08 da b4 f4 00 00 00 10\s+{evex} vsm4key4 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 56 08 da 31\s+{evex} vsm4key4 \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 56 08 da 71 7f\s+{evex} vsm4key4 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 56 08 da 72 80\s+{evex} vsm4key4 -0x800\(%edx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 57 48 da f4\s+vsm4rnds4 %zmm4,%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 57 28 da f4\s+{evex} vsm4rnds4 %ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 57 08 da f4\s+{evex} vsm4rnds4 %xmm4,%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 57 48 da b4 f4 00 00 00 10\s+vsm4rnds4 0x10000000\(%esp,%esi,8\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 57 48 da 31\s+vsm4rnds4 \(%ecx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 57 48 da 71 7f\s+vsm4rnds4 0x1fc0\(%ecx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 57 48 da 72 80\s+vsm4rnds4 -0x2000\(%edx\),%zmm5,%zmm6
+\s*[a-f0-9]+:\s*62 f2 57 28 da b4 f4 00 00 00 10\s+{evex} vsm4rnds4 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 57 28 da 31\s+{evex} vsm4rnds4 \(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 57 28 da 71 7f\s+{evex} vsm4rnds4 0xfe0\(%ecx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 57 28 da 72 80\s+{evex} vsm4rnds4 -0x1000\(%edx\),%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 57 08 da b4 f4 00 00 00 10\s+{evex} vsm4rnds4 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 57 08 da 31\s+{evex} vsm4rnds4 \(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 57 08 da 71 7f\s+{evex} vsm4rnds4 0x7f0\(%ecx\),%xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 57 08 da 72 80\s+{evex} vsm4rnds4 -0x800\(%edx\),%xmm5,%xmm6
+#pass
diff --git a/gas/testsuite/gas/i386/avx10_2sm4.s b/gas/testsuite/gas/i386/avx10_2sm4.s
new file mode 100644
index 00000000000..24ffa597a1b
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2sm4.s
@@ -0,0 +1,67 @@ 
+# Check 32bit SM4 instructions
+
+	.text
+_start:
+	vsm4key4	%zmm4, %zmm5, %zmm6
+	{evex} vsm4key4	%ymm4, %ymm5, %ymm6
+	{evex} vsm4key4	%xmm4, %xmm5, %xmm6
+	vsm4key4	0x10000000(%esp, %esi, 8), %zmm5, %zmm6
+	vsm4key4	(%ecx), %zmm5, %zmm6
+	vsm4key4	8128(%ecx), %zmm5, %zmm6
+	vsm4key4	-8192(%edx), %zmm5, %zmm6
+	{evex} vsm4key4	0x10000000(%esp, %esi, 8), %ymm5, %ymm6
+	{evex} vsm4key4	(%ecx), %ymm5, %ymm6
+	{evex} vsm4key4	4064(%ecx), %ymm5, %ymm6
+	{evex} vsm4key4	-4096(%edx), %ymm5, %ymm6
+	{evex} vsm4key4	0x10000000(%esp, %esi, 8), %xmm5, %xmm6
+	{evex} vsm4key4	(%ecx), %xmm5, %xmm6
+	{evex} vsm4key4	2032(%ecx), %xmm5, %xmm6
+	{evex} vsm4key4	-2048(%edx), %xmm5, %xmm6
+	vsm4rnds4	%zmm4, %zmm5, %zmm6
+	{evex} vsm4rnds4	%ymm4, %ymm5, %ymm6
+	{evex} vsm4rnds4	%xmm4, %xmm5, %xmm6
+	vsm4rnds4	0x10000000(%esp, %esi, 8), %zmm5, %zmm6
+	vsm4rnds4	(%ecx), %zmm5, %zmm6
+	vsm4rnds4	8128(%ecx), %zmm5, %zmm6
+	vsm4rnds4	-8192(%edx), %zmm5, %zmm6
+	{evex} vsm4rnds4	0x10000000(%esp, %esi, 8), %ymm5, %ymm6
+	{evex} vsm4rnds4	(%ecx), %ymm5, %ymm6
+	{evex} vsm4rnds4	4064(%ecx), %ymm5, %ymm6
+	{evex} vsm4rnds4	-4096(%edx), %ymm5, %ymm6
+	{evex} vsm4rnds4	0x10000000(%esp, %esi, 8), %xmm5, %xmm6
+	{evex} vsm4rnds4	(%ecx), %xmm5, %xmm6
+	{evex} vsm4rnds4	2032(%ecx), %xmm5, %xmm6
+	{evex} vsm4rnds4	-2048(%edx), %xmm5, %xmm6
+
+_intel:
+	.intel_syntax noprefix
+	vsm4key4	zmm6, zmm5, zmm4
+	{evex} vsm4key4	ymm6, ymm5, ymm4
+	{evex} vsm4key4	xmm6, xmm5, xmm4
+	vsm4key4	zmm6, zmm5, ZMMWORD PTR [esp+esi*8+0x10000000]
+	vsm4key4	zmm6, zmm5, [ecx]
+	vsm4key4	zmm6, zmm5, ZMMWORD PTR [ecx+8128]
+	vsm4key4	zmm6, zmm5, [edx-8192]
+	{evex} vsm4key4	ymm6, ymm5, [esp+esi*8+0x10000000]
+	{evex} vsm4key4	ymm6, ymm5, YMMWORD PTR [ecx] 
+	{evex} vsm4key4	ymm6, ymm5, [ecx+4064]
+	{evex} vsm4key4	ymm6, ymm5, YMMWORD PTR [edx-4096]
+	{evex} vsm4key4	xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000]
+	{evex} vsm4key4	xmm6, xmm5, [ecx] 
+	{evex} vsm4key4	xmm6, xmm5, [ecx+2032]
+	{evex} vsm4key4	xmm6, xmm5, XMMWORD PTR [edx-2048]
+	vsm4rnds4	zmm6, zmm5, zmm4
+	{evex} vsm4rnds4	ymm6, ymm5, ymm4
+	{evex} vsm4rnds4	xmm6, xmm5, xmm4
+	vsm4rnds4	zmm6, zmm5, [esp+esi*8+0x10000000]
+	vsm4rnds4	zmm6, zmm5, ZMMWORD PTR [ecx]
+	vsm4rnds4	zmm6, zmm5, ZMMWORD PTR [ecx+8128]
+	vsm4rnds4	zmm6, zmm5, [edx-8192]
+	{evex} vsm4rnds4	ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000]
+	{evex} vsm4rnds4	ymm6, ymm5, [ecx]
+	{evex} vsm4rnds4	ymm6, ymm5, [ecx+4064]
+	{evex} vsm4rnds4	ymm6, ymm5, YMMWORD PTR [edx-4096]
+	{evex} vsm4rnds4	xmm6, xmm5, [esp+esi*8+0x10000000]
+	{evex} vsm4rnds4	xmm6, xmm5, XMMWORD PTR [ecx]
+	{evex} vsm4rnds4	xmm6, xmm5, XMMWORD PTR [ecx+2032]
+	{evex} vsm4rnds4	xmm6, xmm5, [edx-2048]
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f66c61eed11..4d41be2ce4b 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -535,6 +535,9 @@  if [gas_32_check] then {
     run_dump_test "avx10_2-512-miscs-intel"
     run_dump_test "avx10_2-256-miscs"
     run_dump_test "avx10_2-256-miscs-intel"
+    run_dump_test "avx10_2sm4"
+    run_dump_test "avx10_2sm4-intel"
+    run_list_test "avx10_2sm4-inval"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2sm4-intel.d b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-intel.d
new file mode 100644
index 00000000000..b5623ab037b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-intel.d
@@ -0,0 +1,41 @@ 
+#objdump: -dw -Mintel
+#name: x86_64 AVX10_2, SM4 insns (Intel disassembly)
+#source: x86-64-avx10_2sm4.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#pass
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*62 02 16 40 da f4\s+vsm4key4 zmm30,zmm29,zmm28
+\s*[a-f0-9]+:\s*62 02 16 20 da f4\s+vsm4key4 ymm30,ymm29,ymm28
+\s*[a-f0-9]+:\s*62 02 16 00 da f4\s+vsm4key4 xmm30,xmm29,xmm28
+\s*[a-f0-9]+:\s*62 22 16 40 da b4 f5 00 00 00 10\s+vsm4key4 zmm30,zmm29,ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 16 40 da 31\s+vsm4key4 zmm30,zmm29,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 16 40 da 71 7f\s+vsm4key4 zmm30,zmm29,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 62 16 40 da 72 80\s+vsm4key4 zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 22 16 20 da b4 f5 00 00 00 10\s+vsm4key4 ymm30,ymm29,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 16 20 da 31\s+vsm4key4 ymm30,ymm29,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 16 20 da 71 7f\s+vsm4key4 ymm30,ymm29,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 62 16 20 da 72 80\s+vsm4key4 ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 22 16 00 da b4 f5 00 00 00 10\s+vsm4key4 xmm30,xmm29,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 16 00 da 31\s+vsm4key4 xmm30,xmm29,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 16 00 da 71 7f\s+vsm4key4 xmm30,xmm29,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 62 16 00 da 72 80\s+vsm4key4 xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 02 17 40 da f4\s+vsm4rnds4 zmm30,zmm29,zmm28
+\s*[a-f0-9]+:\s*62 02 17 20 da f4\s+vsm4rnds4 ymm30,ymm29,ymm28
+\s*[a-f0-9]+:\s*62 02 17 00 da f4\s+vsm4rnds4 xmm30,xmm29,xmm28
+\s*[a-f0-9]+:\s*62 22 17 40 da b4 f5 00 00 00 10\s+vsm4rnds4 zmm30,zmm29,ZMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 17 40 da 31\s+vsm4rnds4 zmm30,zmm29,ZMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 17 40 da 71 7f\s+vsm4rnds4 zmm30,zmm29,ZMMWORD PTR \[rcx\+0x1fc0\]
+\s*[a-f0-9]+:\s*62 62 17 40 da 72 80\s+vsm4rnds4 zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
+\s*[a-f0-9]+:\s*62 22 17 20 da b4 f5 00 00 00 10\s+vsm4rnds4 ymm30,ymm29,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 17 20 da 31\s+vsm4rnds4 ymm30,ymm29,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 17 20 da 71 7f\s+vsm4rnds4 ymm30,ymm29,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 62 17 20 da 72 80\s+vsm4rnds4 ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 22 17 00 da b4 f5 00 00 00 10\s+vsm4rnds4 xmm30,xmm29,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 42 17 00 da 31\s+vsm4rnds4 xmm30,xmm29,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 62 17 00 da 71 7f\s+vsm4rnds4 xmm30,xmm29,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 62 17 00 da 72 80\s+vsm4rnds4 xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.l b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.l
new file mode 100644
index 00000000000..b5410c2770f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.l
@@ -0,0 +1,5 @@ 
+.* Assembler messages:
+.*:6: Error: operand size mismatch for `vsm4key4'
+.*:7: Error: operand size mismatch for `vsm4rnds4'
+.*:8: Error: no EVEX encoding for `vsm4key4'
+.*:9: Error: no EVEX encoding for `vsm4rnds4'
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.s b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.s
new file mode 100644
index 00000000000..8234412f3db
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2sm4-inval.s
@@ -0,0 +1,9 @@ 
+# Check Illegal 64bit SM4 instructions
+
+	.text
+	.arch .noavx10.2
+_start:
+	vsm4key4	%zmm28, %zmm29, %zmm30 
+	vsm4rnds4	%zmm28, %zmm29, %zmm30
+	vsm4key4	%ymm28, %ymm29, %ymm30 
+	vsm4rnds4	%xmm28, %xmm29, %xmm30
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2sm4.d b/gas/testsuite/gas/i386/x86-64-avx10_2sm4.d
new file mode 100644
index 00000000000..8319941f0fe
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2sm4.d
@@ -0,0 +1,39 @@ 
+#objdump: -dw
+#name: x86_64 AVX10_2, SM4 insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 02 16 40 da f4\s+vsm4key4 %zmm28,%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 02 16 20 da f4\s+vsm4key4 %ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 16 00 da f4\s+vsm4key4 %xmm28,%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 22 16 40 da b4 f5 00 00 00 10\s+vsm4key4 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 42 16 40 da 31\s+vsm4key4 \(%r9\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 62 16 40 da 71 7f\s+vsm4key4 0x1fc0\(%rcx\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 62 16 40 da 72 80\s+vsm4key4 -0x2000\(%rdx\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 22 16 20 da b4 f5 00 00 00 10\s+vsm4key4 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 42 16 20 da 31\s+vsm4key4 \(%r9\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 62 16 20 da 71 7f\s+vsm4key4 0xfe0\(%rcx\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 62 16 20 da 72 80\s+vsm4key4 -0x1000\(%rdx\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 22 16 00 da b4 f5 00 00 00 10\s+vsm4key4 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 42 16 00 da 31\s+vsm4key4 \(%r9\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 62 16 00 da 71 7f\s+vsm4key4 0x7f0\(%rcx\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 62 16 00 da 72 80\s+vsm4key4 -0x800\(%rdx\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 02 17 40 da f4\s+vsm4rnds4 %zmm28,%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 02 17 20 da f4\s+vsm4rnds4 %ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 17 00 da f4\s+vsm4rnds4 %xmm28,%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 22 17 40 da b4 f5 00 00 00 10\s+vsm4rnds4 0x10000000\(%rbp,%r14,8\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 42 17 40 da 31\s+vsm4rnds4 \(%r9\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 62 17 40 da 71 7f\s+vsm4rnds4 0x1fc0\(%rcx\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 62 17 40 da 72 80\s+vsm4rnds4 -0x2000\(%rdx\),%zmm29,%zmm30
+\s*[a-f0-9]+:\s*62 22 17 20 da b4 f5 00 00 00 10\s+vsm4rnds4 0x10000000\(%rbp,%r14,8\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 42 17 20 da 31\s+vsm4rnds4 \(%r9\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 62 17 20 da 71 7f\s+vsm4rnds4 0xfe0\(%rcx\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 62 17 20 da 72 80\s+vsm4rnds4 -0x1000\(%rdx\),%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 22 17 00 da b4 f5 00 00 00 10\s+vsm4rnds4 0x10000000\(%rbp,%r14,8\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 42 17 00 da 31\s+vsm4rnds4 \(%r9\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 62 17 00 da 71 7f\s+vsm4rnds4 0x7f0\(%rcx\),%xmm29,%xmm30
+\s*[a-f0-9]+:\s*62 62 17 00 da 72 80\s+vsm4rnds4 -0x800\(%rdx\),%xmm29,%xmm30
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2sm4.s b/gas/testsuite/gas/i386/x86-64-avx10_2sm4.s
new file mode 100644
index 00000000000..5859bc055b8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2sm4.s
@@ -0,0 +1,67 @@ 
+# Check 64bit SM4 instructions
+
+	.text
+_start:
+	vsm4key4	%zmm28, %zmm29, %zmm30
+	vsm4key4	%ymm28, %ymm29, %ymm30 
+	vsm4key4	%xmm28, %xmm29, %xmm30
+	vsm4key4	0x10000000(%rbp, %r14, 8), %zmm29, %zmm30
+	vsm4key4	(%r9), %zmm29, %zmm30
+	vsm4key4	8128(%rcx), %zmm29, %zmm30
+	vsm4key4	-8192(%rdx), %zmm29, %zmm30
+	vsm4key4	0x10000000(%rbp, %r14, 8), %ymm29, %ymm30
+	vsm4key4	(%r9), %ymm29, %ymm30
+	vsm4key4	4064(%rcx), %ymm29, %ymm30
+	vsm4key4	-4096(%rdx), %ymm29, %ymm30
+	vsm4key4	0x10000000(%rbp, %r14, 8), %xmm29, %xmm30
+	vsm4key4	(%r9), %xmm29, %xmm30
+	vsm4key4	2032(%rcx), %xmm29, %xmm30
+	vsm4key4	-2048(%rdx), %xmm29, %xmm30
+	vsm4rnds4	%zmm28, %zmm29, %zmm30
+	vsm4rnds4	%ymm28, %ymm29, %ymm30
+	vsm4rnds4	%xmm28, %xmm29, %xmm30
+	vsm4rnds4	0x10000000(%rbp, %r14, 8), %zmm29, %zmm30
+	vsm4rnds4	(%r9), %zmm29, %zmm30
+	vsm4rnds4	8128(%rcx), %zmm29, %zmm30
+	vsm4rnds4	-8192(%rdx), %zmm29, %zmm30
+	vsm4rnds4	0x10000000(%rbp, %r14, 8), %ymm29, %ymm30
+	vsm4rnds4	(%r9), %ymm29, %ymm30
+	vsm4rnds4	4064(%rcx), %ymm29, %ymm30
+	vsm4rnds4	-4096(%rdx), %ymm29, %ymm30
+	vsm4rnds4	0x10000000(%rbp, %r14, 8), %xmm29, %xmm30
+	vsm4rnds4	(%r9), %xmm29, %xmm30
+	vsm4rnds4	2032(%rcx), %xmm29, %xmm30
+	vsm4rnds4	-2048(%rdx), %xmm29, %xmm30
+
+_intel:
+	.intel_syntax noprefix
+	vsm4key4	zmm30, zmm29, zmm28
+	vsm4key4	ymm30, ymm29, ymm28
+	vsm4key4	xmm30, xmm29, xmm28
+	vsm4key4	zmm30, zmm29, [rbp+r14*8+0x10000000]
+	vsm4key4	zmm30, zmm29, ZMMWORD PTR [r9]
+	vsm4key4	zmm30, zmm29, [rcx+8128]
+	vsm4key4	zmm30, zmm29, ZMMWORD PTR [rdx-8192]
+	vsm4key4	ymm30, ymm29, [rbp+r14*8+0x10000000]
+	vsm4key4	ymm30, ymm29, YMMWORD PTR [r9]
+	vsm4key4	ymm30, ymm29, [rcx+4064]
+	vsm4key4	ymm30, ymm29, YMMWORD PTR [rdx-4096]
+	vsm4key4	xmm30, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000]
+	vsm4key4	xmm30, xmm29, [r9]
+	vsm4key4	xmm30, xmm29, [rcx+2032]
+	vsm4key4	xmm30, xmm29, XMMWORD PTR [rdx-2048]
+	vsm4rnds4	zmm30, zmm29, zmm28
+	vsm4rnds4	ymm30, ymm29, ymm28
+	vsm4rnds4	xmm30, xmm29, xmm28
+	vsm4rnds4	zmm30, zmm29, [rbp+r14*8+0x10000000]
+	vsm4rnds4	zmm30, zmm29, ZMMWORD PTR [r9]
+	vsm4rnds4	zmm30, zmm29, ZMMWORD PTR [rcx+8128]
+	vsm4rnds4	zmm30, zmm29, [rdx-8192]
+	vsm4rnds4	ymm30, ymm29, [rbp+r14*8+0x10000000]
+	vsm4rnds4	ymm30, ymm29, [r9]
+	vsm4rnds4	ymm30, ymm29, YMMWORD PTR [rcx+4064]
+	vsm4rnds4	ymm30, ymm29, YMMWORD PTR [rdx-4096]
+	vsm4rnds4	xmm30, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000]
+	vsm4rnds4	xmm30, xmm29, XMMWORD PTR [r9]
+	vsm4rnds4	xmm30, xmm29, [rcx+2032]
+	vsm4rnds4	xmm30, xmm29, [rdx-2048]
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index b7f5c56c842..44088b92919 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -534,6 +534,9 @@  run_dump_test "x86-64-amx-avx512-intel"
 run_dump_test "x86-64-amx-movrs"
 run_dump_test "x86-64-amx-movrs-intel"
 run_list_test "x86-64-amx-movrs-inval"
+run_dump_test "x86-64-avx10_2sm4"
+run_dump_test "x86-64-avx10_2sm4-intel"
+run_list_test "x86-64-avx10_2sm4-inval"
 run_dump_test "x86-64-clzero"
 run_dump_test "x86-64-mwaitx-bdver4"
 run_list_test "x86-64-mwaitx-reg"
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 368d00051e0..2794e292248 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -538,7 +538,7 @@  static const struct dis386 evex_table[][256] = {
     /* D8 */
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F38DA) },
     { Bad_Opcode },
     { "%XEvaesencY",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "%XEvaesenclastY", { XM, Vex, EXx }, PREFIX_DATA },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f74fb163109..f01c719e5de 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -4271,9 +4271,9 @@  static const struct dis386 prefix_table[][4] = {
   /* PREFIX_VEX_0F38DA_W_0 */
   {
     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
-    { "vsm4key4", { XM, Vex, EXx }, 0 },
+    { "%XEvsm4key4",	{ XM, Vex, EXx }, 0 },
     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
-    { "vsm4rnds4", { XM, Vex, EXx }, 0 },
+    { "%XEvsm4rnds4",	{ XM, Vex, EXx }, 0 },
   },
 
   /* PREFIX_VEX_0F38F2_L_0 */
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 62861520e64..84b057a1190 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -229,8 +229,6 @@  enum i386_cpu
   CpuUSER_MSR,
   /* Intel MSR_IMM Instructions support required.  */
   CpuMSR_IMM,
-  /* Intel AVX10.2 Instructions support required.  */
-  CpuAVX10_2,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -337,6 +335,8 @@  enum i386_cpu
   CpuAPX_F,
   /* Intel AMX-TRANSPOSE Instructions support required.  */
   CpuAMX_TRANSPOSE,
+  /* Intel AVX10.2 Instructions support required.  */
+  CpuAVX10_2,
   /* Not supported in the 64bit mode  */
   CpuNo64,
 
@@ -374,6 +374,7 @@  enum i386_cpu
 		   cpuavx512vl:1, \
 		   cpuapx_f:1, \
 		   cpuamx_transpose:1, \
+		   cpuavx10_2:1, \
       /* NOTE: This field needs to remain last. */ \
 		   cpuno64:1
 
@@ -496,7 +497,6 @@  typedef union i386_cpu_flags
       unsigned int cpulkgs:1;
       unsigned int cpuuser_msr:1;
       unsigned int cpumsr_imm:1;
-      unsigned int cpuavx10_2:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index c335f0347a3..75a4c4f672c 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2196,6 +2196,9 @@  vsm3msg2, 0x66da, SM3, Modrm|Space0F38|Vex128|Src1VVVV|VexW0|NoSuf, { RegXMM|Uns
 vsm4key4, 0xf3da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
 vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
 
+vsm4key4, 0xf3da, SM4&AVX10_2, Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vsm4rnds4, 0xf2da, SM4&AVX10_2, Modrm|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
 // SM4 instructions end.
 
 // VAES