[v3] LoongArch: Fix the infinite loop caused by calling undefweak symbol
Checks
Context |
Check |
Description |
linaro-tcwg-bot/tcwg_binutils_build--master-arm |
success
|
Build passed
|
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 |
success
|
Build passed
|
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 |
success
|
Test passed
|
linaro-tcwg-bot/tcwg_binutils_check--master-arm |
success
|
Test passed
|
Commit Message
The undefweak symbol value of non-default visibility is 0 and does
not use plt entry, and will not be relocated in the relocate_secion
function. As a result, an infinite loop is generated because
bl %plt(sym) => bl 0.
Fix this by converting the call into a jump address 0.
---
Changes in v3:
- The call instruction is not deleted but converted to jump address 0.
- Add b %plt(sym) => jirl $zero,$zero,0.
- Convert in relocate_section instead of relax_section.
Changes in v2:
- Pass @var{again} to loongarch_relax_call_undefweak to continue the
next relax.
v2: https://sourceware.org/pipermail/binutils/2024-November/137744.html
Changes in v1:
- Convert undefweak calls that do not use plt to nop or delete them.
v1: https://sourceware.org/pipermail/binutils/2024-November/137701.html
---
bfd/elfnn-loongarch.c | 39 +++++++++++++++++++
.../ld-loongarch-elf/call_undefweak.d | 26 +++++++++++++
.../ld-loongarch-elf/call_undefweak.s | 33 ++++++++++++++++
.../ld-loongarch-elf/ld-loongarch-elf.exp | 11 ++++++
4 files changed, 109 insertions(+)
create mode 100644 ld/testsuite/ld-loongarch-elf/call_undefweak.d
create mode 100644 ld/testsuite/ld-loongarch-elf/call_undefweak.s
Comments
Pushed to r15-5819.
在 2024/11/29 下午4:29, Lulu Cai 写道:
> The undefweak symbol value of non-default visibility is 0 and does
> not use plt entry, and will not be relocated in the relocate_secion
> function. As a result, an infinite loop is generated because
> bl %plt(sym) => bl 0.
>
> Fix this by converting the call into a jump address 0.
>
> ---
> Changes in v3:
> - The call instruction is not deleted but converted to jump address 0.
> - Add b %plt(sym) => jirl $zero,$zero,0.
> - Convert in relocate_section instead of relax_section.
>
> Changes in v2:
> - Pass @var{again} to loongarch_relax_call_undefweak to continue the
> next relax.
> v2: https://sourceware.org/pipermail/binutils/2024-November/137744.html
>
> Changes in v1:
> - Convert undefweak calls that do not use plt to nop or delete them.
> v1: https://sourceware.org/pipermail/binutils/2024-November/137701.html
> ---
> bfd/elfnn-loongarch.c | 39 +++++++++++++++++++
> .../ld-loongarch-elf/call_undefweak.d | 26 +++++++++++++
> .../ld-loongarch-elf/call_undefweak.s | 33 ++++++++++++++++
> .../ld-loongarch-elf/ld-loongarch-elf.exp | 11 ++++++
> 4 files changed, 109 insertions(+)
> create mode 100644 ld/testsuite/ld-loongarch-elf/call_undefweak.d
> create mode 100644 ld/testsuite/ld-loongarch-elf/call_undefweak.s
>
> diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
> index 8189a23a3a9..7451153270f 100644
> --- a/bfd/elfnn-loongarch.c
> +++ b/bfd/elfnn-loongarch.c
> @@ -222,6 +222,10 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec)
> || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \
> || (R_TYPE) == R_LARCH_TLS_LE64_HI12)
>
> +#define IS_CALL_RELOC(R_TYPE) \
> + ((R_TYPE) == R_LARCH_B26 \
> + ||(R_TYPE) == R_LARCH_CALL36)
> +
> /* If TLS GD/IE need dynamic relocations, INDX will be the dynamic indx,
> and set NEED_RELOC to true used in allocate_dynrelocs and
> loongarch_elf_relocate_section for TLS GD/IE. */
> @@ -4015,9 +4019,44 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
> case R_LARCH_B26:
> case R_LARCH_CALL36:
> unresolved_reloc = false;
> + bool via_plt =
> + plt != NULL && h != NULL && h->plt.offset != (bfd_vma) - 1;
> +
> if (is_undefweak)
> {
> relocation = 0;
> +
> + /* A call to an undefined weak symbol is converted to 0. */
> + if (!via_plt && IS_CALL_RELOC (r_type))
> + {
> + /* call36 fn1 => pcaddu18i $ra,0+jirl $ra,$zero,0
> + tail36 $t0,fn1 => pcaddi18i $t0,0+jirl $zero,$zero,0 */
> + if (R_LARCH_CALL36 == r_type)
> + {
> + uint32_t jirl = bfd_get (32, input_bfd,
> + contents + rel->r_offset + 4);
> + uint32_t rd = LARCH_GET_RD (jirl);
> + jirl = LARCH_OP_JIRL | rd;
> +
> + bfd_put (32, input_bfd, jirl,
> + contents + rel->r_offset + 4);
> + }
> + else
> + {
> + uint32_t b_bl = bfd_get (32, input_bfd,
> + contents + rel->r_offset);
> + /* b %plt(fn1) => jirl $zero,zero,0. */
> + if (LARCH_INSN_B (b_bl))
> + bfd_put (32, input_bfd, LARCH_OP_JIRL,
> + contents + rel->r_offset);
> + else
> + /* bl %plt(fn1) => jirl $ra,zero,0. */
> + bfd_put (32, input_bfd, LARCH_OP_JIRL | 0x1,
> + contents + rel->r_offset);
> + }
> + r = bfd_reloc_continue;
> + break;
> + }
> }
>
> if (resolved_local)
> diff --git a/ld/testsuite/ld-loongarch-elf/call_undefweak.d b/ld/testsuite/ld-loongarch-elf/call_undefweak.d
> new file mode 100644
> index 00000000000..4761651817c
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/call_undefweak.d
> @@ -0,0 +1,26 @@
> +#...
> +Disassembly of section \.plt:
> +#...
> +0+1200004d0 <fn2@plt>:
> + 1200004d0: 1c00010f pcaddu12i \$t3, 8
> + 1200004d4: 28ed01ef ld.d \$t3, \$t3, -1216
> + 1200004d8: 4c0001ed jirl \$t1, \$t3, 0
> + 1200004dc: 03400000 nop
> +
> +Disassembly of section \.text:
> +#...
> +0+120000668 <main>:
> + 120000668: 4c000000 jr \$zero
> + 12000066c: 53fe67ff b -412 # 1200004d0 <fn2@plt>
> + 120000670: 4c000001 jirl \$ra, \$zero, 0
> + 120000674: 57fe5fff bl -420 # 1200004d0 <fn2@plt>
> +
> +0+120000678 <medium_call_nop>:
> + 120000678: 1e000001 pcaddu18i \$ra, 0
> + 12000067c: 4c000001 jirl \$ra, \$zero, 0
> + 120000680: 1e000001 pcaddu18i \$ra, 0
> + 120000684: 4ffe5021 jirl \$ra, \$ra, -432
> + 120000688: 1e00000c pcaddu18i \$t0, 0
> + 12000068c: 4c000000 jr \$zero
> + 120000690: 1e00000c pcaddu18i \$t0, 0
> + 120000694: 4ffe4180 jirl \$zero, \$t0, -448
> diff --git a/ld/testsuite/ld-loongarch-elf/call_undefweak.s b/ld/testsuite/ld-loongarch-elf/call_undefweak.s
> new file mode 100644
> index 00000000000..cc1405f0625
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/call_undefweak.s
> @@ -0,0 +1,33 @@
> + .text
> + .align 2
> + .globl main
> + .type main, @function
> +main:
> + # undefweak symbol with .hidden and .protected
> + # do not need plt entry, Calls to these symbols
> + # are converted to jump to 0.
> +nornal_call_nop:
> + b %plt(fn1)
> + b %plt(fn2)
> +
> + bl %plt(fn1)
> + bl %plt(fn2)
> +
> + # Medium call.
> +medium_call_nop:
> + .option norelax
> + # call36
> + pcaddu18i $r1,%call36(fn1)
> + jirl $r1,$r1,0
> + pcaddu18i $r1,%call36(fn2)
> + jirl $r1,$r1,0
> + # tail36
> + pcaddu18i $r12,%call36(fn1)
> + jirl $r0,$r12,0
> + pcaddu18i $r12,%call36(fn2)
> + jirl $r0,$r12,0
> +
> + .weak fn1
> + .hidden fn1
> +
> + .weak fn2
> diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> index e1b038cb579..d7c2b311f2f 100644
> --- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
> @@ -143,6 +143,17 @@ if [istarget "loongarch64-*-*"] {
> "abs-global.out" \
> ] \
> ]
> +
> + run_cc_link_tests [list \
> + [list \
> + "call undefweak symbol" \
> + "" "" \
> + {call_undefweak.s} \
> + {{objdump {-d} call_undefweak.d}} \
> + "call_undefweak" \
> + ] \
> + ]
> +
> }
>
> if [istarget "loongarch64-*-*"] {
@@ -222,6 +222,10 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec)
|| (R_TYPE) == R_LARCH_TLS_LE64_LO20 \
|| (R_TYPE) == R_LARCH_TLS_LE64_HI12)
+#define IS_CALL_RELOC(R_TYPE) \
+ ((R_TYPE) == R_LARCH_B26 \
+ ||(R_TYPE) == R_LARCH_CALL36)
+
/* If TLS GD/IE need dynamic relocations, INDX will be the dynamic indx,
and set NEED_RELOC to true used in allocate_dynrelocs and
loongarch_elf_relocate_section for TLS GD/IE. */
@@ -4015,9 +4019,44 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
case R_LARCH_B26:
case R_LARCH_CALL36:
unresolved_reloc = false;
+ bool via_plt =
+ plt != NULL && h != NULL && h->plt.offset != (bfd_vma) - 1;
+
if (is_undefweak)
{
relocation = 0;
+
+ /* A call to an undefined weak symbol is converted to 0. */
+ if (!via_plt && IS_CALL_RELOC (r_type))
+ {
+ /* call36 fn1 => pcaddu18i $ra,0+jirl $ra,$zero,0
+ tail36 $t0,fn1 => pcaddi18i $t0,0+jirl $zero,$zero,0 */
+ if (R_LARCH_CALL36 == r_type)
+ {
+ uint32_t jirl = bfd_get (32, input_bfd,
+ contents + rel->r_offset + 4);
+ uint32_t rd = LARCH_GET_RD (jirl);
+ jirl = LARCH_OP_JIRL | rd;
+
+ bfd_put (32, input_bfd, jirl,
+ contents + rel->r_offset + 4);
+ }
+ else
+ {
+ uint32_t b_bl = bfd_get (32, input_bfd,
+ contents + rel->r_offset);
+ /* b %plt(fn1) => jirl $zero,zero,0. */
+ if (LARCH_INSN_B (b_bl))
+ bfd_put (32, input_bfd, LARCH_OP_JIRL,
+ contents + rel->r_offset);
+ else
+ /* bl %plt(fn1) => jirl $ra,zero,0. */
+ bfd_put (32, input_bfd, LARCH_OP_JIRL | 0x1,
+ contents + rel->r_offset);
+ }
+ r = bfd_reloc_continue;
+ break;
+ }
}
if (resolved_local)
new file mode 100644
@@ -0,0 +1,26 @@
+#...
+Disassembly of section \.plt:
+#...
+0+1200004d0 <fn2@plt>:
+ 1200004d0: 1c00010f pcaddu12i \$t3, 8
+ 1200004d4: 28ed01ef ld.d \$t3, \$t3, -1216
+ 1200004d8: 4c0001ed jirl \$t1, \$t3, 0
+ 1200004dc: 03400000 nop
+
+Disassembly of section \.text:
+#...
+0+120000668 <main>:
+ 120000668: 4c000000 jr \$zero
+ 12000066c: 53fe67ff b -412 # 1200004d0 <fn2@plt>
+ 120000670: 4c000001 jirl \$ra, \$zero, 0
+ 120000674: 57fe5fff bl -420 # 1200004d0 <fn2@plt>
+
+0+120000678 <medium_call_nop>:
+ 120000678: 1e000001 pcaddu18i \$ra, 0
+ 12000067c: 4c000001 jirl \$ra, \$zero, 0
+ 120000680: 1e000001 pcaddu18i \$ra, 0
+ 120000684: 4ffe5021 jirl \$ra, \$ra, -432
+ 120000688: 1e00000c pcaddu18i \$t0, 0
+ 12000068c: 4c000000 jr \$zero
+ 120000690: 1e00000c pcaddu18i \$t0, 0
+ 120000694: 4ffe4180 jirl \$zero, \$t0, -448
new file mode 100644
@@ -0,0 +1,33 @@
+ .text
+ .align 2
+ .globl main
+ .type main, @function
+main:
+ # undefweak symbol with .hidden and .protected
+ # do not need plt entry, Calls to these symbols
+ # are converted to jump to 0.
+nornal_call_nop:
+ b %plt(fn1)
+ b %plt(fn2)
+
+ bl %plt(fn1)
+ bl %plt(fn2)
+
+ # Medium call.
+medium_call_nop:
+ .option norelax
+ # call36
+ pcaddu18i $r1,%call36(fn1)
+ jirl $r1,$r1,0
+ pcaddu18i $r1,%call36(fn2)
+ jirl $r1,$r1,0
+ # tail36
+ pcaddu18i $r12,%call36(fn1)
+ jirl $r0,$r12,0
+ pcaddu18i $r12,%call36(fn2)
+ jirl $r0,$r12,0
+
+ .weak fn1
+ .hidden fn1
+
+ .weak fn2
@@ -143,6 +143,17 @@ if [istarget "loongarch64-*-*"] {
"abs-global.out" \
] \
]
+
+ run_cc_link_tests [list \
+ [list \
+ "call undefweak symbol" \
+ "" "" \
+ {call_undefweak.s} \
+ {{objdump {-d} call_undefweak.d}} \
+ "call_undefweak" \
+ ] \
+ ]
+
}
if [istarget "loongarch64-*-*"] {