diff mbox series

RISC-V: Add support for ssdbltrp and smdbltrp extension.

Message ID 20241128111013.10917-1-chendongyan@isrc.iscas.ac.cn
State New
Headers
Series RISC-V: Add support for ssdbltrp and smdbltrp extension. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
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Commit Message

chendongyan Nov. 28, 2024, 11:10 a.m. UTC 
  This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc

bfd/ChangeLog:

	* elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions.

gas/ChangeLog:

	* NEWS: Updated.
	* config/tc-riscv.c (enum riscv_csr_class):
	(riscv_csr_address): Add CSR classes for Ssdbltrp/Smdbltrp.
	* testsuite/gas/riscv/march-help.l: Updated.

---
 bfd/elfxx-riscv.c                    | 4 ++++
 gas/NEWS                             | 4 ++++
 gas/config/tc-riscv.c                | 8 ++++++++
 gas/testsuite/gas/riscv/march-help.l | 2 ++
 4 files changed, 18 insertions(+)

Comments

Jan Beulich Nov. 28, 2024, 11:46 a.m. UTC | #1 
On 28.11.2024 12:10, Dongyan Chen wrote:
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -320,6 +320,10 @@ Changes in 2.38:
>  
>  * Add support for the RISC-V svinval extension, version 1.0.
>  
> +* Add support for the RISC-V ssdbltrp extension, version 1.0.
> +
> +* Add support for the RISC-V smdbltrp extension, version 1.0.
> +
>  * Add support for the RISC-V hypervisor extension, as defined by Privileged
>    Specification 1.12.

Please move up to near the top of the file - you're not retrofitting this
to 2.38, after all.

> @@ -1149,6 +1151,12 @@ riscv_csr_address (const char *csr_name,
>        is_h_required = (csr_class == CSR_CLASS_SSTC_AND_H
>  		      || csr_class == CSR_CLASS_SSTC_AND_H_32);
>        extension = "sstc";
> +      break;
> +	case CSR_CLASS_SSDBLTRP:
> +      extension = "ssdbltrp";
> +      break;
> +	case CSR_CLASS_SMDBLTRP:
> +      extension = "smdbltrp";
>        break;

The case labels are mis-indented here; see ...

>      case CSR_CLASS_DEBUG:
>        break;

... ones adjacent.

Jan
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 45da83e6926..49b4d5ca4eb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1272,6 +1272,8 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sstvala", "+zicsr", check_implicit_always},
   {"sstvecd", "+zicsr", check_implicit_always},
   {"ssu64xl", "+zicsr", check_implicit_always},
+  {"ssdbltrp", "+zicsr", check_implicit_always},
+  {"smdbltrp", "+zicsr", check_implicit_always},
 
   {"svade", "+zicsr", check_implicit_always},
   {"svadu", "+zicsr", check_implicit_always},
@@ -1458,6 +1460,8 @@  static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sstvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstvecd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssu64xl",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssdbltrp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smdbltrp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svade",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svadu",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svbare",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index 23eda334ec6..38957fdd510 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -320,6 +320,10 @@  Changes in 2.38:
 
 * Add support for the RISC-V svinval extension, version 1.0.
 
+* Add support for the RISC-V ssdbltrp extension, version 1.0.
+
+* Add support for the RISC-V smdbltrp extension, version 1.0.
+
 * Add support for the RISC-V hypervisor extension, as defined by Privileged
   Specification 1.12.
 
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3fb7727c250..4cfb0c1e1ad 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -102,6 +102,8 @@  enum riscv_csr_class
   CSR_CLASS_SSTC_AND_H,		/* Sstc only (with H) */
   CSR_CLASS_SSTC_32,		/* Sstc RV32 only */
   CSR_CLASS_SSTC_AND_H_32,	/* Sstc RV32 only (with H) */
+  CSR_CLASS_SSDBLTRP,		/* Ssdbltrp only */
+  CSR_CLASS_SMDBLTRP,		/* Smdbltrp only */
   CSR_CLASS_XTHEADVECTOR,	/* xtheadvector only */
 };
 
@@ -1149,6 +1151,12 @@  riscv_csr_address (const char *csr_name,
       is_h_required = (csr_class == CSR_CLASS_SSTC_AND_H
 		      || csr_class == CSR_CLASS_SSTC_AND_H_32);
       extension = "sstc";
+      break;
+	case CSR_CLASS_SSDBLTRP:
+      extension = "ssdbltrp";
+      break;
+	case CSR_CLASS_SMDBLTRP:
+      extension = "smdbltrp";
       break;
     case CSR_CLASS_DEBUG:
       break;
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 71cccb77102..c3e51c0ca2b 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -127,6 +127,8 @@  All available -march extensions for RISC-V:
 	sstvala                                 1.0
 	sstvecd                                 1.0
 	ssu64xl                                 1.0
+	ssdbltrp                                1.0
+	smdbltrp                                1.0
 	svade                                   1.0
 	svadu                                   1.0
 	svbare                                  1.0