From patchwork Wed Nov 13 08:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haochen Jiang X-Patchwork-Id: 100952 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 904063858405 for ; Wed, 13 Nov 2024 08:47:05 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by sourceware.org (Postfix) with ESMTPS id 0F8333858C66 for ; Wed, 13 Nov 2024 08:44:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0F8333858C66 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0F8333858C66 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731487496; cv=none; b=jHQ2Q+ijSwkE+4JB1KdLrP61RoMeFnXp3uH0Hp759AqMyApPcS/i9bz02fZ9jFtagpALtxxHaQlaMfxmif/RDW3jAPa4RmRaumtYQjmP1n/MAzoB1Lt3hC1nD4Em4YjxfkLMC3GzJ6KALIqDLV0J6yKyg47vVH9GFIFZCFl418E= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731487496; c=relaxed/simple; bh=oziO1kTu5AnD7ilvJR23J0mg1yeRMXtJBVwXhIqqays=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=uyuIbCIDUmKuNyjkaNutVFlDf3Q5/RHv4YSbeacGV1Bj3xw9jMMS128i7LnCJoWp/u2jw0yxsTTwqZdQ/lYlqOWMca7n5WHcdPfsMfKge+DEYQmRgrJgFKhAeVcS/7MN65kib1tcHs0i32xPWyLe55/EkYSsCKozEJWxxAU17pg= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731487488; x=1763023488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oziO1kTu5AnD7ilvJR23J0mg1yeRMXtJBVwXhIqqays=; b=ZBPErj1JDncV6cBv2afXGpwEkQE8KpdzfpiVowRntXt981qSBTnhcecv a/777gYsRjaCz323EpzAmAeSmSX6P2utA4SKDs9wxysOMWCpZt55nzVRZ X7qkG3l3rQQoJqZ0EE4TzqLbOr19lTpibRlwnl4nkNJW0xFQREQCcFErn +fmlsibpVnlrjGLOQxHRhr5SiDrAdMG8Ggf/+Bfqar3EhAI6dcUC7+oB/ bCPJ7fH80mosI++aSiVkjm/sfpw4PPokvdg+wTEwzE+khGs4iWbdcEnpb PJ21ZAY5hvWCUpb5pBDiyCnQnUIEiI13QvEt89ftlQhsJcDzKAPWaE9u+ A==; X-CSE-ConnectionGUID: dwCJI9KhSj+bXcMPyc+fRQ== X-CSE-MsgGUID: Sd8nPdIYRQems4arjw2tMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11254"; a="31458913" X-IronPort-AV: E=Sophos;i="6.12,150,1728975600"; d="scan'208";a="31458913" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2024 00:44:46 -0800 X-CSE-ConnectionGUID: MD/bm7yTR7Wko2NXeRxC7Q== X-CSE-MsgGUID: xGIGuPuUQnaclB6wTXKLxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,150,1728975600"; d="scan'208";a="87545468" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by fmviesa007.fm.intel.com with ESMTP; 13 Nov 2024 00:44:44 -0800 From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@intel.com, "Hu, Lin1" Subject: [PATCH 4/6] Rename Opcode Space Name Evexmap5 to xVexmap5 Date: Wed, 13 Nov 2024 16:44:33 +0800 Message-Id: <20241113084435.1784546-5-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20241113084435.1784546-1-haochen.jiang@intel.com> References: <20241113084435.1784546-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: "Hu, Lin1" Nit: Currently this patch is based on all AVX10.2 instructions, if the AVX10.2 insts are checked in after this patch, I will remove those insts. gas/ChangeLog: * config/tc-i386.c (pte): Change xvexmap5 to map5. (md_assemble): Extend the opcode space scope of sse check. opcodes/ChangeLog: * i386-dis.c (vex_table): Add VEX_MAP5. (get_valid_i386): Ditto. * i386-gen.c (process_i386_opcode_modifier): Change SPACE(EVEXMAP5) to SPACE(xVEXMAP5). * i386-opc.h (SPACE_EVEXMAP5): Change to SPACE_xVEXMAP5. * i386-opc.tbl: Change EVexMap5 to xVexMap5. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 5 +- opcodes/i386-dis.c | 297 ++++++++++++++++++++++++++++++++++++- opcodes/i386-gen.c | 2 +- opcodes/i386-opc.h | 4 +- opcodes/i386-opc.tbl | 196 ++++++++++++------------ opcodes/i386-tbl.h | 344 +++++++++++++++++++++---------------------- 6 files changed, 572 insertions(+), 276 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 57c4285cc68..574d7946dad 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3650,7 +3650,7 @@ pte (insn_template *t) { static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; static const char *const opc_spc[] = { - NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, + NULL, "0f", "0f38", "0f3a", NULL, "xvexmap5", "evexmap6", NULL, "XOP08", "XOP09", "XOP0A", }; unsigned int j; @@ -4218,6 +4218,7 @@ build_vex_prefix (const insn_template *t) case SPACE_0F: case SPACE_0F38: case SPACE_0F3A: + case SPACE_xVEXMAP5: case SPACE_MAP7: i.vex.bytes[0] = 0xc4; break; @@ -7188,7 +7189,7 @@ i386_assemble (char *line) /* The opcode space check isn't strictly needed; it's there only to bypass the logic below when easily possible. */ && t->opcode_space >= SPACE_0F - && t->opcode_space <= SPACE_0F3A + && t->opcode_space <= SPACE_xVEXMAP5 && !is_cpu (&i.tm, CpuSSE4a) && !is_any_vex_encoding (t)) { diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 57f8246bf76..815e02a5d59 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1399,7 +1399,8 @@ enum VEX_0F = 0, VEX_0F38, VEX_0F3A, - VEX_MAP7, + VEX_MAP5, + VEX_MAP7 }; enum @@ -7050,6 +7051,297 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, + /* VEX_MAP5 */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, }; #include "i386-dis-evex.h" @@ -9157,6 +9449,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = VEX_0F3A; break; + case 0x5: + vex_table_index = VEX_MAP5; + break; case 0x7: vex_table_index = VEX_MAP7; break; diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 90a6be46950..6d2cdac6e4e 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1153,7 +1153,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F38), SPACE(0F3A), SPACE(EVEXMAP4), - SPACE(EVEXMAP5), + SPACE(xVEXMAP5), SPACE(EVEXMAP6), SPACE(MAP7), SPACE(XOP08), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 8d7879c8eb4..89a6396686a 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1009,7 +1009,7 @@ typedef struct insn_template 2: 0F38 opcode prefix / space. 3: 0F3A opcode prefix / space. 4: EVEXMAP4 opcode prefix / space. - 5: EVEXMAP5 opcode prefix / space. + 5: xVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. 7: MAP7 opcode prefix / space. 8: XOP 08 opcode space. @@ -1021,7 +1021,7 @@ typedef struct insn_template #define SPACE_0F38 2 #define SPACE_0F3A 3 #define SPACE_EVEXMAP4 4 -#define SPACE_EVEXMAP5 5 +#define SPACE_xVEXMAP5 5 #define SPACE_EVEXMAP6 6 #define SPACE_MAP7 7 #define SPACE_XOP08 8 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2a195c8bbb3..b24f255307e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -118,7 +118,7 @@ #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A #define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4|EVex128 -#define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 +#define xVexMap5 OpcodeSpace=SPACE_xVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 #define VexW0 VexW=VEXW0 @@ -1933,7 +1933,7 @@ vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Uns + h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::xVexMap5:EVexMap6:0::EVexLIG:VexW0:Word:Disp8MemShift=1> vp, 0x66 | 0x, , Modrm||Masking||Src1VVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vs, 0x66 | 1 | 0x, , Modrm||Masking||Src1VVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } @@ -3309,85 +3309,85 @@ vcmpph, 0xc2, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp vcmpsh, 0xf3c2/0x, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcvtdq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtudq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtdq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtudq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtqq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtuqq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtqq2ph, 0x5b, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtuqq2ph, 0xf27a, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtpd2ph, 0x665a, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtpd2ph, 0x665a, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtps2phx, 0x661d, AVX512_FP16&, Modrm||Masking|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtps2phx, 0x661d, AVX512_FP16&, Modrm||Masking|xVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|xVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|xVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking|xVexMap5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|xVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|xVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|xVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } vfpclassph, 0x66, AVX512_FP16&, Modrm||Masking|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8|Imm8S, |Word, RegMask } -vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } -vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } +vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|xVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } +vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|xVexMap5|NoSuf, { RegXMM, Reg32 } vrcpph, 0x664c, AVX512_FP16, Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } @@ -3484,9 +3484,9 @@ vcvt2ps2phx, 0x6667, AVX10_2, Modrm|Space0F38|Src1VVVV|VexW0|Masking|Broadcast|D + bf8s:74:xVexMap5, + + hf8:18:xVexMap5, + + hf8s:1b:xVexMap5> vcvtbiasph2, 0x, AVX10_2, Modrm||Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM } vcvtbiasph2, 0x, AVX10_2, Modrm||EVex512|Src1VVVV|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Word|Unspecified|BaseIndex, RegZMM, RegYMM } @@ -3495,11 +3495,11 @@ vcvtneph2, 0xf3, AVX10_2, Modrm|||VexW0 -vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vcvthf82ph, 0xf21e, AVX10_2, Modrm|xVexMap5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvthf82ph, 0xf21e, AVX10_2, Modrm|xVexMap5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vcvthf82ph, 0xf21e, AVX10_2, Modrm|xVexMap5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpbf16, 0x66, AVX10_2, Modrm|EVexMap5|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpbf16, 0x66, AVX10_2, Modrm|xVexMap5|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vnepbf16, 0x | 0x, AVX10_2, Modrm|EVexMap6|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -3515,44 +3515,44 @@ vreducenepbf16, 0xf256, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8Sh vrndscalenepbf16, 0xf208, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vrsqrtpbf16, 0x4e, AVX10_2, Modrm|EVexMap6|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vscalefnepbf16, 0x2c, AVX10_2, Modrm|EVexMap6|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vsqrtnepbf16, 0x6651, AVX10_2, Modrm|EVexMap5|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcomsbf16, 0x662f, AVX10_2, Modrm|EVexMap5|EVexLIG|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } - -vcvtnebf162ibs, 0xf269, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtnebf162iubs, 0xf26b, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttnebf162ibs, 0xf268, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttnebf162iubs, 0xf26a, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2ibs, 0x69, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2iubs, 0x6b, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2ibs, 0x68, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2iubs, 0x6a, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2ibs, 0x6669, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2iubs, 0x666b, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2ibs, 0x6668, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2iubs, 0x666a, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvttpd2dqs, 0x6d, AVX10_2, Modrm||EVexMap5|Masking|VexW1|Broadcast|CheckOperandSize|NoSuf|, { |Qword, } -vcvttpd2qqs, 0x666d, AVX10_2, Modrm|EVexMap5|Masking|VexW1|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttpd2udqs, 0x6c, AVX10_2, Modrm||EVexMap5|Masking|VexW1|Broadcast|CheckOperandSize|NoSuf|, { |Qword, } -vcvttpd2uqqs, 0x666c, AVX10_2, Modrm|EVexMap5|Masking|VexW1|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2dqs, 0x6d, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex128|EVexMap5|Masking|VexW0|Disp8MemShift=3|Broadcast|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex256|EVexMap5|Masking|VexW0|Disp8MemShift=4|Broadcast|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex512|EVexMap5|Masking|VexW0|Disp8MemShift=5|Broadcast|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2udqs, 0x6c, AVX10_2, Modrm|EVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex128|EVexMap5|Masking|VexW0|Disp8MemShift=3|Broadcast|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex256|EVexMap5|Masking|VexW0|Disp8MemShift=4|Broadcast|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex512|EVexMap5|Masking|VexW0|Disp8MemShift=5|Broadcast|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } - -vcvttsd2sis, 0xf26d, AVX10_2, Modrm|EVexLIG|EVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 } -vcvttsd2sis, 0xf26d, AVX10_2&x64, Modrm|EVexLIG|EVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 } -vcvttsd2usis, 0xf26c, AVX10_2, Modrm|EVexLIG|EVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 } -vcvttsd2usis, 0xf26c, AVX10_2&x64, Modrm|EVexLIG|EVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 } -vcvttss2sis, 0xf36d, AVX10_2, Modrm|EVexLIG|EVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 } -vcvttss2sis, 0xf36d, AVX10_2&x64, Modrm|EVexLIG|EVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 } -vcvttss2usis, 0xf36c, AVX10_2, Modrm|EVexLIG|EVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 } -vcvttss2usis, 0xf36c, AVX10_2&x64, Modrm|EVexLIG|EVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 } +vsqrtnepbf16, 0x6651, AVX10_2, Modrm|xVexMap5|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcomsbf16, 0x662f, AVX10_2, Modrm|xVexMap5|EVexLIG|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } + +vcvtnebf162ibs, 0xf269, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtnebf162iubs, 0xf26b, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttnebf162ibs, 0xf268, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttnebf162iubs, 0xf26a, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2ibs, 0x69, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2iubs, 0x6b, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2ibs, 0x68, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2iubs, 0x6a, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2ibs, 0x6669, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2iubs, 0x666b, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2ibs, 0x6668, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2iubs, 0x666a, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|DWord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvttpd2dqs, 0x6d, AVX10_2, Modrm||xVexMap5|Masking|VexW1|Broadcast|CheckOperandSize|NoSuf|, { |Qword, } +vcvttpd2qqs, 0x666d, AVX10_2, Modrm|xVexMap5|Masking|VexW1|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttpd2udqs, 0x6c, AVX10_2, Modrm||xVexMap5|Masking|VexW1|Broadcast|CheckOperandSize|NoSuf|, { |Qword, } +vcvttpd2uqqs, 0x666c, AVX10_2, Modrm|xVexMap5|Masking|VexW1|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2dqs, 0x6d, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex128|xVexMap5|Masking|VexW0|Disp8MemShift=3|Broadcast|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex256|xVexMap5|Masking|VexW0|Disp8MemShift=4|Broadcast|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2qqs, 0x666d, AVX10_2, Modrm|EVex512|xVexMap5|Masking|VexW0|Disp8MemShift=5|Broadcast|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2udqs, 0x6c, AVX10_2, Modrm|xVexMap5|Masking|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex128|xVexMap5|Masking|VexW0|Disp8MemShift=3|Broadcast|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex256|xVexMap5|Masking|VexW0|Disp8MemShift=4|Broadcast|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2uqqs, 0x666c, AVX10_2, Modrm|EVex512|xVexMap5|Masking|VexW0|Disp8MemShift=5|Broadcast|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } + +vcvttsd2sis, 0xf26d, AVX10_2, Modrm|EVexLIG|xVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 } +vcvttsd2sis, 0xf26d, AVX10_2&x64, Modrm|EVexLIG|xVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 } +vcvttsd2usis, 0xf26c, AVX10_2, Modrm|EVexLIG|xVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 } +vcvttsd2usis, 0xf26c, AVX10_2&x64, Modrm|EVexLIG|xVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 } +vcvttss2sis, 0xf36d, AVX10_2, Modrm|EVexLIG|xVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 } +vcvttss2sis, 0xf36d, AVX10_2&x64, Modrm|EVexLIG|xVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 } +vcvttss2usis, 0xf36c, AVX10_2, Modrm|EVexLIG|xVexMap5|VexW0|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 } +vcvttss2usis, 0xf36c, AVX10_2&x64, Modrm|EVexLIG|xVexMap5|VexW1|Disp8MemShift|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 } vminmaxnepbf16, 0xf252, AVX10_2, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Disp8ShiftVL|Broadcast|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vminmaxp, 0x52, AVX10_2, Modrm|Masking|Space0F3A||Broadcast|Src1VVVV|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -3560,7 +3560,7 @@ vminmaxs, 0x53, AVX10_2, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV| vmovd, 0xf37e, AVX10_2, Load|Modrm|EVex128|VexW0|Space0F|Disp8MemShift=2|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovd, 0x66d6, AVX10_2, Modrm|EVex128|VexW0|Space0F|Disp8MemShift=2|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM } -vmovw, 0xf36e, AVX10_2, D|Modrm|EVex128|VexW0|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovw, 0xf36e, AVX10_2, D|Modrm|EVex128|VexW0|xVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } vcomxs, 0x2f, AVX10_2, Modrm|EVexLIG||||NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } vucomxs, 0x2e, AVX10_2, Modrm|EVexLIG||||NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM }