From patchwork Thu Oct 31 11:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 99905 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9B9CF3857707 for ; Thu, 31 Oct 2024 11:36:51 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 46B7E385770B for ; Thu, 31 Oct 2024 11:35:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 46B7E385770B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 46B7E385770B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730374532; cv=none; b=Zsvl61tAVckyEGbGPrlfNSOrIQUV+1w/1jdn7dl/Ft7wYT3OinQh61KnBikZQxqr2q4n09jRBwWS4v4K1edrqte4+IgUvgGIYiDJgO7b+++iz6KGE27B5ZSEw5w92kVRUcpGj/rbd0oZmuCFNNPb//bHdxYHLwIuRp/SGdkxYrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730374532; c=relaxed/simple; bh=bWMWl1R3Z3zFN+RxWDx8wOx/dNN0QvViE4VpVRSaGxw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=fdqe/ZhjdtceaKG3Bos/0mMGCHlCvYtHTziGdnORSCl09k4LHg1OZge9mtXEBSu1I47lE4zLRU42VdORKSi5uZ3Dub1JBgKudjWJPN7xUlJgKL280jSuErg+5HdQCImuQI2Nnnuo4PLZ/LP+KxV2QzpQdYsZjHruBn+yV4Z+I28= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A19281063; Thu, 31 Oct 2024 04:35:53 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 086433F73B; Thu, 31 Oct 2024 04:35:22 -0700 (PDT) From: Andre Vieira To: binutils@sourceware.org Cc: richard.earnshaw@arm.com, Andre Vieira Subject: [PATCH 2/2] arm, objdump: print obsolote warning when 26-bit set i instructions Date: Thu, 31 Oct 2024 11:35:00 +0000 Message-Id: <20241031113500.3685068-3-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241031113500.3685068-1-andre.simoesdiasvieira@arm.com> References: <20241031113500.3685068-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Arm has obsoleted the 26-bit addressing mode. Diagnose this when disasembling these instructions by printing OBSOLETE. --- gas/testsuite/gas/arm/armv1.d | 8 +++--- gas/testsuite/gas/arm/inst.d | 32 +++++++++++----------- gas/testsuite/gas/arm/pinsn.d | 24 ---------------- gas/testsuite/gas/arm/pinsn.s | 16 ----------- gas/testsuite/gas/arm/wince_inst.d | 32 +++++++++++----------- opcodes/arm-dis.c | 44 +++++++++++++----------------- 6 files changed, 55 insertions(+), 101 deletions(-) delete mode 100644 gas/testsuite/gas/arm/pinsn.d delete mode 100644 gas/testsuite/gas/arm/pinsn.s diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 3ae310a2fb7..1e0df1e999d 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -30,16 +30,16 @@ Disassembly of section .text: 0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 0+50 <[^>]*> e1100000 ? tst r0, r0 0+54 <[^>]*> e1100000 ? tst r0, r0 -0+58 <[^>]*> e110f000 ? tstp r0, r0 +0+58 <[^>]*> e110f000 ? tstp r0, r0 @ p-variant is OBSOLETE 0+5c <[^>]*> e1300000 ? teq r0, r0 0+60 <[^>]*> e1300000 ? teq r0, r0 -0+64 <[^>]*> e130f000 ? teqp r0, r0 +0+64 <[^>]*> e130f000 ? teqp r0, r0 @ p-variant is OBSOLETE 0+68 <[^>]*> e1500000 ? cmp r0, r0 0+6c <[^>]*> e1500000 ? cmp r0, r0 -0+70 <[^>]*> e150f000 ? cmpp r0, r0 +0+70 <[^>]*> e150f000 ? cmpp r0, r0 @ p-variant is OBSOLETE 0+74 <[^>]*> e1700000 ? cmn r0, r0 0+78 <[^>]*> e1700000 ? cmn r0, r0 -0+7c <[^>]*> e170f000 ? cmnp r0, r0 +0+7c <[^>]*> e170f000 ? cmnp r0, r0 @ p-variant is OBSOLETE 0+80 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\) 0+84 <[^>]*> e1b00000 ? movs r0, r0 0+88 <[^>]*> e1e00000 ? mvn r0, r0 diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index 3fda9465193..78f4958d6eb 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -95,22 +95,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teqp r0, #10 @ p-variant is OBSOLETE +0+15c <[^>]*> e132f004 ? teqp r2, r4 @ p-variant is OBSOLETE +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+168 <[^>]*> e370f00a ? cmnp r0, #10 @ p-variant is OBSOLETE +0+16c <[^>]*> e172f004 ? cmnp r2, r4 @ p-variant is OBSOLETE +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+178 <[^>]*> e350f00a ? cmpp r0, #10 @ p-variant is OBSOLETE +0+17c <[^>]*> e152f004 ? cmpp r2, r4 @ p-variant is OBSOLETE +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+188 <[^>]*> e310f00a ? tstp r0, #10 @ p-variant is OBSOLETE +0+18c <[^>]*> e112f004 ? tstp r2, r4 @ p-variant is OBSOLETE +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 @ p-variant is OBSOLETE 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/pinsn.d b/gas/testsuite/gas/arm/pinsn.d deleted file mode 100644 index 792843e4cdd..00000000000 --- a/gas/testsuite/gas/arm/pinsn.d +++ /dev/null @@ -1,24 +0,0 @@ -# name: 26-bit teq/cmn/tst/cmp instructions -# objdump: -dr --prefix-addresses --show-raw-insn -marmv4 -# skip: *-*-pe *-*-wince - -.*: +file format .*arm.* - - -Disassembly of section .text: -0+000 <[^>]*> e330f00a ? teqp r0, #10 -0+004 <[^>]*> e132f004 ? teqp r2, r4 -0+008 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+00c <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+010 <[^>]*> e370f00a ? cmnp r0, #10 -0+014 <[^>]*> e172f004 ? cmnp r2, r4 -0+018 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+01c <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+020 <[^>]*> e350f00a ? cmpp r0, #10 -0+024 <[^>]*> e152f004 ? cmpp r2, r4 -0+028 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+02c <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+030 <[^>]*> e310f00a ? tstp r0, #10 -0+034 <[^>]*> e112f004 ? tstp r2, r4 -0+038 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+03c <[^>]*> e111f113 ? tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/pinsn.s b/gas/testsuite/gas/arm/pinsn.s deleted file mode 100644 index d0afc4655ac..00000000000 --- a/gas/testsuite/gas/arm/pinsn.s +++ /dev/null @@ -1,16 +0,0 @@ -teqp r0, #10 -teqp r2, r4 -teqp r5, r7, lsl #5 -teqp r1, r3, lsl r1 -cmnp r0, #10 -cmnp r2, r4 -cmnp r5, r7, lsl #5 -cmnp r1, r3, lsl r1 -cmpp r0, #10 -cmpp r2, r4 -cmpp r5, r7, lsl #5 -cmpp r1, r3, lsl r1 -tstp r0, #10 -tstp r2, r4 -tstp r5, r7, lsl #5 -tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index 390e4536ae6..4bbac43861d 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -97,22 +97,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teq r0, #10 @ -0+15c <[^>]*> e132f004 ? teq r2, r4 @ -0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ -0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ -0+168 <[^>]*> e370f00a ? cmn r0, #10 @ -0+16c <[^>]*> e172f004 ? cmn r2, r4 @ -0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ -0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ -0+178 <[^>]*> e350f00a ? cmp r0, #10 @ -0+17c <[^>]*> e152f004 ? cmp r2, r4 @ -0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ -0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ -0+188 <[^>]*> e310f00a ? tst r0, #10 @ -0+18c <[^>]*> e112f004 ? tst r2, r4 @ -0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ -0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ +0+158 <[^>]*> e330f00a ? teqp r0, #10 @ p-variant is OBSOLETE +0+15c <[^>]*> e132f004 ? teqp r2, r4 @ p-variant is OBSOLETE +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+168 <[^>]*> e370f00a ? cmnp r0, #10 @ p-variant is OBSOLETE +0+16c <[^>]*> e172f004 ? cmnp r2, r4 @ p-variant is OBSOLETE +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+178 <[^>]*> e350f00a ? cmpp r0, #10 @ p-variant is OBSOLETE +0+17c <[^>]*> e152f004 ? cmpp r2, r4 @ p-variant is OBSOLETE +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 @ p-variant is OBSOLETE +0+188 <[^>]*> e310f00a ? tstp r0, #10 @ p-variant is OBSOLETE +0+18c <[^>]*> e112f004 ? tstp r2, r4 @ p-variant is OBSOLETE +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 @ p-variant is OBSOLETE +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 @ p-variant is OBSOLETE 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2bcc1d2c828..be6d148c5fd 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3359,6 +3359,7 @@ static const struct mopcode32 mve_opcodes[] = %m print register mask for ldm/stm instruction %o print operand2 (immediate or register + shift) %p print 'p' iff bits 12-15 are 15 + %O print OBSOLETE if the 26-bit mode bit is set %t print 't' iff bit 21 set and bit 24 clear %B print arm BLX(1) destination %C print the PSR sub type. @@ -3968,32 +3969,32 @@ static const struct opcode32 arm_opcodes[] = 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, + 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, + 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, + 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o%O"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, @@ -10321,19 +10322,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'p': if ((given & 0x0000f000) == 0x0000f000) - { - arm_feature_set arm_ext_v6 = - ARM_FEATURE_CORE_LOW (ARM_EXT_V6); - - /* The p-variants of tst/cmp/cmn/teq are the pre-V6 - mechanism for setting PSR flag bits. They are - obsolete in V6 onwards. */ - if (! ARM_CPU_HAS_FEATURE (private_data->features, \ - arm_ext_v6)) - func (stream, dis_style_mnemonic, "p"); - else - is_unpredictable = true; - } + func (stream, dis_style_mnemonic, "p"); + break; + case 'O': + if ((given & 0x0000f000) == 0x0000f000) + func (stream, dis_style_text, + "\t@ p-variant is OBSOLETE"); break; case 't':