From patchwork Thu Oct 31 11:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 99904 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ACE603857400 for ; Thu, 31 Oct 2024 11:35:59 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id E031A3858CD9 for ; Thu, 31 Oct 2024 11:35:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E031A3858CD9 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E031A3858CD9 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730374525; cv=none; b=femntnqe9MY/QkgkjpdSUTZ/jkAq8Ty+pv37K8b5WWjy0TWo1zigHDLRh7RuOdNFIOfER5tqDlJRZMU6bmDli3VqvKxgXb4usp9hqc4dABpPGxI+0vkid6CacEPMSWPvqkSmRchS14xE4IrsZJbNhH1umsoDIlrESoTr7j+IW20= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730374525; c=relaxed/simple; bh=vD2VgLa4104sl9d2wBPNGynhqLpDPHE/u/K7S/WexI4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=TjgyOEdQZXMh21ikH1GZ4xGhf5RrF3V58EoCeDGcs8BN0QevAd9pVC9Yk7xP4bZho96X7FphjFVrZdVA0v6VlpffEAaW6KT9bYYZ/+J7pIjElZfgSOejh7O8WW9dg7hebxVpEt3mx+Bnyz3B4ySJlSBWdn23kgwcUUUUVoLpASY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 76101113E; Thu, 31 Oct 2024 04:35:50 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 002D53F73B; Thu, 31 Oct 2024 04:35:19 -0700 (PDT) From: Andre Vieira To: binutils@sourceware.org Cc: richard.earnshaw@arm.com, Andre Vieira Subject: [PATCH 1/2] arm, objdump: Make objdump use bfd's machine detection to drive disassembly Date: Thu, 31 Oct 2024 11:34:59 +0000 Message-Id: <20241031113500.3685068-2-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241031113500.3685068-1-andre.simoesdiasvieira@arm.com> References: <20241031113500.3685068-1-andre.simoesdiasvieira@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch disables, for any elf target, an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. This patch teaches the disassembler to detect such situations by looking for the combination of the bx encoding bits and a relocation, and if both are present it will disassemble it as a bx instead. This patch removes the unused and wrongfully defined ARM_ARCH_V8A_CRC, and defines and uses a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. This also patches up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested. --- gas/testsuite/gas/arm/inst.d | 32 +++++++++++++-------------- gas/testsuite/gas/arm/nops.d | 1 + gas/testsuite/gas/arm/unpredictable.d | 1 + include/opcode/arm.h | 4 ++-- opcodes/arm-dis.c | 14 +++++++++--- 5 files changed, 31 insertions(+), 21 deletions(-) diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index 6f642dbe97f..3fda9465193 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -95,22 +95,22 @@ Disassembly of section .text: 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teq r0, #10 @ -0+15c <[^>]*> e132f004 ? teq r2, r4 @ -0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ -0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ -0+168 <[^>]*> e370f00a ? cmn r0, #10 @ -0+16c <[^>]*> e172f004 ? cmn r2, r4 @ -0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ -0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ -0+178 <[^>]*> e350f00a ? cmp r0, #10 @ -0+17c <[^>]*> e152f004 ? cmp r2, r4 @ -0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ -0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ -0+188 <[^>]*> e310f00a ? tst r0, #10 @ -0+18c <[^>]*> e112f004 ? tst r2, r4 @ -0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ -0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ +0+158 <[^>]*> e330f00a ? teqp r0, #10 +0+15c <[^>]*> e132f004 ? teqp r2, r4 +0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmnp r0, #10 +0+16c <[^>]*> e172f004 ? cmnp r2, r4 +0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmpp r0, #10 +0+17c <[^>]*> e152f004 ? cmpp r2, r4 +0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tstp r0, #10 +0+18c <[^>]*> e112f004 ? tstp r2, r4 +0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 diff --git a/gas/testsuite/gas/arm/nops.d b/gas/testsuite/gas/arm/nops.d index bda0c307dce..0f5de019bbe 100644 --- a/gas/testsuite/gas/arm/nops.d +++ b/gas/testsuite/gas/arm/nops.d @@ -1,4 +1,5 @@ # name: NOP instructions +# as: -march=armv7-a # objdump: -dr --prefix-addresses --show-raw-insn # skip: *-*-pe *-*-wince diff --git a/gas/testsuite/gas/arm/unpredictable.d b/gas/testsuite/gas/arm/unpredictable.d index 0781c18377c..0d3c14b6234 100644 --- a/gas/testsuite/gas/arm/unpredictable.d +++ b/gas/testsuite/gas/arm/unpredictable.d @@ -1,4 +1,5 @@ # name: Upredictable Instructions +# as: -march=armv6 # objdump: -D --prefix-addresses --show-raw-insn .*: +file format .*arm.* diff --git a/include/opcode/arm.h b/include/opcode/arm.h index a89c215faff..de1fcd49adb 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -354,8 +354,6 @@ #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) -#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, \ - ARM_AEXT2_V8A | ARM_EXT2_CRC) #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A \ | ARM_EXT2_CRC, FPU_NEON_EXT_RDMA) #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A \ @@ -381,6 +379,8 @@ #define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \ ARM_AEXT2_V8M_MAIN_DSP) #define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R) +#define ARM_ARCH_V8R_CRC ARM_FEATURE_CORE (ARM_AEXT_V8R, \ + ARM_AEXT2_V8R | ARM_EXT2_CRC) #define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \ ARM_AEXT2_V8_1M_MAIN) #define ARM_ARCH_V9A ARM_FEATURE_ALL(ARM_AEXT_V8A, \ diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index d1d7ca30993..2bcc1d2c828 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -10050,7 +10050,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & insn->mask) != insn->value) continue; - if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) + if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features) + /* If we are dealing with a bx instruction and arvm4, with a + relocation, then it is likely this was assembled with --fix-v4bx + and thus intended as a mode changing instruction, so disassemble + it as such. */ + && (insn->value != 0x12fff10 + || info->mach != bfd_mach_arm_4 + || ((info->flags & INSN_HAS_RELOC) == 0))) continue; /* Special case: an instruction with all bits set in the condition field @@ -12292,7 +12299,7 @@ select_arm_features (unsigned long mach, ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); break; } - case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; + case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R_CRC); break; case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; case bfd_mach_arm_8_1M_MAIN: @@ -12358,7 +12365,8 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bool little) { static struct arm_private_data private; - if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) + if (info->flavour != bfd_target_elf_flavour + && (info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) /* If the user did not use the -m command line switch then default to disassembling all types of ARM instruction.