[v2] RISC-V: Update the doc to match ISA manual

  ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7),
and I realized that may something I typo at beginning when I write the patch
for `.insn` support...:P

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations

Changes for V2:

- Also update all other func* to funct*
---
 gas/doc/c-riscv.texi | 72 ++++++++++++++++++++++----------------------
 1 file changed, 36 insertions(+), 36 deletions(-)
  

Committed, thanks ;)

Nelson

On Tue, Oct 29, 2024 at 8:37 AM Kito Cheng <kito.cheng@sifive.com> wrote:

> ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7),
> and I realized that may something I typo at beginning when I write the
> patch
> for `.insn` support...:P
>
> [1]
> https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
>
> Changes for V2:
>
> - Also update all other func* to funct*
> ---
>  gas/doc/c-riscv.texi | 72 ++++++++++++++++++++++----------------------
>  1 file changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 5614e766988..c12109f6cef 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -442,11 +442,11 @@ instruction formats:
>  @multitable @columnfractions .15 .40
>  @item opcode7 @tab Unsigned immediate or opcode name for 7-bits opcode.
>  @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
> -@item func7 @tab Unsigned immediate for 7-bits function code.
> -@item func6 @tab Unsigned immediate for 6-bits function code.
> -@item func4 @tab Unsigned immediate for 4-bits function code.
> -@item func3 @tab Unsigned immediate for 3-bits function code.
> -@item func2 @tab Unsigned immediate for 2-bits function code.
> +@item funct7 @tab Unsigned immediate for 7-bits function code.
> +@item funct6 @tab Unsigned immediate for 6-bits function code.
> +@item funct4 @tab Unsigned immediate for 4-bits function code.
> +@item funct3 @tab Unsigned immediate for 3-bits function code.
> +@item funct2 @tab Unsigned immediate for 2-bits function code.
>  @item rd @tab Destination register number for operand x, can be GPR or
> FPR.
>  @item rd' @tab Destination register number for operand x,
>  only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
> @@ -554,45 +554,45 @@ The following table lists the RISC-V instruction
> formats that are available
>  with the @samp{.insn} pseudo directive:
>
>  @table @code
> -@item R type: .insn r opcode7, func3, func7, rd, rs1, rs2
> +@item R type: .insn r opcode7, funct3, funct7, rd, rs1, rs2
>  @verbatim
>  +-------+-----+-----+-------+----+---------+
> -| func7 | rs2 | rs1 | func3 | rd | opcode7 |
> +| funct7 | rs2 | rs1 | funct3 | rd | opcode7 |
>  +-------+-----+-----+-------+----+---------+
>  31      25    20    15      12   7        0
>  @end verbatim
>
> -@item R type with 4 register operands: .insn r opcode7, func3, func2, rd,
> rs1, rs2, rs3
> -@itemx R4 type: .insn r4 opcode7, func3, func2, rd, rs1, rs2, rs3
> +@item R type with 4 register operands: .insn r opcode7, funct3, funct2,
> rd, rs1, rs2, rs3
> +@itemx R4 type: .insn r4 opcode7, funct3, funct2, rd, rs1, rs2, rs3
>  @verbatim
>  +-----+-------+-----+-----+-------+----+---------+
> -| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode7 |
> +| rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode7 |
>  +-----+-------+-----+-----+-------+----+---------+
>  31    27      25    20    15      12   7         0
>  @end verbatim
>
> -@item I type: .insn i opcode7, func3, rd, rs1, simm12
> -@itemx I type: .insn i opcode7, func3, rd, simm12(rs1)
> +@item I type: .insn i opcode7, funct3, rd, rs1, simm12
> +@itemx I type: .insn i opcode7, funct3, rd, simm12(rs1)
>  @verbatim
>  +--------------+-----+-------+----+---------+
> -| simm12[11:0] | rs1 | func3 | rd | opcode7 |
> +| simm12[11:0] | rs1 | funct3 | rd | opcode7 |
>  +--------------+-----+-------+----+---------+
>  31             20    15      12   7         0
>  @end verbatim
>
> -@item S type: .insn s opcode7, func3, rs2, simm12(rs1)
> +@item S type: .insn s opcode7, funct3, rs2, simm12(rs1)
>  @verbatim
>  +--------------+-----+-----+-------+-------------+---------+
> -| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode7 |
> +| simm12[11:5] | rs2 | rs1 | funct3 | simm12[4:0] | opcode7 |
>  +--------------+-----+-----+-------+-------------+---------+
>  31             25    20    15      12            7         0
>  @end verbatim
>
> -@item B type: .insn s opcode7, func3, rs1, rs2, symbol
> -@itemx SB type: .insn sb opcode7, func3, rs1, rs2, symbol
> +@item B type: .insn s opcode7, funct3, rs1, rs2, symbol
> +@itemx SB type: .insn sb opcode7, funct3, rs1, rs2, symbol
>  @verbatim
>  +-----------------+-----+-----+-------+----------------+---------+
> -| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode7 |
> +| simm12[12|10:5] | rs2 | rs1 | funct3 | simm12[4:1|11] | opcode7 |
>  +-----------------+-----+-----+-------+----------------+---------+
>  31                25    20    15      12               7         0
>  @end verbatim
> @@ -614,74 +614,74 @@ with the @samp{.insn} pseudo directive:
>  31           30             21           20              12   7         0
>  @end verbatim
>
> -@item CR type: .insn cr opcode2, func4, rd, rs2
> +@item CR type: .insn cr opcode2, funct4, rd, rs2
>  @verbatim
>  +-------+--------+-----+---------+
> -| func4 | rd/rs1 | rs2 | opcode2 |
> +| funct4 | rd/rs1 | rs2 | opcode2 |
>  +-------+--------+-----+---------+
>  15      12       7     2        0
>  @end verbatim
>
> -@item CI type: .insn ci opcode2, func3, rd, simm6
> +@item CI type: .insn ci opcode2, funct3, rd, simm6
>  @verbatim
>  +-------+----------+--------+------------+---------+
> -| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
> +| funct3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
>  +-------+----------+--------+------------+---------+
>  15      13         12       7            2         0
>  @end verbatim
>
> -@item CIW type: .insn ciw opcode2, func3, rd', uimm8
> +@item CIW type: .insn ciw opcode2, funct3, rd', uimm8
>  @verbatim
>  +-------+------------+-----+---------+
> -| func3 | uimm8[7:0] | rd' | opcode2 |
> +| funct3 | uimm8[7:0] | rd' | opcode2 |
>  +-------+-------- ---+-----+---------+
>  15      13           5     2         0
>  @end verbatim
>
> -@item CSS type: .insn css opcode2, func3, rd, uimm6
> +@item CSS type: .insn css opcode2, funct3, rd, uimm6
>  @verbatim
>  +-------+------------+----+---------+
> -| func3 | uimm6[5:0] | rd | opcode2 |
> +| funct3 | uimm6[5:0] | rd | opcode2 |
>  +-------+------------+----+---------+
>  15      13           7    2         0
>  @end verbatim
>
> -@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
> +@item CL type: .insn cl opcode2, funct3, rd', uimm5(rs1')
>  @verbatim
>  +-------+------------+------+------------+------+---------+
> -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
> +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
>  +-------+------------+------+------------+------+---------+
>  15      13           10     7            5      2         0
>  @end verbatim
>
> -@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
> +@item CS type: .insn cs opcode2, funct3, rs2', uimm5(rs1')
>  @verbatim
>  +-------+------------+------+------------+------+---------+
> -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
> +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
>  +-------+------------+------+------------+------+---------+
>  15      13           10     7            5      2         0
>  @end verbatim
>
> -@item CA type: .insn ca opcode2, func6, func2, rd', rs2'
> +@item CA type: .insn ca opcode2, funct6, funct2, rd', rs2'
>  @verbatim
>  +-- ----+----------+-------+------+---------+
> -| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
> +| funct6 | rd'/rs1' | funct2 | rs2' | opcode2 |
>  +-------+----------+-------+------+---------+
>  15      10         7       5      2         0
>  @end verbatim
>
> -@item CB type: .insn cb opcode2, func3, rs1', symbol
> +@item CB type: .insn cb opcode2, funct3, rs1', symbol
>  @verbatim
>  +-------+--------------+------+------------------+---------+
> -| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
> +| funct3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
>  +-------+--------------+------+------------------+---------+
>  15      13             10     7                  2         0
>  @end verbatim
>
> -@item CJ type: .insn cj opcode2, func3, symbol
> +@item CJ type: .insn cj opcode2, funct3, symbol
>  @verbatim
>  +-------+-------------------------------+---------+
> -| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
> +| funct3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
>  +-------+-------------------------------+---------+
>  15      13                              2         0
>  @end verbatim
> --
> 2.34.1
>
>
  

On Okt 29 2024, Kito Cheng wrote:

>  @verbatim
>  +-----+-------+-----+-----+-------+----+---------+
> -| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode7 |
> +| rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode7 |
>  +-----+-------+-----+-----+-------+----+---------+
>  31    27      25    20    15      12   7         0
>  @end verbatim

>  @verbatim
>  +--------------+-----+-------+----+---------+
> -| simm12[11:0] | rs1 | func3 | rd | opcode7 |
> +| simm12[11:0] | rs1 | funct3 | rd | opcode7 |
>  +--------------+-----+-------+----+---------+
>  31             20    15      12   7         0
>  @end verbatim

>  @verbatim
>  +--------------+-----+-----+-------+-------------+---------+
> -| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode7 |
> +| simm12[11:5] | rs2 | rs1 | funct3 | simm12[4:0] | opcode7 |
>  +--------------+-----+-----+-------+-------------+---------+
>  31             25    20    15      12            7         0
>  @end verbatim

>  @verbatim
>  +-----------------+-----+-----+-------+----------------+---------+
> -| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode7 |
> +| simm12[12|10:5] | rs2 | rs1 | funct3 | simm12[4:1|11] | opcode7 |
>  +-----------------+-----+-----+-------+----------------+---------+
>  31                25    20    15      12               7         0
>  @end verbatim

>  @verbatim
>  +-------+--------+-----+---------+
> -| func4 | rd/rs1 | rs2 | opcode2 |
> +| funct4 | rd/rs1 | rs2 | opcode2 |
>  +-------+--------+-----+---------+
>  15      12       7     2        0
>  @end verbatim

>  @verbatim
>  +-------+----------+--------+------------+---------+
> -| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
> +| funct3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
>  +-------+----------+--------+------------+---------+
>  15      13         12       7            2         0
>  @end verbatim

>  @verbatim
>  +-------+------------+-----+---------+
> -| func3 | uimm8[7:0] | rd' | opcode2 |
> +| funct3 | uimm8[7:0] | rd' | opcode2 |
>  +-------+-------- ---+-----+---------+
>  15      13           5     2         0
>  @end verbatim

>  @verbatim
>  +-------+------------+----+---------+
> -| func3 | uimm6[5:0] | rd | opcode2 |
> +| funct3 | uimm6[5:0] | rd | opcode2 |
>  +-------+------------+----+---------+
>  15      13           7    2         0
>  @end verbatim

>  @verbatim
>  +-------+------------+------+------------+------+---------+
> -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
> +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
>  +-------+------------+------+------------+------+---------+
>  15      13           10     7            5      2         0
>  @end verbatim

>  @verbatim
>  +-------+------------+------+------------+------+---------+
> -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
> +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
>  +-------+------------+------+------------+------+---------+
>  15      13           10     7            5      2         0
>  @end verbatim

>  @verbatim
>  +-- ----+----------+-------+------+---------+
> -| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
> +| funct6 | rd'/rs1' | funct2 | rs2' | opcode2 |
>  +-------+----------+-------+------+---------+
>  15      10         7       5      2         0
>  @end verbatim

>  @verbatim
>  +-------+--------------+------+------------------+---------+
> -| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
> +| funct3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
>  +-------+--------------+------+------------------+---------+
>  15      13             10     7                  2         0
>  @end verbatim

>  @verbatim
>  +-------+-------------------------------+---------+
> -| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
> +| funct3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
>  +-------+-------------------------------+---------+
>  15      13                              2         0
>  @end verbatim

All tables are now misaligned.
  

Thanks, fixed.

Nelson

On Thu, Oct 31, 2024 at 12:19 AM Andreas Schwab <schwab@linux-m68k.org>
wrote:

> On Okt 29 2024, Kito Cheng wrote:
>
> >  @verbatim
> >  +-----+-------+-----+-----+-------+----+---------+
> > -| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode7 |
> > +| rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode7 |
> >  +-----+-------+-----+-----+-------+----+---------+
> >  31    27      25    20    15      12   7         0
> >  @end verbatim
>
> >  @verbatim
> >  +--------------+-----+-------+----+---------+
> > -| simm12[11:0] | rs1 | func3 | rd | opcode7 |
> > +| simm12[11:0] | rs1 | funct3 | rd | opcode7 |
> >  +--------------+-----+-------+----+---------+
> >  31             20    15      12   7         0
> >  @end verbatim
>
> >  @verbatim
> >  +--------------+-----+-----+-------+-------------+---------+
> > -| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode7 |
> > +| simm12[11:5] | rs2 | rs1 | funct3 | simm12[4:0] | opcode7 |
> >  +--------------+-----+-----+-------+-------------+---------+
> >  31             25    20    15      12            7         0
> >  @end verbatim
>
> >  @verbatim
> >  +-----------------+-----+-----+-------+----------------+---------+
> > -| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode7 |
> > +| simm12[12|10:5] | rs2 | rs1 | funct3 | simm12[4:1|11] | opcode7 |
> >  +-----------------+-----+-----+-------+----------------+---------+
> >  31                25    20    15      12               7         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+--------+-----+---------+
> > -| func4 | rd/rs1 | rs2 | opcode2 |
> > +| funct4 | rd/rs1 | rs2 | opcode2 |
> >  +-------+--------+-----+---------+
> >  15      12       7     2        0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+----------+--------+------------+---------+
> > -| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
> > +| funct3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
> >  +-------+----------+--------+------------+---------+
> >  15      13         12       7            2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+------------+-----+---------+
> > -| func3 | uimm8[7:0] | rd' | opcode2 |
> > +| funct3 | uimm8[7:0] | rd' | opcode2 |
> >  +-------+-------- ---+-----+---------+
> >  15      13           5     2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+------------+----+---------+
> > -| func3 | uimm6[5:0] | rd | opcode2 |
> > +| funct3 | uimm6[5:0] | rd | opcode2 |
> >  +-------+------------+----+---------+
> >  15      13           7    2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+------------+------+------------+------+---------+
> > -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
> > +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
> >  +-------+------------+------+------------+------+---------+
> >  15      13           10     7            5      2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+------------+------+------------+------+---------+
> > -| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
> > +| funct3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
> >  +-------+------------+------+------------+------+---------+
> >  15      13           10     7            5      2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-- ----+----------+-------+------+---------+
> > -| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
> > +| funct6 | rd'/rs1' | funct2 | rs2' | opcode2 |
> >  +-------+----------+-------+------+---------+
> >  15      10         7       5      2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+--------------+------+------------------+---------+
> > -| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
> > +| funct3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
> >  +-------+--------------+------+------------------+---------+
> >  15      13             10     7                  2         0
> >  @end verbatim
>
> >  @verbatim
> >  +-------+-------------------------------+---------+
> > -| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
> > +| funct3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
> >  +-------+-------------------------------+---------+
> >  15      13                              2         0
> >  @end verbatim
>
> All tables are now misaligned.
>
> --
> Andreas Schwab, schwab@linux-m68k.org
> GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
> "And now for something completely different."
>