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Tue, 15 Oct 2024 02:31:55 -0700 (PDT) Received: from sw05.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e77371099sm883007b3a.15.2024.10.15.02.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 02:31:54 -0700 (PDT) From: Hau Hsu To: binutils@sourceware.org, kito.cheng@gmail.com, hau.hsu@sifive.com Subject: [PATCH v1] RISC-V: Let fcvt.* recognize rounding mode != 0 Date: Tue, 15 Oct 2024 17:30:26 +0800 Message-Id: <20241015093025.1644019-1-hau.hsu@sifive.com> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org For those floating point convert instructions that convert from lower precisions to higher precisions, although the rounding mode has no effects, the spec doesn’t forbid them to be values other than zero. fcvt.q.l and fcvt.q.lu were fixed by 1d1595b. This patch also adds test for them. gas/ChangeLog: * testsuite/gas/riscv/fp-zfh-insns.d: New test for rounding mode. * testsuite/gas/riscv/fp-zfh-insns.s: Likewise. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Likewise. * testsuite/gas/riscv/zfbfmin.d: Likewise. * testsuite/gas/riscv/zfbfmin.s: Likewise. * testsuite/gas/riscv/zqinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Likewise. opcode/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcodes for fcvt.* with rounding mode. --- gas/testsuite/gas/riscv/fp-zfh-insns.d | 3 +++ gas/testsuite/gas/riscv/fp-zfh-insns.s | 3 +++ gas/testsuite/gas/riscv/zdinx.d | 2 ++ gas/testsuite/gas/riscv/zdinx.s | 2 ++ gas/testsuite/gas/riscv/zfbfmin.d | 1 + gas/testsuite/gas/riscv/zfbfmin.s | 1 + gas/testsuite/gas/riscv/zqinx.d | 6 ++++++ gas/testsuite/gas/riscv/zqinx.s | 6 ++++++ opcodes/riscv-opc.c | 11 +++++++++++ 9 files changed, 35 insertions(+) diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.d b/gas/testsuite/gas/riscv/fp-zfh-insns.d index 054e628ef66..476b40367fb 100644 --- a/gas/testsuite/gas/riscv/fp-zfh-insns.d +++ b/gas/testsuite/gas/riscv/fp-zfh-insns.d @@ -67,8 +67,11 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+e4058553[ ]+fmv.x.h[ ]+a0,fa1 [ ]+[0-9a-f]+:[ ]+f4058553[ ]+fmv.h.x[ ]+fa0,a1 [ ]+[0-9a-f]+:[ ]+40258553[ ]+fcvt.s.h[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+4025f553[ ]+fcvt.s.h[ ]+fa0,fa1,dyn [ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt.d.h[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+4225f553[ ]+fcvt.d.h[ ]+fa0,fa1,dyn [ ]+[0-9a-f]+:[ ]+46258553[ ]+fcvt.q.h[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+4625f553[ ]+fcvt.q.h[ ]+fa0,fa1,dyn [ ]+[0-9a-f]+:[ ]+4405f553[ ]+fcvt.h.s[ ]+fa0,fa1 [ ]+[0-9a-f]+:[ ]+44058553[ ]+fcvt.h.s[ ]+fa0,fa1,rne [ ]+[0-9a-f]+:[ ]+4415f553[ ]+fcvt.h.d[ ]+fa0,fa1 diff --git a/gas/testsuite/gas/riscv/fp-zfh-insns.s b/gas/testsuite/gas/riscv/fp-zfh-insns.s index 3619e72d252..14710bcf63d 100644 --- a/gas/testsuite/gas/riscv/fp-zfh-insns.s +++ b/gas/testsuite/gas/riscv/fp-zfh-insns.s @@ -53,8 +53,11 @@ fmv.h.x fa0, a1 fcvt.s.h fa0, fa1 + fcvt.s.h fa0, fa1, dyn fcvt.d.h fa0, fa1 + fcvt.d.h fa0, fa1, dyn fcvt.q.h fa0, fa1 + fcvt.q.h fa0, fa1, dyn fcvt.h.s fa0, fa1 fcvt.h.s fa0, fa1, rne fcvt.h.d fa0, fa1 diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d index 18d3fa3c41c..81f4d700ed0 100644 --- a/gas/testsuite/gas/riscv/zdinx.d +++ b/gas/testsuite/gas/riscv/zdinx.d @@ -35,7 +35,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+c2358553[ ]+fcvt.lu.d[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d205f553[ ]+fcvt.d.w[ ]+a0,a1,dyn [ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d215f553[ ]+fcvt.d.wu[ ]+a0,a1,dyn [ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1 [ ]+[0-9a-f]+:[ ]+d2258553[ ]+fcvt.d.l[ ]+a0,a1,rne [ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s index 3cff27e1458..c22db36f697 100644 --- a/gas/testsuite/gas/riscv/zdinx.s +++ b/gas/testsuite/gas/riscv/zdinx.s @@ -29,7 +29,9 @@ target: fcvt.lu.d a0, a1 fcvt.lu.d a0, a1, rne fcvt.d.w a0, a1 + fcvt.d.w a0, a1, dyn fcvt.d.wu a0, a1 + fcvt.d.wu a0, a1, dyn fcvt.d.l a0, a1 fcvt.d.l a0, a1, rne fcvt.d.lu a0, a1 diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d index 7cacc0bd684..88156909dc8 100644 --- a/gas/testsuite/gas/riscv/zfbfmin.d +++ b/gas/testsuite/gas/riscv/zfbfmin.d @@ -9,3 +9,4 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1 [ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne [ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1 +[ ]+[0-9a-f]+:[ ]+4065f553[ ]+fcvt.s.bf16[ ]+fa0,fa1,dyn diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s index c9a9af3e394..a586efd58f4 100644 --- a/gas/testsuite/gas/riscv/zfbfmin.s +++ b/gas/testsuite/gas/riscv/zfbfmin.s @@ -4,3 +4,4 @@ target: fcvt.bf16.s fa0, fa1, rne # fcvt.s.bf16 fcvt.s.bf16 fa0, fa1 + fcvt.s.bf16 fa0, fa1, dyn diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d index 28142654ca1..a2520684ba5 100644 --- a/gas/testsuite/gas/riscv/zqinx.d +++ b/gas/testsuite/gas/riscv/zqinx.d @@ -35,11 +35,17 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c6367553[ ]+fcvt.lu.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+c6360553[ ]+fcvt.lu.q[ ]+a0,a2,rne [ ]+[0-9a-f]+:[ ]+d6060553[ ]+fcvt.q.w[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6067553[ ]+fcvt.q.w[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+d6160553[ ]+fcvt.q.wu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6167553[ ]+fcvt.q.wu[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+d6260553[ ]+fcvt.q.l[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6267553[ ]+fcvt.q.l[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+d6360553[ ]+fcvt.q.lu[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+d6367553[ ]+fcvt.q.lu[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+46060553[ ]+fcvt.q.s[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46067553[ ]+fcvt.q.s[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+46160553[ ]+fcvt.q.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+46167553[ ]+fcvt.q.d[ ]+a0,a2,dyn [ ]+[0-9a-f]+:[ ]+40367553[ ]+fcvt.s.q[ ]+a0,a2 [ ]+[0-9a-f]+:[ ]+40360553[ ]+fcvt.s.q[ ]+a0,a2,rne [ ]+[0-9a-f]+:[ ]+42367553[ ]+fcvt.d.q[ ]+a0,a2 diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s index 84d045feb4d..d1070eb621a 100644 --- a/gas/testsuite/gas/riscv/zqinx.s +++ b/gas/testsuite/gas/riscv/zqinx.s @@ -29,12 +29,18 @@ target: fcvt.lu.q a0, a2 fcvt.lu.q a0, a2, rne fcvt.q.w a0, a2 + fcvt.q.w a0, a2, dyn fcvt.q.wu a0, a2 + fcvt.q.wu a0, a2, dyn fcvt.q.l a0, a2 + fcvt.q.l a0, a2, dyn fcvt.q.lu a0, a2 + fcvt.q.lu a0, a2, dyn fcvt.q.s a0, a2 + fcvt.q.s a0, a2, dyn fcvt.q.d a0, a2 + fcvt.q.d a0, a2, dyn fcvt.s.q a0, a2 fcvt.s.q a0, a2, rne fcvt.d.q a0, a2 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 8d5c574da6e..8ff65a1bd42 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -847,8 +847,11 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, +{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_S_H, MASK_FCVT_S_H, match_opcode, 0 }, {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, +{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S,m", MATCH_FCVT_D_H, MASK_FCVT_D_H, match_opcode, 0 }, {"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S,m", MATCH_FCVT_Q_H, MASK_FCVT_Q_H, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, @@ -874,6 +877,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, {"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, {"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16, match_opcode, 0 }, /* Single-precision floating-point instruction subset. */ {"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, @@ -993,8 +997,11 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, {"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, +{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_W, MASK_FCVT_D_W, match_opcode, 0 }, {"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_WU, MASK_FCVT_D_WU, match_opcode, 0 }, {"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_D_S, MASK_FCVT_D_S, match_opcode, 0 }, {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, {"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, @@ -1050,9 +1057,13 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, {"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, +{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_W, MASK_FCVT_Q_W, match_opcode, 0 }, {"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, +{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU, match_opcode, 0 }, {"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, +{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_Q_S, MASK_FCVT_Q_S, match_opcode, 0 }, {"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, +{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_Q_D, MASK_FCVT_Q_D, match_opcode, 0 }, {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, {"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },