diff mbox series

x86: Refine instruction check in x86_check_tls_relocation

Message ID 20241014110135.1166703-1-lili.cui@intel.com
State New
Headers
Series x86: Refine instruction check in x86_check_tls_relocation |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Cui, Lili Oct. 14, 2024, 11:01 a.m. UTC 
  This patch is to Refine instruction check in x86_check_tls_relocation.

Ok for master?

Thanks,
Lili.


gas/ChangeLog:

        * config/tc-i386.c
	(x86_check_tls_relocation): Refine instruction check.
---
 gas/config/tc-i386.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

Comments

Jan Beulich Oct. 14, 2024, 11:31 a.m. UTC | #1 
On 14.10.2024 13:01, Cui, Lili wrote:
> This patch is to Refine instruction check in x86_check_tls_relocation.
> 
> Ok for master?

Yes. And thanks.

Jan
diff mbox series

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index cdefde03717..cfab10d68b8 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6747,9 +6747,10 @@  x86_check_tls_relocation (enum bfd_reloc_code_real r_type)
 	  && i.tm.mnem_off != MN_add
 	  && i.tm.mnem_off != MN_mov)
 	return x86_tls_error_insn;
-      if (i.op[1].regs->reg_type.bitfield.class != Reg
-	  || i.op[0].regs->reg_type.bitfield.class
-	  || i.imm_operands)
+      if (i.imm_operands
+	  || i.disp_operands != 1
+	  || i.reg_operands != 1
+	  || i.types[1].bitfield.class != Reg)
 	return x86_tls_error_opcode;
       if (!i.base_reg)
 	return x86_tls_error_no_base_reg;
@@ -6769,9 +6770,10 @@  x86_check_tls_relocation (enum bfd_reloc_code_real r_type)
        */
       if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov)
 	return x86_tls_error_insn;
-      if (i.op[1].regs->reg_type.bitfield.class != Reg
-	  || i.op[0].regs->reg_type.bitfield.class
-	  || i.imm_operands)
+      if (i.imm_operands
+	  || i.disp_operands != 1
+	  || i.reg_operands != 1
+	  || i.types[1].bitfield.class != Reg)
 	return x86_tls_error_opcode;
       if (i.base_reg || i.index_reg)
 	return x86_tls_error_require_no_base_index_reg;
@@ -6789,10 +6791,9 @@  x86_check_tls_relocation (enum bfd_reloc_code_real r_type)
        */
       if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov)
 	return x86_tls_error_insn;
-      if (i.op[i.operands - 1].regs->reg_type.bitfield.class != Reg
-	  || (i.op[0].regs->reg_type.bitfield.class
-	      && i.tm.opcode_modifier.vexvvvv != VexVVVV_DST)
-	  || i.imm_operands)
+      if (i.imm_operands
+	  || i.disp_operands != 1
+	  || i.types[i.operands - 1].bitfield.class != Reg)
 	return x86_tls_error_opcode;
       if (!i.base_reg)
 	return x86_tls_error_no_base_reg;