[1/1] RISC-V: Add Xcvbi linker tests
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Commit Message
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
Nazareno Bruschi <nazareno.bruschi@embecosm.com>
Lin Sinan
ld/testsuite/ld-riscv-elf/ChangeLog:
* cv-bi-beqimm.d: New test.
* cv-bi-beqimm.s: New test.
* cv-bi-bneimm.d: New test.
* cv-bi-bneimm.s: New test.
* ld-riscv-elf.exp: Add Xcvbi ld tests.
---
ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d | 21 +++++++++++++++++++++
ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s | 11 +++++++++++
ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d | 21 +++++++++++++++++++++
ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s | 11 +++++++++++
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 ++
5 files changed, 66 insertions(+)
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
Comments
Although I have repeatedly replied, you have repeatedly ignored the comment
from the risc-v target maintainer and continued to send the patch that I
have already rejected for many times. Unfortunately, this is extremely
troubling to me, so I have no choice but to give the reason for rejecting
this patch for the last time - since the vendor core-v bi extension doesn't
add any new relocations, there is no reason to add any test case for them.
Nelson
On Thu, Sep 26, 2024 at 1:20 PM Mary Bennett <mary.bennett682@gmail.com>
wrote:
> Spec:
> https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
> Contributors:
> Mary Bennett <mary.bennett682@gmail.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
> Nazareno Bruschi <nazareno.bruschi@embecosm.com>
> Lin Sinan
>
> ld/testsuite/ld-riscv-elf/ChangeLog:
>
> * cv-bi-beqimm.d: New test.
> * cv-bi-beqimm.s: New test.
> * cv-bi-bneimm.d: New test.
> * cv-bi-bneimm.s: New test.
> * ld-riscv-elf.exp: Add Xcvbi ld tests.
> ---
> ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d | 21 +++++++++++++++++++++
> ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s | 11 +++++++++++
> ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d | 21 +++++++++++++++++++++
> ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s | 11 +++++++++++
> ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 ++
> 5 files changed, 66 insertions(+)
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
>
> diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
> b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
> new file mode 100644
> index 00000000000..b50d3846c1c
> --- /dev/null
> +++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
> @@ -0,0 +1,21 @@
> +#name: beqimm relocation
> +#source: cv-bi-beqimm.s
> +#as: -march=rv32i_xcvbi
> +#ld: -melf32lriscv
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +
> +Disassembly of section \.text:
> +
> +.* <func>:
> +.*:[[:space:]]+00008067[[:space:]]+ret
> +
> +.* <_start>:
>
> +.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
> +.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
> +
> +.* <L2>:
> +.*:[[:space:]]+00000013[[:space:]]+nop
> +#pass
> diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
> b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
> new file mode 100644
> index 00000000000..88a6b293e69
> --- /dev/null
> +++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
> @@ -0,0 +1,11 @@
> + .option nopic
> + .text
> + .align 1
> + .globl _start
> + .type _start, @function
> +
> +func: ret
> +_start:
> + cv.beqimm t0, -16, L2
> + call func
> +L2: nop
> diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
> b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
> new file mode 100644
> index 00000000000..52231a14b71
> --- /dev/null
> +++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
> @@ -0,0 +1,21 @@
> +#name: bneimm relocation
> +#source: cv-bi-bneimm.s
> +#as: -march=rv32i_xcvbi
> +#ld: -melf32lriscv
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +
> +Disassembly of section \.text:
> +
> +.* <func>:
> +.*:[[:space:]]+00008067[[:space:]]+ret
> +
> +.* <_start>:
>
> +.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
> +.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
> +
> +.* <L2>:
> +.*:[[:space:]]+00000013[[:space:]]+nop
> +#pass
> diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
> b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
> new file mode 100644
> index 00000000000..0f514f02e1b
> --- /dev/null
> +++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
> @@ -0,0 +1,11 @@
> + .option nopic
> + .text
> + .align 1
> + .globl _start
> + .type _start, @function
> +
> +func: ret
> +_start:
> + cv.bneimm t0, -16, L2
> + call func
> +L2: nop
> diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
> b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
> index 0ee20255551..0953cc51d4a 100644
> --- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
> +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
> @@ -176,6 +176,8 @@ if [istarget "riscv*-*-*"] {
> run_dump_test "uleb128"
> run_dump_test "pr31179"
> run_dump_test "pr31179-r"
> + run_dump_test "cv-bi-bneimm"
> + run_dump_test "cv-bi-beqimm"
> run_ld_link_tests [list \
> [list "Weak reference 32" "-T weakref.ld
> -m[riscv_choose_ilp32_emul]" "" \
> "-march=rv32i -mabi=ilp32" {weakref32.s} \
> --
> 2.43.0
>
>
new file mode 100644
@@ -0,0 +1,21 @@
+#name: beqimm relocation
+#source: cv-bi-beqimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
new file mode 100644
@@ -0,0 +1,11 @@
+ .option nopic
+ .text
+ .align 1
+ .globl _start
+ .type _start, @function
+
+func: ret
+_start:
+ cv.beqimm t0, -16, L2
+ call func
+L2: nop
new file mode 100644
@@ -0,0 +1,21 @@
+#name: bneimm relocation
+#source: cv-bi-bneimm.s
+#as: -march=rv32i_xcvbi
+#ld: -melf32lriscv
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+.* <func>:
+.*:[[:space:]]+00008067[[:space:]]+ret
+
+.* <_start>:
+.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+<L2>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func>
+
+.* <L2>:
+.*:[[:space:]]+00000013[[:space:]]+nop
+#pass
new file mode 100644
@@ -0,0 +1,11 @@
+ .option nopic
+ .text
+ .align 1
+ .globl _start
+ .type _start, @function
+
+func: ret
+_start:
+ cv.bneimm t0, -16, L2
+ call func
+L2: nop
@@ -176,6 +176,8 @@ if [istarget "riscv*-*-*"] {
run_dump_test "uleb128"
run_dump_test "pr31179"
run_dump_test "pr31179-r"
+ run_dump_test "cv-bi-bneimm"
+ run_dump_test "cv-bi-beqimm"
run_ld_link_tests [list \
[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
"-march=rv32i -mabi=ilp32" {weakref32.s} \