diff mbox series

[v5] Support ymm rounding control for Intel AVX10.2

Message ID 20240823083811.1087970-1-haochen.jiang@intel.com
State New
Headers
Series [v5] Support ymm rounding control for Intel AVX10.2 |

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Commit Message

Haochen Jiang Aug. 23, 2024, 8:38 a.m. UTC 
  Hi all,

This is the v5 patch for ymm rounding control support in AVX10.2, with
changes in v5 and patch descrption embedded following.

Tested on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

---

Changes in v5:

  - Fix the buggy check_VecOperands for ymm rounding.
  - Add more invalid testcases for conversion between different types.
  - Removed 64 bit invalid test since it is redundant.
  - Change u in build_evex_prefix from int to bool since it is actaully
    a bool.

---

In the patch, in order to support ymm rounding for AVX10.2, we derive
evex attribute for all cases instead of only for rc_none to encode U bit.
Also changed some bad_opcode return due to the share of U bit with APX_F.

Instead of adding new table entries, our current method is to alter the
CPUID part to add AVX10_2 explicitly for ymm rounding support, also
using similar way as APX_F for the CPUID combination, since ymm rounding
control is also somehow an instruction promotion, i.e.:

  #define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)

This will result in a bit increment for CPU_FLAGS_COMMON.

If we even do not want to make changes in table, it may end up with
spliting enconding_evex512 into two enmumerators to do so. But it will
be a seperate patch.

gas/ChangeLog:

	* config/tc-i386.c
	(cpu_arch): Add avx10_2.
	(cpu_flags_match): Handle AVX10_2.
	(build_evex_prefix): Handle U bit. Derive evex attribute
	for all cases.
	(check_VecOperands): Handle AVX10.2 and ymm roundings.
	* doc/c-i386.texi: Document .avx10.2.
	* testsuite/gas/i386/i386.exp: Run AVX10.2 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx10_2-rounding-intel.d: New test.
	* testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto.
	* testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto.
	* testsuite/gas/i386/avx10_2-rounding.d: Ditto.
	* testsuite/gas/i386/avx10_2-rounding.s: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (struct instr_info): Add U bit.
	(get_valid_dis386): Handle U bit.
	* i386-gen.c (isa_dependencies): Add AVX10.2.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX10_2): New.
	(i386_cpu_flags): Add cpuavx10_2.
	* i386-opc.tbl: Add ymm rounding to old entries. Also modify
	some old entries due to Exy and xyz iterator refactor.
	* i386-tbl.h: Regenerated.
---

Changes in v4:

  - Remove variable ymm and derive evex attribute under all
    circumstances.
  - Remove maybe_cpu check in check_VecOperands since it is actually
    useless. Also adjust the logic for rounding operands due to ymm
    varible removal since we do not need to derive that.
  - Add REX_X check back in get_valid_dis386 with new restrictions.
  - Add invalid testcases to check ymm rounding is disabled when
    AVX10.2 is off.

Changes in v3:

  - Remove the AVX10_2 wrapper for $z in table since it is not needed.
  - Use only maybe_cpu instead of is_cpu and maybe_cpu for ymm rounding
    checking since is_cpu is useless there.

Changes in v2:

  - Refactor the testcases to use .irp to eliminate redundancy.
  - Merge all table entry instead of adding new ones in table by using
    similar methods in APX_F.
  - Remove the NEWS change since it is pre-mature.
  - Relax the get_valid_dis386 bad opcode check to REX_B only. Previously,
    REX_X is also checked.
  - Fix the format for the confusing if/else.

---
 gas/config/tc-i386.c                          |   121 +-
 gas/doc/c-i386.texi                           |     6 +-
 .../gas/i386/avx10_2-rounding-intel.d         |   452 +
 .../gas/i386/avx10_2-rounding-inval.l         |    35 +
 .../gas/i386/avx10_2-rounding-inval.s         |    39 +
 gas/testsuite/gas/i386/avx10_2-rounding.d     |   450 +
 gas/testsuite/gas/i386/avx10_2-rounding.s     |   350 +
 gas/testsuite/gas/i386/i386.exp               |     3 +
 .../gas/i386/x86-64-avx10_2-rounding-intel.d  |   452 +
 .../gas/i386/x86-64-avx10_2-rounding.d        |   450 +
 .../gas/i386/x86-64-avx10_2-rounding.s        |   350 +
 gas/testsuite/gas/i386/x86-64.exp             |     2 +
 opcodes/i386-dis.c                            |    21 +-
 opcodes/i386-gen.c                            |     3 +
 opcodes/i386-init.h                           |   532 +-
 opcodes/i386-opc.h                            |     3 +
 opcodes/i386-opc.tbl                          |   150 +-
 opcodes/i386-tbl.h                            | 17654 ++++++++--------
 18 files changed, 11855 insertions(+), 9218 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/avx10_2-rounding-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx10_2-rounding-inval.l
 create mode 100644 gas/testsuite/gas/i386/avx10_2-rounding-inval.s
 create mode 100644 gas/testsuite/gas/i386/avx10_2-rounding.d
 create mode 100644 gas/testsuite/gas/i386/avx10_2-rounding.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2-rounding.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_2-rounding.s

Comments

Jan Beulich Aug. 26, 2024, 2:23 p.m. UTC | #1 
On 23.08.2024 10:38, Haochen Jiang wrote:
> In the patch, in order to support ymm rounding for AVX10.2, we derive
> evex attribute for all cases instead of only for rc_none to encode U bit.
> Also changed some bad_opcode return due to the share of U bit with APX_F.
> 
> Instead of adding new table entries, our current method is to alter the
> CPUID part to add AVX10_2 explicitly for ymm rounding support, also
> using similar way as APX_F for the CPUID combination, since ymm rounding
> control is also somehow an instruction promotion, i.e.:
> 
>   #define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)

The APX attribute was only added as necessary. Legacy insns being extended
to use REX2 encodings weren't altered. Similarly no AVX10.1 attributes were
added anywhere. IOW as before - please limit the opcode table changes to
just those places where new insn forms need adding (I expect that's going
to be a couple of convert insns with differring source/destination element
sizes).

> @@ -4278,10 +4281,63 @@ build_evex_prefix (void)
>    else
>      w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
>  
> +  if (i.tm.opcode_modifier.evex == EVEXDYN)
> +    {
> +      unsigned int op;
> +
> +      /* Determine vector length from the last multi-length vector operand.  */
> +      for (op = i.operands; op--;)
> +	if (i.tm.operand_types[op].bitfield.xmmword
> +	    + i.tm.operand_types[op].bitfield.ymmword
> +	    + i.tm.operand_types[op].bitfield.zmmword > 1)
> +	  {
> +	    if (i.types[op].bitfield.zmmword)
> +	      {
> +		i.tm.opcode_modifier.evex = EVEX512;
> +		break;
> +	      }
> +	    else if (i.types[op].bitfield.ymmword)
> +	      {
> +		i.tm.opcode_modifier.evex = EVEX256;
> +		break;
> +	      }
> +	    else if (i.types[op].bitfield.xmmword)
> +	      {
> +		i.tm.opcode_modifier.evex = EVEX128;
> +		break;
> +	      }
> +	    else if ((i.broadcast.type || i.broadcast.bytes)
> +		      && op == i.broadcast.operand)
> +	      {
> +		switch (get_broadcast_bytes (&i.tm, true))
> +		  {
> +		    case 64:
> +		      i.tm.opcode_modifier.evex = EVEX512;
> +		      break;
> +		    case 32:
> +		      i.tm.opcode_modifier.evex = EVEX256;
> +		      break;
> +		    case 16:
> +		      i.tm.opcode_modifier.evex = EVEX128;
> +		      break;
> +		    default:
> +		      abort ();
> +		  }
> +		break;
> +	      }
> +	  }
> +
> +      if (op >= MAX_OPERANDS)
> +	abort ();
> +    }
> +
> +  u = (i.rounding.type != rc_none
> +       && i.tm.opcode_modifier.evex == EVEX256) ? false : true;

What's the conditional operator for? This

  u = (i.rounding.type == rc_none
       || i.tm.opcode_modifier.evex != EVEX256);

is imo easier to follow.

> @@ -8024,13 +8029,19 @@ check_VecOperands (const insn_template *t)
>  	  return 1;
>  	}
>  
> -      /* Non-EVEX.{LIG,512} forms need to have a ZMM register as at least one
> -	 operand.  There's no need to check all operands, though: Either of the
> +      /* Non-EVEX.{LIG,512,256} forms need to have a ZMM or YMM register as at
> +         least one operand.  For YMM register or EVEX256, we will need AVX10.2

Nit: Indentation.

> +	 enabled.  There's no need to check all operands, though: Either of the
>  	 last two operands will be of the right size in all relevant templates.  */
>        if (t->opcode_modifier.evex != EVEXLIG
>  	  && t->opcode_modifier.evex != EVEX512
> +	  && (t->opcode_modifier.evex != EVEX256
> +	      || !cpu_arch_flags.bitfield.cpuavx10_2)
>  	  && !i.types[t->operands - 1].bitfield.zmmword
> -	  && !i.types[t->operands - 2].bitfield.zmmword)
> +	  && !i.types[t->operands - 2].bitfield.zmmword
> +	  && ((!i.types[t->operands - 1].bitfield.ymmword
> +	       && !i.types[t->operands - 2].bitfield.ymmword)
> +	      || !cpu_arch_flags.bitfield.cpuavx10_2))
>  	{
>  	  i.error = operand_size_mismatch;
>  	  return 1;

Since you now uniformly resolve t->opcode_modifier.evex when it's EVEXDYN,
do you actually still need the .zmmword / .ymmword checks? In the
calculation of the U bit you also rely on solely that attribute.

Jan
Haochen Jiang Aug. 27, 2024, 7:08 a.m. UTC | #2 
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, August 26, 2024 10:23 PM
> 
> On 23.08.2024 10:38, Haochen Jiang wrote:
> > In the patch, in order to support ymm rounding for AVX10.2, we derive
> > evex attribute for all cases instead of only for rc_none to encode U bit.
> > Also changed some bad_opcode return due to the share of U bit with APX_F.
> >
> > Instead of adding new table entries, our current method is to alter the
> > CPUID part to add AVX10_2 explicitly for ymm rounding support, also
> > using similar way as APX_F for the CPUID combination, since ymm rounding
> > control is also somehow an instruction promotion, i.e.:
> >
> >   #define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)
> 
> The APX attribute was only added as necessary. Legacy insns being extended
> to use REX2 encodings weren't altered. Similarly no AVX10.1 attributes were
> added anywhere. IOW as before - please limit the opcode table changes to
> just those places where new insn forms need adding (I expect that's going
> to be a couple of convert insns with differring source/destination element
> sizes).

AVX10.1 definitely doesn't need to be added everywhere since we are actually
implying AVX512.

However, AVX10.2 is different, it does contain new feature for ymm rounding.
I am not changing everywhere but only altering those related instruction CPUID,
which is the maybe optimal change for now since splitting encoding_evex512
will be a separate patch. All of them are needed, which are actually the new insn
forms since ymm rounding doesn't exist before AVX10.2.

> 
> > +  u = (i.rounding.type != rc_none
> > +       && i.tm.opcode_modifier.evex == EVEX256) ? false : true;
> 
> What's the conditional operator for? This
> 
>   u = (i.rounding.type == rc_none
>        || i.tm.opcode_modifier.evex != EVEX256);
> 
> is imo easier to follow.

It comes from original 0-1. Yes, it should be that after changing to bool.

> 
> > +	 enabled.  There's no need to check all operands, though: Either of the
> >  	 last two operands will be of the right size in all relevant templates.  */
> >        if (t->opcode_modifier.evex != EVEXLIG
> >  	  && t->opcode_modifier.evex != EVEX512
> > +	  && (t->opcode_modifier.evex != EVEX256
> > +	      || !cpu_arch_flags.bitfield.cpuavx10_2)
> >  	  && !i.types[t->operands - 1].bitfield.zmmword
> > -	  && !i.types[t->operands - 2].bitfield.zmmword)
> > +	  && !i.types[t->operands - 2].bitfield.zmmword
> > +	  && ((!i.types[t->operands - 1].bitfield.ymmword
> > +	       && !i.types[t->operands - 2].bitfield.ymmword)
> > +	      || !cpu_arch_flags.bitfield.cpuavx10_2))
> >  	{
> >  	  i.error = operand_size_mismatch;
> >  	  return 1;
> 
> Since you now uniformly resolve t->opcode_modifier.evex when it's EVEXDYN,
> do you actually still need the .zmmword / .ymmword checks? In the
> calculation of the U bit you also rely on solely that attribute.

check_VecOperands() comes earlier than build_evex_prefix(). At this point,
the evex for EVEXDYN has not been derived. We could and I have considered to
move that part into check_VecOperands(), but I suppose it might be out of
scope for this function.

Thx,
Haochen

> 
> Jan
Jan Beulich Aug. 27, 2024, 9:15 a.m. UTC | #3 
On 27.08.2024 09:08, Jiang, Haochen wrote:
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Monday, August 26, 2024 10:23 PM
>>
>> On 23.08.2024 10:38, Haochen Jiang wrote:
>>> In the patch, in order to support ymm rounding for AVX10.2, we derive
>>> evex attribute for all cases instead of only for rc_none to encode U bit.
>>> Also changed some bad_opcode return due to the share of U bit with APX_F.
>>>
>>> Instead of adding new table entries, our current method is to alter the
>>> CPUID part to add AVX10_2 explicitly for ymm rounding support, also
>>> using similar way as APX_F for the CPUID combination, since ymm rounding
>>> control is also somehow an instruction promotion, i.e.:
>>>
>>>   #define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)
>>
>> The APX attribute was only added as necessary. Legacy insns being extended
>> to use REX2 encodings weren't altered. Similarly no AVX10.1 attributes were
>> added anywhere. IOW as before - please limit the opcode table changes to
>> just those places where new insn forms need adding (I expect that's going
>> to be a couple of convert insns with differring source/destination element
>> sizes).
> 
> AVX10.1 definitely doesn't need to be added everywhere since we are actually
> implying AVX512.
> 
> However, AVX10.2 is different, it does contain new feature for ymm rounding.
> I am not changing everywhere but only altering those related instruction CPUID,
> which is the maybe optimal change for now since splitting encoding_evex512
> will be a separate patch. All of them are needed, which are actually the new insn
> forms since ymm rounding doesn't exist before AVX10.2.

Well, no, I'm afraid you're not going to convince me unless you come
forward with a hard technical requirement. Yet really it is the other
way around: Take

vcvtph2pd, 0x5a, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }

as example: What use is the AVX10_2 here? Even with AVX10.2 support
turned off, as long as AVX512VL is enabled the template is going to be
eligible for use. It is still solely the code you're adding to
check_VecOperands() which makes sure SAE cannot be used in such a case.

And for the case where one mentally considers AVX512VL disabled, the
resulting expression is actively misleading: AVX512_FP16&AVX10_2 is
wrong - AVX10_1 is sufficient for this insn to be used, as that (and
not AVX10.2) implies AVX512-FP16 (except of course for the possible
vector length restriction).

You need to touch this template, yes, but only to add SAE.

>>> +  u = (i.rounding.type != rc_none
>>> +       && i.tm.opcode_modifier.evex == EVEX256) ? false : true;
>>
>> What's the conditional operator for? This
>>
>>   u = (i.rounding.type == rc_none
>>        || i.tm.opcode_modifier.evex != EVEX256);
>>
>> is imo easier to follow.
> 
> It comes from original 0-1. Yes, it should be that after changing to bool.

Just to mention it: When u still wasn't bool, no conditional operator
should have needed using either. I know there are examples to the contrary
in existing code - I suppose all of them should be changed.

>>> +	 enabled.  There's no need to check all operands, though: Either of the
>>>  	 last two operands will be of the right size in all relevant templates.  */
>>>        if (t->opcode_modifier.evex != EVEXLIG
>>>  	  && t->opcode_modifier.evex != EVEX512
>>> +	  && (t->opcode_modifier.evex != EVEX256
>>> +	      || !cpu_arch_flags.bitfield.cpuavx10_2)
>>>  	  && !i.types[t->operands - 1].bitfield.zmmword
>>> -	  && !i.types[t->operands - 2].bitfield.zmmword)
>>> +	  && !i.types[t->operands - 2].bitfield.zmmword
>>> +	  && ((!i.types[t->operands - 1].bitfield.ymmword
>>> +	       && !i.types[t->operands - 2].bitfield.ymmword)
>>> +	      || !cpu_arch_flags.bitfield.cpuavx10_2))
>>>  	{
>>>  	  i.error = operand_size_mismatch;
>>>  	  return 1;
>>
>> Since you now uniformly resolve t->opcode_modifier.evex when it's EVEXDYN,
>> do you actually still need the .zmmword / .ymmword checks? In the
>> calculation of the U bit you also rely on solely that attribute.
> 
> check_VecOperands() comes earlier than build_evex_prefix(). At this point,
> the evex for EVEXDYN has not been derived. We could and I have considered to
> move that part into check_VecOperands(), but I suppose it might be out of
> scope for this function.

Oh, I'm sorry. The sequence of hunks misled me. You're right, and I agree
with not moving that logic.

Jan
Haochen Jiang Aug. 28, 2024, 2:58 a.m. UTC | #4 
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, August 27, 2024 5:15 PM
> 
> On 27.08.2024 09:08, Jiang, Haochen wrote:
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Monday, August 26, 2024 10:23 PM
> >>
> >> On 23.08.2024 10:38, Haochen Jiang wrote:
> >>> In the patch, in order to support ymm rounding for AVX10.2, we derive
> >>> evex attribute for all cases instead of only for rc_none to encode U bit.
> >>> Also changed some bad_opcode return due to the share of U bit with
> APX_F.
> >>>
> >>> Instead of adding new table entries, our current method is to alter the
> >>> CPUID part to add AVX10_2 explicitly for ymm rounding support, also
> >>> using similar way as APX_F for the CPUID combination, since ymm
> rounding
> >>> control is also somehow an instruction promotion, i.e.:
> >>>
> >>>   #define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)
> >>
> >> The APX attribute was only added as necessary. Legacy insns being
> extended
> >> to use REX2 encodings weren't altered. Similarly no AVX10.1 attributes
> were
> >> added anywhere. IOW as before - please limit the opcode table changes to
> >> just those places where new insn forms need adding (I expect that's going
> >> to be a couple of convert insns with differring source/destination element
> >> sizes).
> >
> > AVX10.1 definitely doesn't need to be added everywhere since we are
> actually
> > implying AVX512.
> >
> > However, AVX10.2 is different, it does contain new feature for ymm
> rounding.
> > I am not changing everywhere but only altering those related instruction
> CPUID,
> > which is the maybe optimal change for now since splitting encoding_evex512
> > will be a separate patch. All of them are needed, which are actually the new
> insn
> > forms since ymm rounding doesn't exist before AVX10.2.
> 
> Well, no, I'm afraid you're not going to convince me unless you come
> forward with a hard technical requirement. Yet really it is the other
> way around: Take
> 
> vcvtph2pd, 0x5a, AVX512_FP16&(AVX512VL|AVX10_2),
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3
> |NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
> 
> as example: What use is the AVX10_2 here? Even with AVX10.2 support
> turned off, as long as AVX512VL is enabled the template is going to be
> eligible for use. It is still solely the code you're adding to
> check_VecOperands() which makes sure SAE cannot be used in such a case.
> 
> And for the case where one mentally considers AVX512VL disabled, the
> resulting expression is actively misleading: AVX512_FP16&AVX10_2 is
> wrong - AVX10_1 is sufficient for this insn to be used, as that (and
> not AVX10.2) implies AVX512-FP16 (except of course for the possible
> vector length restriction).

Ah... I finally get your point. My mind was still stuck at the point when I
am checking is/maybe_cpu in check_VecOperands. They are removed for
now.

My little concern is that when I removed that, the reason is that we are
adding AVX10.2 in templates, which caused the check becoming redundant.
But we probably only need to care about CPUID bitfield. Then the check is
redundant even from the very beginning.

Let me have a try to adding SAE only to see if there is something unexpected
happen.

Thx,
Haochen

> 
> Jan
diff mbox series

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ad68ba9322d..c9f0125ce59 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1186,6 +1186,7 @@  static const arch_entry cpu_arch[] =
   VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
   SUBARCH (user_msr, USER_MSR, USER_MSR, false),
   SUBARCH (apx_f, APX_F, APX_F, false),
+  VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
 };
 
 #undef SUBARCH
@@ -1732,6 +1733,7 @@  _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
     case CpuAVX512F:  return a->bitfield.cpuavx512f;
     case CpuAVX512VL: return a->bitfield.cpuavx512vl;
     case CpuAPX_F:    return a->bitfield.cpuapx_f;
+    case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
     case Cpu64:       return a->bitfield.cpu64;
     case CpuNo64:     return a->bitfield.cpuno64;
     default:
@@ -4206,6 +4208,7 @@  static void
 build_evex_prefix (void)
 {
   unsigned int register_specifier, w;
+  bool u;
   rex_byte vrex_used = 0;
 
   /* Check register specifier.  */
@@ -4278,10 +4281,63 @@  build_evex_prefix (void)
   else
     w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
 
+  if (i.tm.opcode_modifier.evex == EVEXDYN)
+    {
+      unsigned int op;
+
+      /* Determine vector length from the last multi-length vector operand.  */
+      for (op = i.operands; op--;)
+	if (i.tm.operand_types[op].bitfield.xmmword
+	    + i.tm.operand_types[op].bitfield.ymmword
+	    + i.tm.operand_types[op].bitfield.zmmword > 1)
+	  {
+	    if (i.types[op].bitfield.zmmword)
+	      {
+		i.tm.opcode_modifier.evex = EVEX512;
+		break;
+	      }
+	    else if (i.types[op].bitfield.ymmword)
+	      {
+		i.tm.opcode_modifier.evex = EVEX256;
+		break;
+	      }
+	    else if (i.types[op].bitfield.xmmword)
+	      {
+		i.tm.opcode_modifier.evex = EVEX128;
+		break;
+	      }
+	    else if ((i.broadcast.type || i.broadcast.bytes)
+		      && op == i.broadcast.operand)
+	      {
+		switch (get_broadcast_bytes (&i.tm, true))
+		  {
+		    case 64:
+		      i.tm.opcode_modifier.evex = EVEX512;
+		      break;
+		    case 32:
+		      i.tm.opcode_modifier.evex = EVEX256;
+		      break;
+		    case 16:
+		      i.tm.opcode_modifier.evex = EVEX128;
+		      break;
+		    default:
+		      abort ();
+		  }
+		break;
+	      }
+	  }
+
+      if (op >= MAX_OPERANDS)
+	abort ();
+    }
+
+  u = (i.rounding.type != rc_none
+       && i.tm.opcode_modifier.evex == EVEX256) ? false : true;
+
   /* The third byte of the EVEX prefix.  */
   i.vex.bytes[2] = ((w << 7)
 		    | (register_specifier << 3)
-		    | 4 /* Encode the U bit.  */
+		    | (u << 2)
 		    | i.tm.opcode_modifier.opcodeprefix);
 
   /* The fourth byte of the EVEX prefix.  */
@@ -4295,57 +4351,6 @@  build_evex_prefix (void)
       /* Encode the vector length.  */
       unsigned int vec_length;
 
-      if (i.tm.opcode_modifier.evex == EVEXDYN)
-	{
-	  unsigned int op;
-
-	  /* Determine vector length from the last multi-length vector
-	     operand.  */
-	  for (op = i.operands; op--;)
-	    if (i.tm.operand_types[op].bitfield.xmmword
-		+ i.tm.operand_types[op].bitfield.ymmword
-		+ i.tm.operand_types[op].bitfield.zmmword > 1)
-	      {
-		if (i.types[op].bitfield.zmmword)
-		  {
-		    i.tm.opcode_modifier.evex = EVEX512;
-		    break;
-		  }
-		else if (i.types[op].bitfield.ymmword)
-		  {
-		    i.tm.opcode_modifier.evex = EVEX256;
-		    break;
-		  }
-		else if (i.types[op].bitfield.xmmword)
-		  {
-		    i.tm.opcode_modifier.evex = EVEX128;
-		    break;
-		  }
-		else if ((i.broadcast.type || i.broadcast.bytes)
-			 && op == i.broadcast.operand)
-		  {
-		    switch (get_broadcast_bytes (&i.tm, true))
-		      {
-			case 64:
-			  i.tm.opcode_modifier.evex = EVEX512;
-			  break;
-			case 32:
-			  i.tm.opcode_modifier.evex = EVEX256;
-			  break;
-			case 16:
-			  i.tm.opcode_modifier.evex = EVEX128;
-			  break;
-			default:
-			  abort ();
-		      }
-		    break;
-		  }
-	      }
-
-	  if (op >= MAX_OPERANDS)
-	    abort ();
-	}
-
       switch (i.tm.opcode_modifier.evex)
 	{
 	case EVEXLIG: /* LL' is ignored */
@@ -8024,13 +8029,19 @@  check_VecOperands (const insn_template *t)
 	  return 1;
 	}
 
-      /* Non-EVEX.{LIG,512} forms need to have a ZMM register as at least one
-	 operand.  There's no need to check all operands, though: Either of the
+      /* Non-EVEX.{LIG,512,256} forms need to have a ZMM or YMM register as at
+         least one operand.  For YMM register or EVEX256, we will need AVX10.2
+	 enabled.  There's no need to check all operands, though: Either of the
 	 last two operands will be of the right size in all relevant templates.  */
       if (t->opcode_modifier.evex != EVEXLIG
 	  && t->opcode_modifier.evex != EVEX512
+	  && (t->opcode_modifier.evex != EVEX256
+	      || !cpu_arch_flags.bitfield.cpuavx10_2)
 	  && !i.types[t->operands - 1].bitfield.zmmword
-	  && !i.types[t->operands - 2].bitfield.zmmword)
+	  && !i.types[t->operands - 2].bitfield.zmmword
+	  && ((!i.types[t->operands - 1].bitfield.ymmword
+	       && !i.types[t->operands - 2].bitfield.ymmword)
+	      || !cpu_arch_flags.bitfield.cpuavx10_2))
 	{
 	  i.error = operand_size_mismatch;
 	  return 1;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 36ba82506fe..a9e43560aea 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -219,6 +219,10 @@  accept various extension mnemonics.  For example,
 @code{avx10.1/128},
 @code{user_msr},
 @code{apx_f},
+@code{avx10.2},
+@code{avx10.2/512},
+@code{avx10.2/256},
+@code{avx10.2/128},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_fp16},
@@ -1679,7 +1683,7 @@  supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
 @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
 @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
-@item @samp{.pbndkb} @tab @samp{.user_msr}
+@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.avx10.2}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx10_2-rounding-intel.d b/gas/testsuite/gas/i386/avx10_2-rounding-intel.d
new file mode 100644
index 00000000000..09535f6a1f7
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2-rounding-intel.d
@@ -0,0 +1,452 @@ 
+#objdump: -dw -Mintel
+#name: i386 AVX10.2 insns rounding (Intel disassembly)
+#source: avx10_2-rounding.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+#...
+\s*a83:\s*62 f1 d1 18 c2 ec 7b\s+vcmppd k5,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f1 d1 1f c2 ec 7b\s+vcmppd k5\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f2 f9 18 42 f5\s+vgetexppd ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 f9 1f 42 f5\s+vgetexppd ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 f9 9f 42 f5\s+vgetexppd ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 51 f5\s+vsqrtpd ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 3f 51 f5\s+vsqrtpd ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 51 f5\s+vsqrtpd ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f3 50 18 c2 ec 7b\s+vcmpph k5,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 50 1f c2 ec 7b\s+vcmpph k5\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f6 79 18 42 f5\s+vgetexpph ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f6 79 1f 42 f5\s+vgetexpph ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f6 79 9f 42 f5\s+vgetexpph ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 51 f5\s+vsqrtph ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 3f 51 f5\s+vsqrtph ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 51 f5\s+vsqrtph ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 c2 ec 7b\s+vcmpps k5,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f1 50 1f c2 ec 7b\s+vcmpps k5\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f2 79 18 42 f5\s+vgetexpps ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 79 1f 42 f5\s+vgetexpps ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 79 9f 42 f5\s+vgetexpps ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 18 51 f5\s+vsqrtps ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 3f 51 f5\s+vsqrtps ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 51 f5\s+vsqrtps ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 58 f4\s+vaddpd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 3f 58 f4\s+vaddpd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 58 f4\s+vaddpd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 58 f4\s+vaddph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 3f 58 f4\s+vaddph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 58 f4\s+vaddph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 58 f4\s+vaddps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 3f 58 f4\s+vaddps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 58 f4\s+vaddps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5e f4\s+vdivpd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 3f 5e f4\s+vdivpd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 5e f4\s+vdivpd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5e f4\s+vdivph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 3f 5e f4\s+vdivph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 5e f4\s+vdivph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5e f4\s+vdivps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 3f 5e f4\s+vdivps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 5e f4\s+vdivps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 59 f4\s+vmulpd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 3f 59 f4\s+vmulpd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 59 f4\s+vmulpd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 59 f4\s+vmulph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 3f 59 f4\s+vmulph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 59 f4\s+vmulph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 59 f4\s+vmulps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 3f 59 f4\s+vmulps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 59 f4\s+vmulps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 2c f4\s+vscalefpd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 3f 2c f4\s+vscalefpd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff 2c f4\s+vscalefpd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 18 2c f4\s+vscalefph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 3f 2c f4\s+vscalefph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 ff 2c f4\s+vscalefph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 18 2c f4\s+vscalefps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 3f 2c f4\s+vscalefps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 ff 2c f4\s+vscalefps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5c f4\s+vsubpd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 3f 5c f4\s+vsubpd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 5c f4\s+vsubpd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5c f4\s+vsubph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 3f 5c f4\s+vsubph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 5c f4\s+vsubph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5c f4\s+vsubps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 3f 5c f4\s+vsubps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 5c f4\s+vsubps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5f f4\s+vmaxpd ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 1f 5f f4\s+vmaxpd ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 9f 5f f4\s+vmaxpd ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5f f4\s+vmaxph ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 1f 5f f4\s+vmaxph ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 9f 5f f4\s+vmaxph ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5f f4\s+vmaxps ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 1f 5f f4\s+vmaxps ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 9f 5f f4\s+vmaxps ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5d f4\s+vminpd ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 1f 5d f4\s+vminpd ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 d1 9f 5d f4\s+vminpd ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5d f4\s+vminph ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 1f 5d f4\s+vminph ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f5 50 9f 5d f4\s+vminph ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5d f4\s+vminps ymm6,ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 1f 5d f4\s+vminps ymm6\{k7\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f1 50 9f 5d f4\s+vminps ymm6\{k7\}\{z\},ymm5,ymm4\{sae\}
+\s*[a-f0-9]+:\s*62 f3 f9 18 26 f5 7b\s+vgetmantpd ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 1f 26 f5 7b\s+vgetmantpd ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 9f 26 f5 7b\s+vgetmantpd ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 18 26 f5 7b\s+vgetmantph ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 1f 26 f5 7b\s+vgetmantph ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 9f 26 f5 7b\s+vgetmantph ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 18 26 f5 7b\s+vgetmantps ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 1f 26 f5 7b\s+vgetmantps ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 9f 26 f5 7b\s+vgetmantps ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 18 56 f5 7b\s+vreducepd ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 1f 56 f5 7b\s+vreducepd ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 9f 56 f5 7b\s+vreducepd ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 18 56 f5 7b\s+vreduceph ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 1f 56 f5 7b\s+vreduceph ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 9f 56 f5 7b\s+vreduceph ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 18 56 f5 7b\s+vreduceps ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 1f 56 f5 7b\s+vreduceps ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 79 9f 56 f5 7b\s+vreduceps ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 18 09 f5 7b\s+vrndscalepd ymm6,ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 1f 09 f5 7b\s+vrndscalepd ymm6\{k7\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 f9 9f 09 f5 7b\s+vrndscalepd ymm6\{k7\}\{z\},ymm5\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 78 18 08 f5 7b\s+vrndscaleph ymm6,ymm5\{sae\},0x7b
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+\s*[a-f0-9]+:\s*62 f2 51 3f 9e f4\s+vfnmsub132ps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 ff 9e f4\s+vfnmsub132ps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 ae f4\s+vfnmsub213pd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 3f ae f4\s+vfnmsub213pd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff ae f4\s+vfnmsub213pd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 18 ae f4\s+vfnmsub213ph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 3f ae f4\s+vfnmsub213ph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 ff ae f4\s+vfnmsub213ph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 18 ae f4\s+vfnmsub213ps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 3f ae f4\s+vfnmsub213ps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 ff ae f4\s+vfnmsub213ps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 be f4\s+vfnmsub231pd ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 3f be f4\s+vfnmsub231pd ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff be f4\s+vfnmsub231pd ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 18 be f4\s+vfnmsub231ph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 3f be f4\s+vfnmsub231ph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 51 ff be f4\s+vfnmsub231ph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 18 be f4\s+vfnmsub231ps ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 3f be f4\s+vfnmsub231ps ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f2 51 ff be f4\s+vfnmsub231ps ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f3 d1 18 54 f4 7b\s+vfixupimmpd ymm6,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 d1 1f 54 f4 7b\s+vfixupimmpd ymm6\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 d1 9f 54 f4 7b\s+vfixupimmpd ymm6\{k7\}\{z\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 18 54 f4 7b\s+vfixupimmps ymm6,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 1f 54 f4 7b\s+vfixupimmps ymm6\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 9f 54 f4 7b\s+vfixupimmps ymm6\{k7\}\{z\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 d1 18 50 f4 7b\s+vrangepd ymm6,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 d1 1f 50 f4 7b\s+vrangepd ymm6\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 d1 9f 50 f4 7b\s+vrangepd ymm6\{k7\}\{z\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 18 50 f4 7b\s+vrangeps ymm6,ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 1f 50 f4 7b\s+vrangeps ymm6\{k7\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f3 51 9f 50 f4 7b\s+vrangeps ymm6\{k7\}\{z\},ymm5,ymm4\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 f6 53 18 56 f4\s+vfcmaddcph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 53 3f 56 f4\s+vfcmaddcph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 53 ff 56 f4\s+vfcmaddcph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 53 18 d6 f4\s+vfcmulcph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 53 3f d6 f4\s+vfcmulcph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 53 ff d6 f4\s+vfcmulcph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 18 56 f4\s+vfmaddcph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 3f 56 f4\s+vfmaddcph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 ff 56 f4\s+vfmaddcph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 18 d6 f4\s+vfmulcph ymm6,ymm5,ymm4\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 3f d6 f4\s+vfmulcph ymm6\{k7\},ymm5,ymm4\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f6 52 ff d6 f4\s+vfmulcph ymm6\{k7\}\{z\},ymm5,ymm4\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 5b f5\s+vcvtdq2ph xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 3f 5b f5\s+vcvtdq2ph xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 5b f5\s+vcvtdq2ph xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 18 5b f5\s+vcvtdq2ps ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 3f 5b f5\s+vcvtdq2ps ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 5b f5\s+vcvtdq2ps ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 7b 18 7a f5\s+vcvtudq2ph xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 7b 3f 7a f5\s+vcvtudq2ph xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 7b ff 7a f5\s+vcvtudq2ph xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 7b 18 7a f5\s+vcvtudq2ps ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 7b 3f 7a f5\s+vcvtudq2ps ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 7b ff 7a f5\s+vcvtudq2ps ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb 18 e6 f5\s+vcvtpd2dq xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb 3f e6 f5\s+vcvtpd2dq xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb ff e6 f5\s+vcvtpd2dq xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 f9 18 5a f5\s+vcvtpd2ph xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 f9 3f 5a f5\s+vcvtpd2ph xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 f9 ff 5a f5\s+vcvtpd2ph xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 5a f5\s+vcvtpd2ps xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 3f 5a f5\s+vcvtpd2ps xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 5a f5\s+vcvtpd2ps xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 79 f5\s+vcvtpd2udq xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 3f 79 f5\s+vcvtpd2udq xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 ff 79 f5\s+vcvtpd2udq xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 7b f5\s+vcvtpd2qq ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 3f 7b f5\s+vcvtpd2qq ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 7b f5\s+vcvtpd2qq ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 79 f5\s+vcvtpd2uqq ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 3f 79 f5\s+vcvtpd2uqq ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 79 f5\s+vcvtpd2uqq ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 5b f5\s+vcvtph2dq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 3f 5b f5\s+vcvtph2dq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 5b f5\s+vcvtph2dq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7b f5\s+vcvtph2qq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 3f 7b f5\s+vcvtph2qq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 7b f5\s+vcvtph2qq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 79 f5\s+vcvtph2udq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 3f 79 f5\s+vcvtph2udq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 79 f5\s+vcvtph2udq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 79 f5\s+vcvtph2uqq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 3f 79 f5\s+vcvtph2uqq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 79 f5\s+vcvtph2uqq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 5a f5\s+vcvtph2pd ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 1f 5a f5\s+vcvtph2pd ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 5a f5\s+vcvtph2pd ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 79 18 13 f5\s+vcvtph2ps ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 79 1f 13 f5\s+vcvtph2ps ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f2 79 9f 13 f5\s+vcvtph2ps ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f6 79 18 13 f5\s+vcvtph2psx ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f6 79 1f 13 f5\s+vcvtph2psx ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f6 79 9f 13 f5\s+vcvtph2psx ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 7d f5\s+vcvtph2uw ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 3f 7d f5\s+vcvtph2uw ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 7d f5\s+vcvtph2uw ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7d f5\s+vcvtph2w ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 3f 7d f5\s+vcvtph2w ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 7d f5\s+vcvtph2w ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 18 5b f5\s+vcvtps2dq ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 3f 5b f5\s+vcvtps2dq ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 5b f5\s+vcvtps2dq ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 18 79 f5\s+vcvtps2udq ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 3f 79 f5\s+vcvtps2udq ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 79 f5\s+vcvtps2udq ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 78 18 5a f5\s+vcvtps2pd ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 1f 5a f5\s+vcvtps2pd ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 9f 5a f5\s+vcvtps2pd ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 1d f5\s+vcvtps2phx xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 3f 1d f5\s+vcvtps2phx xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 1d f5\s+vcvtps2phx xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 18 7b f5\s+vcvtps2qq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 3f 7b f5\s+vcvtps2qq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 7b f5\s+vcvtps2qq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 18 79 f5\s+vcvtps2uqq ymm6,xmm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 3f 79 f5\s+vcvtps2uqq ymm6\{k7\},xmm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 79 f5\s+vcvtps2uqq ymm6\{k7\}\{z\},xmm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa 18 e6 f5\s+vcvtqq2pd ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa 3f e6 f5\s+vcvtqq2pd ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa ff e6 f5\s+vcvtqq2pd ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 f8 18 5b f5\s+vcvtqq2ph xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 f8 3f 5b f5\s+vcvtqq2ph xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 f8 ff 5b f5\s+vcvtqq2ph xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 5b f5\s+vcvtqq2ps xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 3f 5b f5\s+vcvtqq2ps xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 ff 5b f5\s+vcvtqq2ps xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa 18 7a f5\s+vcvtuqq2pd ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa 3f 7a f5\s+vcvtuqq2pd ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 fa ff 7a f5\s+vcvtuqq2pd ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 fb 18 7a f5\s+vcvtuqq2ph xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 fb 3f 7a f5\s+vcvtuqq2ph xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 fb ff 7a f5\s+vcvtuqq2ph xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb 18 7a f5\s+vcvtuqq2ps xmm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb 3f 7a f5\s+vcvtuqq2ps xmm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f1 fb ff 7a f5\s+vcvtuqq2ps xmm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 e6 f5\s+vcvttpd2dq xmm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 1f e6 f5\s+vcvttpd2dq xmm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f e6 f5\s+vcvttpd2dq xmm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 78 f5\s+vcvttpd2udq xmm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 1f 78 f5\s+vcvttpd2udq xmm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f8 9f 78 f5\s+vcvttpd2udq xmm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 7a f5\s+vcvttpd2qq ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 1f 7a f5\s+vcvttpd2qq ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f 7a f5\s+vcvttpd2qq ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 78 f5\s+vcvttpd2uqq ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 1f 78 f5\s+vcvttpd2uqq ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f 78 f5\s+vcvttpd2uqq ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 7a 18 5b f5\s+vcvttph2dq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 7a 1f 5b f5\s+vcvttph2dq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 7a 9f 5b f5\s+vcvttph2dq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7a f5\s+vcvttph2qq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 1f 7a f5\s+vcvttph2qq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 7a f5\s+vcvttph2qq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 78 f5\s+vcvttph2udq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 1f 78 f5\s+vcvttph2udq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 78 f5\s+vcvttph2udq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 78 f5\s+vcvttph2uqq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 1f 78 f5\s+vcvttph2uqq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 78 f5\s+vcvttph2uqq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 18 7c f5\s+vcvttph2uw ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 1f 7c f5\s+vcvttph2uw ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 7c f5\s+vcvttph2uw ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7c f5\s+vcvttph2w ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 1f 7c f5\s+vcvttph2w ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 7c f5\s+vcvttph2w ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 7a 18 5b f5\s+vcvttps2dq ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 7a 1f 5b f5\s+vcvttps2dq ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 7a 9f 5b f5\s+vcvttps2dq ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 18 78 f5\s+vcvttps2udq ymm6,ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 1f 78 f5\s+vcvttps2udq ymm6\{k7\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 78 9f 78 f5\s+vcvttps2udq ymm6\{k7\}\{z\},ymm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 18 7a f5\s+vcvttps2qq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 1f 7a f5\s+vcvttps2qq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 9f 7a f5\s+vcvttps2qq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 18 78 f5\s+vcvttps2uqq ymm6,xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 1f 78 f5\s+vcvttps2uqq ymm6\{k7\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f1 79 9f 78 f5\s+vcvttps2uqq ymm6\{k7\}\{z\},xmm5\{sae\}
+\s*[a-f0-9]+:\s*62 f5 7b 18 7d f5\s+vcvtuw2ph ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 7b 3f 7d f5\s+vcvtuw2ph ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 7b ff 7d f5\s+vcvtuw2ph ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+\s*[a-f0-9]+:\s*62 f5 7a 18 7d f5\s+vcvtw2ph ymm6,ymm5\{rn-sae\}
+\s*[a-f0-9]+:\s*62 f5 7a 3f 7d f5\s+vcvtw2ph ymm6\{k7\},ymm5\{rd-sae\}
+\s*[a-f0-9]+:\s*62 f5 7a ff 7d f5\s+vcvtw2ph ymm6\{k7\}\{z\},ymm5\{rz-sae\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx10_2-rounding-inval.l b/gas/testsuite/gas/i386/avx10_2-rounding-inval.l
new file mode 100644
index 00000000000..924353be13a
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2-rounding-inval.l
@@ -0,0 +1,35 @@ 
+.* Assembler messages:
+.*:6: Error: operand size mismatch for `vcmppd'
+.*:7: Error: operand size mismatch for `vgetexppd'
+.*:8: Error: operand size mismatch for `vsqrtpd'
+.*:9: Error: operand size mismatch for `vaddpd'
+.*:10: Error: operand size mismatch for `vmaxpd'
+.*:11: Error: operand size mismatch for `vreducepd'
+.*:12: Error: operand size mismatch for `vfmadd132pd'
+.*:13: Error: operand size mismatch for `vrangepd'
+.*:14: Error: operand size mismatch for `vfcmaddcph'
+.*:15: Error: operand size mismatch for `vcvtdq2ph'
+.*:16: Error: operand size mismatch for `vcvtdq2ps'
+.*:17: Error: operand size mismatch for `vcvtpd2dq'
+.*:18: Error: operand size mismatch for `vcvtpd2ph'
+.*:19: Error: operand size mismatch for `vcvtpd2qq'
+.*:20: Error: operand size mismatch for `vcvtph2dq'
+.*:21: Error: operand size mismatch for `vcvtph2qq'
+.*:22: Error: operand size mismatch for `vcvtph2pd'
+.*:23: Error: operand size mismatch for `vcvtph2ps'
+.*:24: Error: operand size mismatch for `vcvtph2uw'
+.*:25: Error: operand size mismatch for `vcvtps2dq'
+.*:26: Error: operand size mismatch for `vcvtps2pd'
+.*:27: Error: operand size mismatch for `vcvtps2phx'
+.*:28: Error: operand size mismatch for `vcvtps2qq'
+.*:29: Error: operand size mismatch for `vcvtqq2pd'
+.*:30: Error: operand size mismatch for `vcvtqq2ph'
+.*:31: Error: operand size mismatch for `vcvtqq2ps'
+.*:32: Error: operand size mismatch for `vcvttpd2dq'
+.*:33: Error: operand size mismatch for `vcvttpd2qq'
+.*:34: Error: operand size mismatch for `vcvttph2dq'
+.*:35: Error: operand size mismatch for `vcvttph2qq'
+.*:36: Error: operand size mismatch for `vcvttph2uw'
+.*:37: Error: operand size mismatch for `vcvttps2dq'
+.*:38: Error: operand size mismatch for `vcvttps2qq'
+.*:39: Error: operand size mismatch for `vcvtuw2ph'
diff --git a/gas/testsuite/gas/i386/avx10_2-rounding-inval.s b/gas/testsuite/gas/i386/avx10_2-rounding-inval.s
new file mode 100644
index 00000000000..fbde553c1ab
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2-rounding-inval.s
@@ -0,0 +1,39 @@ 
+# Check invalid AVX10.2 instructions
+
+	.text
+	.arch .noavx10.2
+_start:
+	vcmppd	$123, {sae}, %ymm4, %ymm5, %k5
+	vgetexppd	{sae}, %ymm5, %ymm6
+	vsqrtpd	{rn-sae}, %ymm5, %ymm6
+	vaddpd	{rn-sae}, %ymm4, %ymm5, %ymm6
+	vmaxpd	{sae}, %ymm4, %ymm5, %ymm6
+	vreducepd	$123, {sae}, %ymm5, %ymm6
+	vfmadd132pd	{rn-sae}, %ymm4, %ymm5, %ymm6
+	vrangepd	$123, {sae}, %ymm4, %ymm5, %ymm6
+	vfcmaddcph	{rn-sae}, %ymm4, %ymm5, %ymm6
+	vcvtdq2ph	{rn-sae}, %ymm5, %xmm6
+	vcvtdq2ps	{rn-sae}, %ymm5, %ymm6
+	vcvtpd2dq	{rn-sae}, %ymm5, %xmm6
+	vcvtpd2ph	{rn-sae}, %ymm5, %xmm6
+	vcvtpd2qq	{rn-sae}, %ymm5, %ymm6
+	vcvtph2dq	{rn-sae}, %xmm5, %ymm6
+	vcvtph2qq	{rn-sae}, %xmm5, %ymm6
+	vcvtph2pd	{sae}, %xmm5, %ymm6
+	vcvtph2ps	{sae}, %xmm5, %ymm6
+	vcvtph2uw	{rn-sae}, %ymm5, %ymm6
+	vcvtps2dq	{rn-sae}, %ymm5, %ymm6
+	vcvtps2pd	{sae}, %xmm5, %ymm6
+	vcvtps2phx	{rn-sae}, %ymm5, %xmm6
+	vcvtps2qq	{rn-sae}, %xmm5, %ymm6
+	vcvtqq2pd	{rn-sae}, %ymm5, %ymm6
+	vcvtqq2ph	{rn-sae}, %ymm5, %xmm6
+	vcvtqq2ps	{rn-sae}, %ymm5, %xmm6
+	vcvttpd2dq	{sae}, %ymm5, %xmm6
+	vcvttpd2qq	{sae}, %ymm5, %ymm6
+	vcvttph2dq	{sae}, %xmm5, %ymm6
+	vcvttph2qq	{sae}, %xmm5, %ymm6
+	vcvttph2uw	{sae}, %ymm5, %ymm6
+	vcvttps2dq	{sae}, %ymm5, %ymm6
+	vcvttps2qq	{sae}, %xmm5, %ymm6
+	vcvtuw2ph	{rn-sae}, %ymm5, %ymm6
diff --git a/gas/testsuite/gas/i386/avx10_2-rounding.d b/gas/testsuite/gas/i386/avx10_2-rounding.d
new file mode 100644
index 00000000000..30d4624770d
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2-rounding.d
@@ -0,0 +1,450 @@ 
+#objdump: -dw
+#name: i386 AVX10.2 rounding insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f1 d1 18 c2 ec 7b\s+vcmppd \$0x7b,\{sae\},%ymm4,%ymm5,%k5
+\s*[a-f0-9]+:\s*62 f1 d1 1f c2 ec 7b\s+vcmppd \$0x7b,\{sae\},%ymm4,%ymm5,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 f9 18 42 f5\s+vgetexppd \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 f9 1f 42 f5\s+vgetexppd \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 f9 9f 42 f5\s+vgetexppd \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 51 f5\s+vsqrtpd \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 f9 3f 51 f5\s+vsqrtpd \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 51 f5\s+vsqrtpd \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 50 18 c2 ec 7b\s+vcmpph \$0x7b,\{sae\},%ymm4,%ymm5,%k5
+\s*[a-f0-9]+:\s*62 f3 50 1f c2 ec 7b\s+vcmpph \$0x7b,\{sae\},%ymm4,%ymm5,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 79 18 42 f5\s+vgetexpph \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 79 1f 42 f5\s+vgetexpph \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 79 9f 42 f5\s+vgetexpph \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 51 f5\s+vsqrtph \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 3f 51 f5\s+vsqrtph \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 51 f5\s+vsqrtph \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 c2 ec 7b\s+vcmpps \$0x7b,\{sae\},%ymm4,%ymm5,%k5
+\s*[a-f0-9]+:\s*62 f1 50 1f c2 ec 7b\s+vcmpps \$0x7b,\{sae\},%ymm4,%ymm5,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 79 18 42 f5\s+vgetexpps \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 79 1f 42 f5\s+vgetexpps \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 79 9f 42 f5\s+vgetexpps \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 78 18 51 f5\s+vsqrtps \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 78 3f 51 f5\s+vsqrtps \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 51 f5\s+vsqrtps \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 58 f4\s+vaddpd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 3f 58 f4\s+vaddpd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 58 f4\s+vaddpd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 58 f4\s+vaddph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 3f 58 f4\s+vaddph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 58 f4\s+vaddph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 58 f4\s+vaddps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 3f 58 f4\s+vaddps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 58 f4\s+vaddps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5e f4\s+vdivpd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 3f 5e f4\s+vdivpd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 5e f4\s+vdivpd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5e f4\s+vdivph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 3f 5e f4\s+vdivph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 5e f4\s+vdivph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5e f4\s+vdivps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 3f 5e f4\s+vdivps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 5e f4\s+vdivps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 59 f4\s+vmulpd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 3f 59 f4\s+vmulpd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 59 f4\s+vmulpd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 59 f4\s+vmulph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 3f 59 f4\s+vmulph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 59 f4\s+vmulph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 59 f4\s+vmulps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 3f 59 f4\s+vmulps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 59 f4\s+vmulps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 2c f4\s+vscalefpd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 d1 3f 2c f4\s+vscalefpd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff 2c f4\s+vscalefpd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 51 18 2c f4\s+vscalefph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f 2c f4\s+vscalefph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff 2c f4\s+vscalefph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 2c f4\s+vscalefps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f 2c f4\s+vscalefps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff 2c f4\s+vscalefps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5c f4\s+vsubpd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 3f 5c f4\s+vsubpd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 ff 5c f4\s+vsubpd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5c f4\s+vsubph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 3f 5c f4\s+vsubph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 ff 5c f4\s+vsubph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5c f4\s+vsubps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 3f 5c f4\s+vsubps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 ff 5c f4\s+vsubps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5f f4\s+vmaxpd \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 1f 5f f4\s+vmaxpd \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 9f 5f f4\s+vmaxpd \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5f f4\s+vmaxph \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 1f 5f f4\s+vmaxph \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 9f 5f f4\s+vmaxph \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5f f4\s+vmaxps \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 1f 5f f4\s+vmaxps \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 9f 5f f4\s+vmaxps \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 d1 18 5d f4\s+vminpd \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 d1 1f 5d f4\s+vminpd \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 d1 9f 5d f4\s+vminpd \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 50 18 5d f4\s+vminph \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 50 1f 5d f4\s+vminph \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 50 9f 5d f4\s+vminph \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 50 18 5d f4\s+vminps \{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 50 1f 5d f4\s+vminps \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 50 9f 5d f4\s+vminps \{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 f9 18 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 f9 1f 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f3 f9 9f 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 78 18 26 f5 7b\s+vgetmantph \$0x7b,\{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 78 1f 26 f5 7b\s+vgetmantph \$0x7b,\{sae\},%ymm5,%ymm6\{%k7\}
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+\s*[a-f0-9]+:\s*62 f6 51 18 ac f4\s+vfnmadd213ph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f ac f4\s+vfnmadd213ph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff ac f4\s+vfnmadd213ph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 ac f4\s+vfnmadd213ps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f ac f4\s+vfnmadd213ps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff ac f4\s+vfnmadd213ps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 bc f4\s+vfnmadd231pd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 d1 3f bc f4\s+vfnmadd231pd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff bc f4\s+vfnmadd231pd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 51 18 bc f4\s+vfnmadd231ph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f bc f4\s+vfnmadd231ph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff bc f4\s+vfnmadd231ph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 bc f4\s+vfnmadd231ps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f bc f4\s+vfnmadd231ps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff bc f4\s+vfnmadd231ps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 9e f4\s+vfnmsub132pd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 d1 3f 9e f4\s+vfnmsub132pd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff 9e f4\s+vfnmsub132pd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 51 18 9e f4\s+vfnmsub132ph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f 9e f4\s+vfnmsub132ph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff 9e f4\s+vfnmsub132ph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 9e f4\s+vfnmsub132ps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f 9e f4\s+vfnmsub132ps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff 9e f4\s+vfnmsub132ps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 ae f4\s+vfnmsub213pd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 d1 3f ae f4\s+vfnmsub213pd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff ae f4\s+vfnmsub213pd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 51 18 ae f4\s+vfnmsub213ph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f ae f4\s+vfnmsub213ph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff ae f4\s+vfnmsub213ph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 ae f4\s+vfnmsub213ps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f ae f4\s+vfnmsub213ps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff ae f4\s+vfnmsub213ps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 d1 18 be f4\s+vfnmsub231pd \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 d1 3f be f4\s+vfnmsub231pd \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 d1 ff be f4\s+vfnmsub231pd \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 51 18 be f4\s+vfnmsub231ph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 51 3f be f4\s+vfnmsub231ph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 51 ff be f4\s+vfnmsub231ph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 51 18 be f4\s+vfnmsub231ps \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 51 3f be f4\s+vfnmsub231ps \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 51 ff be f4\s+vfnmsub231ps \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 d1 18 54 f4 7b\s+vfixupimmpd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 d1 1f 54 f4 7b\s+vfixupimmpd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f3 d1 9f 54 f4 7b\s+vfixupimmpd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 51 18 54 f4 7b\s+vfixupimmps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 51 1f 54 f4 7b\s+vfixupimmps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f3 51 9f 54 f4 7b\s+vfixupimmps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 d1 18 50 f4 7b\s+vrangepd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 d1 1f 50 f4 7b\s+vrangepd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f3 d1 9f 50 f4 7b\s+vrangepd \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f3 51 18 50 f4 7b\s+vrangeps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f3 51 1f 50 f4 7b\s+vrangeps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f3 51 9f 50 f4 7b\s+vrangeps \$0x7b,\{sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 53 18 56 f4\s+vfcmaddcph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 53 3f 56 f4\s+vfcmaddcph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 53 ff 56 f4\s+vfcmaddcph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 53 18 d6 f4\s+vfcmulcph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 53 3f d6 f4\s+vfcmulcph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 53 ff d6 f4\s+vfcmulcph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 52 18 56 f4\s+vfmaddcph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 52 3f 56 f4\s+vfmaddcph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 52 ff 56 f4\s+vfmaddcph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 52 18 d6 f4\s+vfmulcph \{rn-sae\},%ymm4,%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 52 3f d6 f4\s+vfmulcph \{rd-sae\},%ymm4,%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 52 ff d6 f4\s+vfmulcph \{rz-sae\},%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 5b f5\s+vcvtdq2ph \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 78 3f 5b f5\s+vcvtdq2ph \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 5b f5\s+vcvtdq2ph \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 78 18 5b f5\s+vcvtdq2ps \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 78 3f 5b f5\s+vcvtdq2ps \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 5b f5\s+vcvtdq2ps \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7b 18 7a f5\s+vcvtudq2ph \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 7b 3f 7a f5\s+vcvtudq2ph \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 7b ff 7a f5\s+vcvtudq2ph \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 7b 18 7a f5\s+vcvtudq2ps \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 7b 3f 7a f5\s+vcvtudq2ps \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 7b ff 7a f5\s+vcvtudq2ps \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 fb 18 e6 f5\s+vcvtpd2dq \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 fb 3f e6 f5\s+vcvtpd2dq \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 fb ff e6 f5\s+vcvtpd2dq \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 f9 18 5a f5\s+vcvtpd2ph \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 f9 3f 5a f5\s+vcvtpd2ph \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 f9 ff 5a f5\s+vcvtpd2ph \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 5a f5\s+vcvtpd2ps \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 f9 3f 5a f5\s+vcvtpd2ps \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 5a f5\s+vcvtpd2ps \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 79 f5\s+vcvtpd2udq \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 f8 3f 79 f5\s+vcvtpd2udq \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f8 ff 79 f5\s+vcvtpd2udq \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 7b f5\s+vcvtpd2qq \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 f9 3f 7b f5\s+vcvtpd2qq \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 7b f5\s+vcvtpd2qq \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 79 f5\s+vcvtpd2uqq \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 f9 3f 79 f5\s+vcvtpd2uqq \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 ff 79 f5\s+vcvtpd2uqq \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 5b f5\s+vcvtph2dq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 3f 5b f5\s+vcvtph2dq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 5b f5\s+vcvtph2dq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7b f5\s+vcvtph2qq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 3f 7b f5\s+vcvtph2qq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 7b f5\s+vcvtph2qq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 79 f5\s+vcvtph2udq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 3f 79 f5\s+vcvtph2udq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 79 f5\s+vcvtph2udq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 79 f5\s+vcvtph2uqq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 3f 79 f5\s+vcvtph2uqq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 79 f5\s+vcvtph2uqq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 5a f5\s+vcvtph2pd \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 1f 5a f5\s+vcvtph2pd \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 5a f5\s+vcvtph2pd \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f2 79 18 13 f5\s+vcvtph2ps \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f2 79 1f 13 f5\s+vcvtph2ps \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f2 79 9f 13 f5\s+vcvtph2ps \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f6 79 18 13 f5\s+vcvtph2psx \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f6 79 1f 13 f5\s+vcvtph2psx \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f6 79 9f 13 f5\s+vcvtph2psx \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 7d f5\s+vcvtph2uw \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 3f 7d f5\s+vcvtph2uw \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 ff 7d f5\s+vcvtph2uw \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7d f5\s+vcvtph2w \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 3f 7d f5\s+vcvtph2w \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 7d f5\s+vcvtph2w \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 79 18 5b f5\s+vcvtps2dq \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 79 3f 5b f5\s+vcvtps2dq \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 5b f5\s+vcvtps2dq \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 78 18 79 f5\s+vcvtps2udq \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 78 3f 79 f5\s+vcvtps2udq \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 78 ff 79 f5\s+vcvtps2udq \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 78 18 5a f5\s+vcvtps2pd \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 78 1f 5a f5\s+vcvtps2pd \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 78 9f 5a f5\s+vcvtps2pd \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 1d f5\s+vcvtps2phx \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 79 3f 1d f5\s+vcvtps2phx \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 ff 1d f5\s+vcvtps2phx \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 79 18 7b f5\s+vcvtps2qq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 79 3f 7b f5\s+vcvtps2qq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 7b f5\s+vcvtps2qq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 79 18 79 f5\s+vcvtps2uqq \{rn-sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 79 3f 79 f5\s+vcvtps2uqq \{rd-sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 79 ff 79 f5\s+vcvtps2uqq \{rz-sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 fa 18 e6 f5\s+vcvtqq2pd \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 fa 3f e6 f5\s+vcvtqq2pd \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 fa ff e6 f5\s+vcvtqq2pd \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 f8 18 5b f5\s+vcvtqq2ph \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 f8 3f 5b f5\s+vcvtqq2ph \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 f8 ff 5b f5\s+vcvtqq2ph \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 5b f5\s+vcvtqq2ps \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 f8 3f 5b f5\s+vcvtqq2ps \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f8 ff 5b f5\s+vcvtqq2ps \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 fa 18 7a f5\s+vcvtuqq2pd \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 fa 3f 7a f5\s+vcvtuqq2pd \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 fa ff 7a f5\s+vcvtuqq2pd \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 fb 18 7a f5\s+vcvtuqq2ph \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f5 fb 3f 7a f5\s+vcvtuqq2ph \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 fb ff 7a f5\s+vcvtuqq2ph \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 fb 18 7a f5\s+vcvtuqq2ps \{rn-sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 fb 3f 7a f5\s+vcvtuqq2ps \{rd-sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 fb ff 7a f5\s+vcvtuqq2ps \{rz-sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 e6 f5\s+vcvttpd2dq \{sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 f9 1f e6 f5\s+vcvttpd2dq \{sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f e6 f5\s+vcvttpd2dq \{sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f8 18 78 f5\s+vcvttpd2udq \{sae\},%ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f1 f8 1f 78 f5\s+vcvttpd2udq \{sae\},%ymm5,%xmm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f8 9f 78 f5\s+vcvttpd2udq \{sae\},%ymm5,%xmm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 7a f5\s+vcvttpd2qq \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 f9 1f 7a f5\s+vcvttpd2qq \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f 7a f5\s+vcvttpd2qq \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 f9 18 78 f5\s+vcvttpd2uqq \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 f9 1f 78 f5\s+vcvttpd2uqq \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 f9 9f 78 f5\s+vcvttpd2uqq \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7a 18 5b f5\s+vcvttph2dq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 7a 1f 5b f5\s+vcvttph2dq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 7a 9f 5b f5\s+vcvttph2dq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7a f5\s+vcvttph2qq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 1f 7a f5\s+vcvttph2qq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 7a f5\s+vcvttph2qq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 78 f5\s+vcvttph2udq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 1f 78 f5\s+vcvttph2udq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 78 f5\s+vcvttph2udq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 78 f5\s+vcvttph2uqq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 1f 78 f5\s+vcvttph2uqq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 78 f5\s+vcvttph2uqq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 78 18 7c f5\s+vcvttph2uw \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 78 1f 7c f5\s+vcvttph2uw \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 78 9f 7c f5\s+vcvttph2uw \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 79 18 7c f5\s+vcvttph2w \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 79 1f 7c f5\s+vcvttph2w \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 79 9f 7c f5\s+vcvttph2w \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 7a 18 5b f5\s+vcvttps2dq \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 7a 1f 5b f5\s+vcvttps2dq \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 7a 9f 5b f5\s+vcvttps2dq \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 78 18 78 f5\s+vcvttps2udq \{sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 78 1f 78 f5\s+vcvttps2udq \{sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 78 9f 78 f5\s+vcvttps2udq \{sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 79 18 7a f5\s+vcvttps2qq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 79 1f 7a f5\s+vcvttps2qq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 79 9f 7a f5\s+vcvttps2qq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f1 79 18 78 f5\s+vcvttps2uqq \{sae\},%xmm5,%ymm6
+\s*[a-f0-9]+:\s*62 f1 79 1f 78 f5\s+vcvttps2uqq \{sae\},%xmm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f1 79 9f 78 f5\s+vcvttps2uqq \{sae\},%xmm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7b 18 7d f5\s+vcvtuw2ph \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 7b 3f 7d f5\s+vcvtuw2ph \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 7b ff 7d f5\s+vcvtuw2ph \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 f5 7a 18 7d f5\s+vcvtw2ph \{rn-sae\},%ymm5,%ymm6
+\s*[a-f0-9]+:\s*62 f5 7a 3f 7d f5\s+vcvtw2ph \{rd-sae\},%ymm5,%ymm6\{%k7\}
+\s*[a-f0-9]+:\s*62 f5 7a ff 7d f5\s+vcvtw2ph \{rz-sae\},%ymm5,%ymm6\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx10_2-rounding.s b/gas/testsuite/gas/i386/avx10_2-rounding.s
new file mode 100644
index 00000000000..713c21dae52
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx10_2-rounding.s
@@ -0,0 +1,350 @@ 
+# Check 32bit AVX10.2 instructions
+
+	.text
+_start:
+	.irp m, pd, ph, ps
+	vcmp\m	$123, {sae}, %ymm4, %ymm5, %k5
+	vcmp\m	$123, {sae}, %ymm4, %ymm5, %k5{%k7}
+	vgetexp\m	{sae}, %ymm5, %ymm6
+	vgetexp\m	{sae}, %ymm5, %ymm6{%k7}
+	vgetexp\m	{sae}, %ymm5, %ymm6{%k7}{z}
+	vsqrt\m	{rn-sae}, %ymm5, %ymm6
+	vsqrt\m	{rd-sae}, %ymm5, %ymm6{%k7}
+	vsqrt\m	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp a, add, div, mul, scalef, sub
+	.irp m, pd, ph, ps
+	v\a\m	{rn-sae}, %ymm4, %ymm5, %ymm6
+	v\a\m	{rd-sae}, %ymm4, %ymm5, %ymm6{%k7}
+	v\a\m	{rz-sae}, %ymm4, %ymm5, %ymm6{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, max, min
+	.irp m, pd, ph, ps
+	v\a\m	{sae}, %ymm4, %ymm5, %ymm6
+	v\a\m	{sae}, %ymm4, %ymm5, %ymm6{%k7}
+	v\a\m	{sae}, %ymm4, %ymm5, %ymm6{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, getmant, reduce, rndscale
+	.irp m, pd, ph, ps
+	v\a\m	$123, {sae}, %ymm5, %ymm6
+	v\a\m	$123, {sae}, %ymm5, %ymm6{%k7}
+	v\a\m	$123, {sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, madd, maddsub, msub, msubadd, nmadd, nmsub
+	.irp n, 132, 213, 231
+	.irp m, pd, ph, ps
+	vf\a\n\m	{rn-sae}, %ymm4, %ymm5, %ymm6
+	vf\a\n\m	{rd-sae}, %ymm4, %ymm5, %ymm6{%k7}
+	vf\a\n\m	{rz-sae}, %ymm4, %ymm5, %ymm6{%k7}{z}
+	.endr
+	.endr
+	.endr
+
+	.irp a, fixupimm, range
+	.irp m, pd, ps
+	v\a\m	$123, {sae}, %ymm4, %ymm5, %ymm6
+	v\a\m	$123, {sae}, %ymm4, %ymm5, %ymm6{%k7}
+	v\a\m	$123, {sae}, %ymm4, %ymm5, %ymm6{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, cmadd, cmul, madd, mul
+	vf\a\()cph	{rn-sae}, %ymm4, %ymm5, %ymm6
+	vf\a\()cph	{rd-sae}, %ymm4, %ymm5, %ymm6{%k7}
+	vf\a\()cph	{rz-sae}, %ymm4, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp n, dq, udq
+	vcvt\n\()2ph	{rn-sae}, %ymm5, %xmm6
+	vcvt\n\()2ph	{rd-sae}, %ymm5, %xmm6{%k7}
+	vcvt\n\()2ph	{rz-sae}, %ymm5, %xmm6{%k7}{z}
+
+	vcvt\n\()2ps	{rn-sae}, %ymm5, %ymm6
+	vcvt\n\()2ps	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvt\n\()2ps	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, dq, ph, ps, udq
+	vcvtpd2\m	{rn-sae}, %ymm5, %xmm6
+	vcvtpd2\m	{rd-sae}, %ymm5, %xmm6{%k7}
+	vcvtpd2\m	{rz-sae}, %ymm5, %xmm6{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvtpd2\m	{rn-sae}, %ymm5, %ymm6
+	vcvtpd2\m	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvtpd2\m	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvtph2\m	{rn-sae}, %xmm5, %ymm6
+	vcvtph2\m	{rd-sae}, %xmm5, %ymm6{%k7}
+	vcvtph2\m	{rz-sae}, %xmm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, pd, ps, psx
+	vcvtph2\m	{sae}, %xmm5, %ymm6
+	vcvtph2\m	{sae}, %xmm5, %ymm6{%k7}
+	vcvtph2\m	{sae}, %xmm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, uw, w
+	vcvtph2\m	{rn-sae}, %ymm5, %ymm6
+	vcvtph2\m	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvtph2\m	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, dq, udq
+	vcvtps2\m	{rn-sae}, %ymm5, %ymm6
+	vcvtps2\m	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvtps2\m	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	vcvtps2pd	{sae}, %xmm5, %ymm6
+	vcvtps2pd	{sae}, %xmm5, %ymm6{%k7}
+	vcvtps2pd	{sae}, %xmm5, %ymm6{%k7}{z}
+
+	vcvtps2phx	{rn-sae}, %ymm5, %xmm6
+	vcvtps2phx	{rd-sae}, %ymm5, %xmm6{%k7}
+	vcvtps2phx	{rz-sae}, %ymm5, %xmm6{%k7}{z}
+
+	.irp m, qq, uqq
+	vcvtps2\m	{rn-sae}, %xmm5, %ymm6
+	vcvtps2\m	{rd-sae}, %xmm5, %ymm6{%k7}
+	vcvtps2\m	{rz-sae}, %xmm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp n, qq, uqq
+	vcvt\n\()2pd	{rn-sae}, %ymm5, %ymm6
+	vcvt\n\()2pd	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvt\n\()2pd	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+
+	.irp m, ph, ps
+	vcvt\n\()2\m	{rn-sae}, %ymm5, %xmm6
+	vcvt\n\()2\m	{rd-sae}, %ymm5, %xmm6{%k7}
+	vcvt\n\()2\m	{rz-sae}, %ymm5, %xmm6{%k7}{z}
+	.endr
+	.endr
+
+	.irp m, dq, udq
+	vcvttpd2\m	{sae}, %ymm5, %xmm6
+	vcvttpd2\m	{sae}, %ymm5, %xmm6{%k7}
+	vcvttpd2\m	{sae}, %ymm5, %xmm6{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttpd2\m	{sae}, %ymm5, %ymm6
+	vcvttpd2\m	{sae}, %ymm5, %ymm6{%k7}
+	vcvttpd2\m	{sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvttph2\m	{sae}, %xmm5, %ymm6
+	vcvttph2\m	{sae}, %xmm5, %ymm6{%k7}
+	vcvttph2\m	{sae}, %xmm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, uw, w
+	vcvttph2\m	{sae}, %ymm5, %ymm6
+	vcvttph2\m	{sae}, %ymm5, %ymm6{%k7}
+	vcvttph2\m	{sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, dq, udq
+	vcvttps2\m	{sae}, %ymm5, %ymm6
+	vcvttps2\m	{sae}, %ymm5, %ymm6{%k7}
+	vcvttps2\m	{sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttps2\m	{sae}, %xmm5, %ymm6
+	vcvttps2\m	{sae}, %xmm5, %ymm6{%k7}
+	vcvttps2\m	{sae}, %xmm5, %ymm6{%k7}{z}
+	.endr
+
+	.irp n, uw, w
+	vcvt\n\()2ph	{rn-sae}, %ymm5, %ymm6
+	vcvt\n\()2ph	{rd-sae}, %ymm5, %ymm6{%k7}
+	vcvt\n\()2ph	{rz-sae}, %ymm5, %ymm6{%k7}{z}
+	.endr
+
+	.intel_syntax noprefix
+	.irp m, pd, ph, ps
+	vcmp\m	k5, ymm5, ymm4{sae}, 123
+	vcmp\m	k5{k7}, ymm5, ymm4{sae}, 123
+	vgetexp\m	ymm6, ymm5{sae}
+	vgetexp\m	ymm6{k7}, ymm5{sae}
+	vgetexp\m	ymm6{k7}{z}, ymm5{sae}
+	vsqrt\m	ymm6, ymm5{rn-sae}
+	vsqrt\m	ymm6{k7}, ymm5{rd-sae}
+	vsqrt\m	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	.irp a, add, div, mul, scalef, sub
+	.irp m, pd, ph, ps
+	v\a\m	ymm6, ymm5, ymm4{rn-sae}
+	v\a\m	ymm6{k7}, ymm5, ymm4{rd-sae}
+	v\a\m	ymm6{k7}{z}, ymm5, ymm4{rz-sae}
+	.endr
+	.endr
+
+	.irp a, max, min
+	.irp m, pd, ph, ps
+	v\a\m	ymm6, ymm5, ymm4, {sae}
+	v\a\m	ymm6{k7}, ymm5, ymm4, {sae}
+	v\a\m	ymm6{k7}{z}, ymm5, ymm4, {sae}
+	.endr
+	.endr
+
+	.irp a, getmant, reduce, rndscale
+	.irp m, pd, ph, ps
+	v\a\m	ymm6, ymm5{sae}, 123
+	v\a\m	ymm6{k7}, ymm5{sae}, 123
+	v\a\m	ymm6{k7}{z}, ymm5{sae}, 123
+	.endr
+	.endr
+
+	.irp a, madd, maddsub, msub, msubadd, nmadd, nmsub
+	.irp n, 132, 213, 231
+	.irp m, pd, ph, ps
+	vf\a\n\m	ymm6, ymm5, ymm4{rn-sae}
+	vf\a\n\m	ymm6{k7}, ymm5, ymm4{rd-sae}
+	vf\a\n\m	ymm6{k7}{z}, ymm5, ymm4{rz-sae}
+	.endr
+	.endr
+	.endr
+
+	.irp a, fixupimm, range
+	.irp m, pd, ps
+	v\a\m	ymm6, ymm5, ymm4{sae}, 123
+	v\a\m	ymm6{k7}, ymm5, ymm4{sae}, 123
+	v\a\m	ymm6{k7}{z}, ymm5, ymm4{sae}, 123
+	.endr
+	.endr
+
+	.irp a, cmadd, cmul, madd, mul
+	vf\a\()cph	ymm6, ymm5, ymm4{rn-sae}
+	vf\a\()cph	ymm6{k7}, ymm5, ymm4{rd-sae}
+	vf\a\()cph	ymm6{k7}{z}, ymm5, ymm4{rz-sae}
+	.endr
+
+	.irp n, dq, udq
+	vcvt\n\()2ph	xmm6, ymm5{rn-sae}
+	vcvt\n\()2ph	xmm6{k7}, ymm5{rd-sae}
+	vcvt\n\()2ph	xmm6{k7}{z}, ymm5{rz-sae}
+
+	vcvt\n\()2ps	ymm6, ymm5{rn-sae}
+	vcvt\n\()2ps	ymm6{k7}, ymm5{rd-sae}
+	vcvt\n\()2ps	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	.irp m, dq, ph, ps, udq
+	vcvtpd2\m	xmm6, ymm5{rn-sae}
+	vcvtpd2\m	xmm6{k7}, ymm5{rd-sae}
+	vcvtpd2\m	xmm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvtpd2\m	ymm6, ymm5{rn-sae}
+	vcvtpd2\m	ymm6{k7}, ymm5{rd-sae}
+	vcvtpd2\m	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvtph2\m	ymm6, xmm5{rn-sae}
+	vcvtph2\m	ymm6{k7}, xmm5{rd-sae}
+	vcvtph2\m	ymm6{k7}{z}, xmm5{rz-sae}
+	.endr
+
+	.irp m, pd, ps, psx
+	vcvtph2\m	ymm6, xmm5{sae}
+	vcvtph2\m	ymm6{k7}, xmm5{sae}
+	vcvtph2\m	ymm6{k7}{z}, xmm5{sae}
+	.endr
+
+	.irp m, uw, w
+	vcvtph2\m	ymm6, ymm5{rn-sae}
+	vcvtph2\m	ymm6{k7}, ymm5{rd-sae}
+	vcvtph2\m	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	.irp m, dq, udq
+	vcvtps2\m	ymm6, ymm5{rn-sae}
+	vcvtps2\m	ymm6{k7}, ymm5{rd-sae}
+	vcvtps2\m	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
+
+	vcvtps2pd	ymm6, xmm5{sae}
+	vcvtps2pd	ymm6{k7}, xmm5{sae}
+	vcvtps2pd	ymm6{k7}{z}, xmm5{sae}
+
+	vcvtps2phx	xmm6, ymm5{rn-sae}
+	vcvtps2phx	xmm6{k7}, ymm5{rd-sae}
+	vcvtps2phx	xmm6{k7}{z}, ymm5{rz-sae}
+
+	.irp m, qq, uqq
+	vcvtps2\m	ymm6, xmm5{rn-sae}
+	vcvtps2\m	ymm6{k7}, xmm5{rd-sae}
+	vcvtps2\m	ymm6{k7}{z}, xmm5{rz-sae}
+	.endr
+
+	.irp n, qq, uqq
+	vcvt\n\()2pd	ymm6, ymm5{rn-sae}
+	vcvt\n\()2pd	ymm6{k7}, ymm5{rd-sae}
+	vcvt\n\()2pd	ymm6{k7}{z}, ymm5{rz-sae}
+
+	.irp m, ph, ps
+	vcvt\n\()2\m	xmm6, ymm5{rn-sae}
+	vcvt\n\()2\m	xmm6{k7}, ymm5{rd-sae}
+	vcvt\n\()2\m	xmm6{k7}{z}, ymm5{rz-sae}
+	.endr
+	.endr
+
+	.irp m, dq, udq
+	vcvttpd2\m	xmm6, ymm5{sae}
+	vcvttpd2\m	xmm6{k7}, ymm5{sae}
+	vcvttpd2\m	xmm6{k7}{z}, ymm5{sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttpd2\m	ymm6, ymm5{sae}
+	vcvttpd2\m	ymm6{k7}, ymm5{sae}
+	vcvttpd2\m	ymm6{k7}{z}, ymm5{sae}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvttph2\m	ymm6, xmm5{sae}
+	vcvttph2\m	ymm6{k7}, xmm5{sae}
+	vcvttph2\m	ymm6{k7}{z}, xmm5{sae}
+	.endr
+
+	.irp m, uw, w
+	vcvttph2\m	ymm6, ymm5{sae}
+	vcvttph2\m	ymm6{k7}, ymm5{sae}
+	vcvttph2\m	ymm6{k7}{z}, ymm5{sae}
+	.endr
+
+	.irp m, dq, udq
+	vcvttps2\m	ymm6, ymm5{sae}
+	vcvttps2\m	ymm6{k7}, ymm5{sae}
+	vcvttps2\m	ymm6{k7}{z}, ymm5{sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttps2\m	ymm6, xmm5{sae}
+	vcvttps2\m	ymm6{k7}, xmm5{sae}
+	vcvttps2\m	ymm6{k7}{z}, xmm5{sae}
+	.endr
+
+	.irp n, uw, w
+	vcvt\n\()2ph	ymm6, ymm5{rn-sae}
+	vcvt\n\()2ph	ymm6{k7}, ymm5{rd-sae}
+	vcvt\n\()2ph	ymm6{k7}{z}, ymm5{rz-sae}
+	.endr
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3e707b3d0c6..75ad061b32c 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -519,6 +519,9 @@  if [gas_32_check] then {
     run_list_test "pbndkb-inval"
     run_list_test "user_msr-inval"
     run_list_test "apx-push2pop2-inval"
+    run_dump_test "avx10_2-rounding"
+    run_dump_test "avx10_2-rounding-intel"
+    run_list_test "avx10_2-rounding-inval"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d
new file mode 100644
index 00000000000..d5e17c2069f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d
@@ -0,0 +1,452 @@ 
+#objdump: -dw -Mintel
+#name: x86_64 AVX10.2 rounding insns (Intel disassembly)
+#source: x86-64-avx10_2-rounding.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+#...
+\s*a83:\s*62 91 91 10 c2 ec 7b\s+vcmppd k5,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 91 91 17 c2 ec 7b\s+vcmppd k5\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 02 f9 18 42 f5\s+vgetexppd ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 f9 1f 42 f5\s+vgetexppd ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 f9 9f 42 f5\s+vgetexppd ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 51 f5\s+vsqrtpd ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 3f 51 f5\s+vsqrtpd ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 51 f5\s+vsqrtpd ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 93 10 10 c2 ec 7b\s+vcmpph k5,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 93 10 17 c2 ec 7b\s+vcmpph k5\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 06 79 18 42 f5\s+vgetexpph ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 06 79 1f 42 f5\s+vgetexpph ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 06 79 9f 42 f5\s+vgetexpph ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 51 f5\s+vsqrtph ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 78 3f 51 f5\s+vsqrtph ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 78 ff 51 f5\s+vsqrtph ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 91 10 10 c2 ec 7b\s+vcmpps k5,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 91 10 17 c2 ec 7b\s+vcmpps k5\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 02 79 18 42 f5\s+vgetexpps ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 79 1f 42 f5\s+vgetexpps ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 79 9f 42 f5\s+vgetexpps ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 18 51 f5\s+vsqrtps ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 78 3f 51 f5\s+vsqrtps ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 78 ff 51 f5\s+vsqrtps ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 58 f4\s+vaddpd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 91 37 58 f4\s+vaddpd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 91 f7 58 f4\s+vaddpd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 58 f4\s+vaddph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 10 37 58 f4\s+vaddph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 10 f7 58 f4\s+vaddph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 58 f4\s+vaddps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 10 37 58 f4\s+vaddps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 10 f7 58 f4\s+vaddps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 5e f4\s+vdivpd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 91 37 5e f4\s+vdivpd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 91 f7 5e f4\s+vdivpd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 5e f4\s+vdivph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 10 37 5e f4\s+vdivph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 10 f7 5e f4\s+vdivph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 5e f4\s+vdivps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 10 37 5e f4\s+vdivps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 10 f7 5e f4\s+vdivps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 59 f4\s+vmulpd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 91 37 59 f4\s+vmulpd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 91 f7 59 f4\s+vmulpd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 59 f4\s+vmulph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 10 37 59 f4\s+vmulph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 10 f7 59 f4\s+vmulph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 59 f4\s+vmulps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 10 37 59 f4\s+vmulps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 10 f7 59 f4\s+vmulps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 02 91 10 2c f4\s+vscalefpd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 02 91 37 2c f4\s+vscalefpd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 02 91 f7 2c f4\s+vscalefpd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 11 10 2c f4\s+vscalefph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 11 37 2c f4\s+vscalefph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 11 f7 2c f4\s+vscalefph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 02 11 10 2c f4\s+vscalefps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 02 11 37 2c f4\s+vscalefps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 02 11 f7 2c f4\s+vscalefps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 5c f4\s+vsubpd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 91 37 5c f4\s+vsubpd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 91 f7 5c f4\s+vsubpd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 5c f4\s+vsubph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 10 37 5c f4\s+vsubph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 10 f7 5c f4\s+vsubph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 5c f4\s+vsubps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 10 37 5c f4\s+vsubps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 10 f7 5c f4\s+vsubps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 5f f4\s+vmaxpd ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 91 17 5f f4\s+vmaxpd ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 91 97 5f f4\s+vmaxpd ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 5f f4\s+vmaxph ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 17 5f f4\s+vmaxph ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 97 5f f4\s+vmaxph ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 5f f4\s+vmaxps ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 17 5f f4\s+vmaxps ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 97 5f f4\s+vmaxps ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 91 10 5d f4\s+vminpd ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 91 17 5d f4\s+vminpd ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 91 97 5d f4\s+vminpd ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 10 5d f4\s+vminph ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 17 5d f4\s+vminph ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 05 10 97 5d f4\s+vminph ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 10 5d f4\s+vminps ymm30,ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 17 5d f4\s+vminps ymm30\{k7\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 01 10 97 5d f4\s+vminps ymm30\{k7\}\{z\},ymm29,ymm28\{sae\}
+\s*[a-f0-9]+:\s*62 03 f9 18 26 f5 7b\s+vgetmantpd ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 1f 26 f5 7b\s+vgetmantpd ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 9f 26 f5 7b\s+vgetmantpd ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 18 26 f5 7b\s+vgetmantph ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 1f 26 f5 7b\s+vgetmantph ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 9f 26 f5 7b\s+vgetmantph ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 18 26 f5 7b\s+vgetmantps ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 1f 26 f5 7b\s+vgetmantps ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 9f 26 f5 7b\s+vgetmantps ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 18 56 f5 7b\s+vreducepd ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 1f 56 f5 7b\s+vreducepd ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 9f 56 f5 7b\s+vreducepd ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 18 56 f5 7b\s+vreduceph ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 1f 56 f5 7b\s+vreduceph ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 9f 56 f5 7b\s+vreduceph ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 18 56 f5 7b\s+vreduceps ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 1f 56 f5 7b\s+vreduceps ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 9f 56 f5 7b\s+vreduceps ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 18 09 f5 7b\s+vrndscalepd ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 1f 09 f5 7b\s+vrndscalepd ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 f9 9f 09 f5 7b\s+vrndscalepd ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 18 08 f5 7b\s+vrndscaleph ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 1f 08 f5 7b\s+vrndscaleph ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 78 9f 08 f5 7b\s+vrndscaleph ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 18 08 f5 7b\s+vrndscaleps ymm30,ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 1f 08 f5 7b\s+vrndscaleps ymm30\{k7\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 79 9f 08 f5 7b\s+vrndscaleps ymm30\{k7\}\{z\},ymm29\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 02 91 10 98 f4\s+vfmadd132pd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 02 91 37 98 f4\s+vfmadd132pd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 02 91 f7 98 f4\s+vfmadd132pd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 11 10 98 f4\s+vfmadd132ph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 11 37 98 f4\s+vfmadd132ph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 11 f7 98 f4\s+vfmadd132ph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 02 11 10 98 f4\s+vfmadd132ps ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 02 11 37 98 f4\s+vfmadd132ps ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 02 11 f7 98 f4\s+vfmadd132ps ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 02 91 10 a8 f4\s+vfmadd213pd ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 02 91 37 a8 f4\s+vfmadd213pd ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 02 91 f7 a8 f4\s+vfmadd213pd ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 11 10 a8 f4\s+vfmadd213ph ymm30,ymm29,ymm28\{rn-sae\}
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+\s*[a-f0-9]+:\s*62 03 91 17 54 f4 7b\s+vfixupimmpd ymm30\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 91 97 54 f4 7b\s+vfixupimmpd ymm30\{k7\}\{z\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 10 54 f4 7b\s+vfixupimmps ymm30,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 17 54 f4 7b\s+vfixupimmps ymm30\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 97 54 f4 7b\s+vfixupimmps ymm30\{k7\}\{z\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 91 10 50 f4 7b\s+vrangepd ymm30,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 91 17 50 f4 7b\s+vrangepd ymm30\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 91 97 50 f4 7b\s+vrangepd ymm30\{k7\}\{z\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 10 50 f4 7b\s+vrangeps ymm30,ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 17 50 f4 7b\s+vrangeps ymm30\{k7\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 03 11 97 50 f4 7b\s+vrangeps ymm30\{k7\}\{z\},ymm29,ymm28\{sae\},0x7b
+\s*[a-f0-9]+:\s*62 06 13 10 56 f4\s+vfcmaddcph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 13 37 56 f4\s+vfcmaddcph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 13 f7 56 f4\s+vfcmaddcph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 13 10 d6 f4\s+vfcmulcph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 13 37 d6 f4\s+vfcmulcph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 13 f7 d6 f4\s+vfcmulcph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 12 10 56 f4\s+vfmaddcph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 12 37 56 f4\s+vfmaddcph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 12 f7 56 f4\s+vfmaddcph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 06 12 10 d6 f4\s+vfmulcph ymm30,ymm29,ymm28\{rn-sae\}
+\s*[a-f0-9]+:\s*62 06 12 37 d6 f4\s+vfmulcph ymm30\{k7\},ymm29,ymm28\{rd-sae\}
+\s*[a-f0-9]+:\s*62 06 12 f7 d6 f4\s+vfmulcph ymm30\{k7\}\{z\},ymm29,ymm28\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 5b f5\s+vcvtdq2ph xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 78 3f 5b f5\s+vcvtdq2ph xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 78 ff 5b f5\s+vcvtdq2ph xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 78 18 5b f5\s+vcvtdq2ps ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 78 3f 5b f5\s+vcvtdq2ps ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 78 ff 5b f5\s+vcvtdq2ps ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 7b 18 7a f5\s+vcvtudq2ph xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 7b 3f 7a f5\s+vcvtudq2ph xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 7b ff 7a f5\s+vcvtudq2ph xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 7b 18 7a f5\s+vcvtudq2ps ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 7b 3f 7a f5\s+vcvtudq2ps ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 7b ff 7a f5\s+vcvtudq2ps ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 fb 18 e6 f5\s+vcvtpd2dq xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 fb 3f e6 f5\s+vcvtpd2dq xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 fb ff e6 f5\s+vcvtpd2dq xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 f9 18 5a f5\s+vcvtpd2ph xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 f9 3f 5a f5\s+vcvtpd2ph xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 f9 ff 5a f5\s+vcvtpd2ph xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 5a f5\s+vcvtpd2ps xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 3f 5a f5\s+vcvtpd2ps xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 5a f5\s+vcvtpd2ps xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 18 79 f5\s+vcvtpd2udq xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 3f 79 f5\s+vcvtpd2udq xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 ff 79 f5\s+vcvtpd2udq xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 7b f5\s+vcvtpd2qq ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 3f 7b f5\s+vcvtpd2qq ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 7b f5\s+vcvtpd2qq ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 79 f5\s+vcvtpd2uqq ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 3f 79 f5\s+vcvtpd2uqq ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 79 f5\s+vcvtpd2uqq ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 5b f5\s+vcvtph2dq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 79 3f 5b f5\s+vcvtph2dq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 79 ff 5b f5\s+vcvtph2dq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 7b f5\s+vcvtph2qq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 79 3f 7b f5\s+vcvtph2qq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 79 ff 7b f5\s+vcvtph2qq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 79 f5\s+vcvtph2udq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 78 3f 79 f5\s+vcvtph2udq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 78 ff 79 f5\s+vcvtph2udq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 79 f5\s+vcvtph2uqq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 79 3f 79 f5\s+vcvtph2uqq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 79 ff 79 f5\s+vcvtph2uqq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 5a f5\s+vcvtph2pd ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 1f 5a f5\s+vcvtph2pd ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 9f 5a f5\s+vcvtph2pd ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 79 18 13 f5\s+vcvtph2ps ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 79 1f 13 f5\s+vcvtph2ps ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 02 79 9f 13 f5\s+vcvtph2ps ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 06 79 18 13 f5\s+vcvtph2psx ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 06 79 1f 13 f5\s+vcvtph2psx ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 06 79 9f 13 f5\s+vcvtph2psx ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 7d f5\s+vcvtph2uw ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 78 3f 7d f5\s+vcvtph2uw ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 78 ff 7d f5\s+vcvtph2uw ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 7d f5\s+vcvtph2w ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 79 3f 7d f5\s+vcvtph2w ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 79 ff 7d f5\s+vcvtph2w ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 79 18 5b f5\s+vcvtps2dq ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 79 3f 5b f5\s+vcvtps2dq ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 79 ff 5b f5\s+vcvtps2dq ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 78 18 79 f5\s+vcvtps2udq ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 78 3f 79 f5\s+vcvtps2udq ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 78 ff 79 f5\s+vcvtps2udq ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 78 18 5a f5\s+vcvtps2pd ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 1f 5a f5\s+vcvtps2pd ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 9f 5a f5\s+vcvtps2pd ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 1d f5\s+vcvtps2phx xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 79 3f 1d f5\s+vcvtps2phx xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 79 ff 1d f5\s+vcvtps2phx xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 79 18 7b f5\s+vcvtps2qq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 79 3f 7b f5\s+vcvtps2qq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 79 ff 7b f5\s+vcvtps2qq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 79 18 79 f5\s+vcvtps2uqq ymm30,xmm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 79 3f 79 f5\s+vcvtps2uqq ymm30\{k7\},xmm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 79 ff 79 f5\s+vcvtps2uqq ymm30\{k7\}\{z\},xmm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 fa 18 e6 f5\s+vcvtqq2pd ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 fa 3f e6 f5\s+vcvtqq2pd ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 fa ff e6 f5\s+vcvtqq2pd ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 f8 18 5b f5\s+vcvtqq2ph xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 f8 3f 5b f5\s+vcvtqq2ph xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 f8 ff 5b f5\s+vcvtqq2ph xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 18 5b f5\s+vcvtqq2ps xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 3f 5b f5\s+vcvtqq2ps xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 f8 ff 5b f5\s+vcvtqq2ps xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 fa 18 7a f5\s+vcvtuqq2pd ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 fa 3f 7a f5\s+vcvtuqq2pd ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 fa ff 7a f5\s+vcvtuqq2pd ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 fb 18 7a f5\s+vcvtuqq2ph xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 fb 3f 7a f5\s+vcvtuqq2ph xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 fb ff 7a f5\s+vcvtuqq2ph xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 fb 18 7a f5\s+vcvtuqq2ps xmm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 01 fb 3f 7a f5\s+vcvtuqq2ps xmm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 01 fb ff 7a f5\s+vcvtuqq2ps xmm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 e6 f5\s+vcvttpd2dq xmm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 1f e6 f5\s+vcvttpd2dq xmm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 9f e6 f5\s+vcvttpd2dq xmm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f8 18 78 f5\s+vcvttpd2udq xmm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f8 1f 78 f5\s+vcvttpd2udq xmm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f8 9f 78 f5\s+vcvttpd2udq xmm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 7a f5\s+vcvttpd2qq ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 1f 7a f5\s+vcvttpd2qq ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 9f 7a f5\s+vcvttpd2qq ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 18 78 f5\s+vcvttpd2uqq ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 1f 78 f5\s+vcvttpd2uqq ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 f9 9f 78 f5\s+vcvttpd2uqq ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 7a 18 5b f5\s+vcvttph2dq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 7a 1f 5b f5\s+vcvttph2dq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 7a 9f 5b f5\s+vcvttph2dq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 7a f5\s+vcvttph2qq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 1f 7a f5\s+vcvttph2qq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 9f 7a f5\s+vcvttph2qq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 78 f5\s+vcvttph2udq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 1f 78 f5\s+vcvttph2udq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 9f 78 f5\s+vcvttph2udq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 78 f5\s+vcvttph2uqq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 1f 78 f5\s+vcvttph2uqq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 9f 78 f5\s+vcvttph2uqq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 18 7c f5\s+vcvttph2uw ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 1f 7c f5\s+vcvttph2uw ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 78 9f 7c f5\s+vcvttph2uw ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 18 7c f5\s+vcvttph2w ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 1f 7c f5\s+vcvttph2w ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 79 9f 7c f5\s+vcvttph2w ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 7a 18 5b f5\s+vcvttps2dq ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 7a 1f 5b f5\s+vcvttps2dq ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 7a 9f 5b f5\s+vcvttps2dq ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 18 78 f5\s+vcvttps2udq ymm30,ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 1f 78 f5\s+vcvttps2udq ymm30\{k7\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 78 9f 78 f5\s+vcvttps2udq ymm30\{k7\}\{z\},ymm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 18 7a f5\s+vcvttps2qq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 1f 7a f5\s+vcvttps2qq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 9f 7a f5\s+vcvttps2qq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 18 78 f5\s+vcvttps2uqq ymm30,xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 1f 78 f5\s+vcvttps2uqq ymm30\{k7\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 01 79 9f 78 f5\s+vcvttps2uqq ymm30\{k7\}\{z\},xmm29\{sae\}
+\s*[a-f0-9]+:\s*62 05 7b 18 7d f5\s+vcvtuw2ph ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 7b 3f 7d f5\s+vcvtuw2ph ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 7b ff 7d f5\s+vcvtuw2ph ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+\s*[a-f0-9]+:\s*62 05 7a 18 7d f5\s+vcvtw2ph ymm30,ymm29\{rn-sae\}
+\s*[a-f0-9]+:\s*62 05 7a 3f 7d f5\s+vcvtw2ph ymm30\{k7\},ymm29\{rd-sae\}
+\s*[a-f0-9]+:\s*62 05 7a ff 7d f5\s+vcvtw2ph ymm30\{k7\}\{z\},ymm29\{rz-sae\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.d b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.d
new file mode 100644
index 00000000000..2bdfbf30740
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.d
@@ -0,0 +1,450 @@ 
+#objdump: -dw
+#name: x86_64 AVX10.2 rounding insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 91 91 10 c2 ec 7b\s+vcmppd \$0x7b,\{sae\},%ymm28,%ymm29,%k5
+\s*[a-f0-9]+:\s*62 91 91 17 c2 ec 7b\s+vcmppd \$0x7b,\{sae\},%ymm28,%ymm29,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 02 f9 18 42 f5\s+vgetexppd \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 f9 1f 42 f5\s+vgetexppd \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 f9 9f 42 f5\s+vgetexppd \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 51 f5\s+vsqrtpd \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 f9 3f 51 f5\s+vsqrtpd \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 51 f5\s+vsqrtpd \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 93 10 10 c2 ec 7b\s+vcmpph \$0x7b,\{sae\},%ymm28,%ymm29,%k5
+\s*[a-f0-9]+:\s*62 93 10 17 c2 ec 7b\s+vcmpph \$0x7b,\{sae\},%ymm28,%ymm29,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 06 79 18 42 f5\s+vgetexpph \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 79 1f 42 f5\s+vgetexpph \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 79 9f 42 f5\s+vgetexpph \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 51 f5\s+vsqrtph \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 3f 51 f5\s+vsqrtph \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 ff 51 f5\s+vsqrtph \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 91 10 10 c2 ec 7b\s+vcmpps \$0x7b,\{sae\},%ymm28,%ymm29,%k5
+\s*[a-f0-9]+:\s*62 91 10 17 c2 ec 7b\s+vcmpps \$0x7b,\{sae\},%ymm28,%ymm29,%k5\{%k7\}
+\s*[a-f0-9]+:\s*62 02 79 18 42 f5\s+vgetexpps \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 79 1f 42 f5\s+vgetexpps \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 79 9f 42 f5\s+vgetexpps \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 78 18 51 f5\s+vsqrtps \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 78 3f 51 f5\s+vsqrtps \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 78 ff 51 f5\s+vsqrtps \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 58 f4\s+vaddpd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 37 58 f4\s+vaddpd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 f7 58 f4\s+vaddpd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 58 f4\s+vaddph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 37 58 f4\s+vaddph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 f7 58 f4\s+vaddph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 58 f4\s+vaddps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 37 58 f4\s+vaddps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 f7 58 f4\s+vaddps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 5e f4\s+vdivpd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 37 5e f4\s+vdivpd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 f7 5e f4\s+vdivpd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 5e f4\s+vdivph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 37 5e f4\s+vdivph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 f7 5e f4\s+vdivph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 5e f4\s+vdivps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 37 5e f4\s+vdivps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 f7 5e f4\s+vdivps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 59 f4\s+vmulpd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 37 59 f4\s+vmulpd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 f7 59 f4\s+vmulpd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 59 f4\s+vmulph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 37 59 f4\s+vmulph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 f7 59 f4\s+vmulph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 59 f4\s+vmulps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 37 59 f4\s+vmulps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 f7 59 f4\s+vmulps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 2c f4\s+vscalefpd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 91 37 2c f4\s+vscalefpd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 91 f7 2c f4\s+vscalefpd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 11 10 2c f4\s+vscalefph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 11 37 2c f4\s+vscalefph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 11 f7 2c f4\s+vscalefph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 11 10 2c f4\s+vscalefps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 11 37 2c f4\s+vscalefps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 11 f7 2c f4\s+vscalefps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 5c f4\s+vsubpd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 37 5c f4\s+vsubpd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 f7 5c f4\s+vsubpd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 5c f4\s+vsubph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 37 5c f4\s+vsubph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 f7 5c f4\s+vsubph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 5c f4\s+vsubps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 37 5c f4\s+vsubps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 f7 5c f4\s+vsubps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 5f f4\s+vmaxpd \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 17 5f f4\s+vmaxpd \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 97 5f f4\s+vmaxpd \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 5f f4\s+vmaxph \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 17 5f f4\s+vmaxph \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 97 5f f4\s+vmaxph \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 5f f4\s+vmaxps \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 17 5f f4\s+vmaxps \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 97 5f f4\s+vmaxps \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 91 10 5d f4\s+vminpd \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 91 17 5d f4\s+vminpd \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 91 97 5d f4\s+vminpd \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 10 10 5d f4\s+vminph \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 10 17 5d f4\s+vminph \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 10 97 5d f4\s+vminph \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 10 10 5d f4\s+vminps \{sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 10 17 5d f4\s+vminps \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 10 97 5d f4\s+vminps \{sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 f9 18 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 f9 1f 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 f9 9f 26 f5 7b\s+vgetmantpd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 78 18 26 f5 7b\s+vgetmantph \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 78 1f 26 f5 7b\s+vgetmantph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 78 9f 26 f5 7b\s+vgetmantph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 79 18 26 f5 7b\s+vgetmantps \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 79 1f 26 f5 7b\s+vgetmantps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 79 9f 26 f5 7b\s+vgetmantps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 f9 18 56 f5 7b\s+vreducepd \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 f9 1f 56 f5 7b\s+vreducepd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 f9 9f 56 f5 7b\s+vreducepd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 78 18 56 f5 7b\s+vreduceph \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 78 1f 56 f5 7b\s+vreduceph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 78 9f 56 f5 7b\s+vreduceph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 79 18 56 f5 7b\s+vreduceps \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 79 1f 56 f5 7b\s+vreduceps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 79 9f 56 f5 7b\s+vreduceps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 f9 18 09 f5 7b\s+vrndscalepd \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 f9 1f 09 f5 7b\s+vrndscalepd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 f9 9f 09 f5 7b\s+vrndscalepd \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 78 18 08 f5 7b\s+vrndscaleph \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 78 1f 08 f5 7b\s+vrndscaleph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 78 9f 08 f5 7b\s+vrndscaleph \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 03 79 18 08 f5 7b\s+vrndscaleps \$0x7b,\{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 03 79 1f 08 f5 7b\s+vrndscaleps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 03 79 9f 08 f5 7b\s+vrndscaleps \$0x7b,\{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 98 f4\s+vfmadd132pd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 91 37 98 f4\s+vfmadd132pd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 91 f7 98 f4\s+vfmadd132pd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 11 10 98 f4\s+vfmadd132ph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 11 37 98 f4\s+vfmadd132ph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 11 f7 98 f4\s+vfmadd132ph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 11 10 98 f4\s+vfmadd132ps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 11 37 98 f4\s+vfmadd132ps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 11 f7 98 f4\s+vfmadd132ps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 a8 f4\s+vfmadd213pd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 91 37 a8 f4\s+vfmadd213pd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 91 f7 a8 f4\s+vfmadd213pd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 11 10 a8 f4\s+vfmadd213ph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 11 37 a8 f4\s+vfmadd213ph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 11 f7 a8 f4\s+vfmadd213ph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 11 10 a8 f4\s+vfmadd213ps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 11 37 a8 f4\s+vfmadd213ps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 11 f7 a8 f4\s+vfmadd213ps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 b8 f4\s+vfmadd231pd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 91 37 b8 f4\s+vfmadd231pd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 91 f7 b8 f4\s+vfmadd231pd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 11 10 b8 f4\s+vfmadd231ph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 11 37 b8 f4\s+vfmadd231ph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 11 f7 b8 f4\s+vfmadd231ph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 11 10 b8 f4\s+vfmadd231ps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 11 37 b8 f4\s+vfmadd231ps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 11 f7 b8 f4\s+vfmadd231ps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 96 f4\s+vfmaddsub132pd \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 91 37 96 f4\s+vfmaddsub132pd \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 91 f7 96 f4\s+vfmaddsub132pd \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 11 10 96 f4\s+vfmaddsub132ph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 11 37 96 f4\s+vfmaddsub132ph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 11 f7 96 f4\s+vfmaddsub132ph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 11 10 96 f4\s+vfmaddsub132ps \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 11 37 96 f4\s+vfmaddsub132ps \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 11 f7 96 f4\s+vfmaddsub132ps \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 91 10 a6 f4\s+vfmaddsub213pd \{rn-sae\},%ymm28,%ymm29,%ymm30
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+\s*[a-f0-9]+:\s*62 06 12 f7 56 f4\s+vfmaddcph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 12 10 d6 f4\s+vfmulcph \{rn-sae\},%ymm28,%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 12 37 d6 f4\s+vfmulcph \{rd-sae\},%ymm28,%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 12 f7 d6 f4\s+vfmulcph \{rz-sae\},%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 5b f5\s+vcvtdq2ph \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 78 3f 5b f5\s+vcvtdq2ph \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 ff 5b f5\s+vcvtdq2ph \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 78 18 5b f5\s+vcvtdq2ps \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 78 3f 5b f5\s+vcvtdq2ps \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 78 ff 5b f5\s+vcvtdq2ps \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 7b 18 7a f5\s+vcvtudq2ph \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 7b 3f 7a f5\s+vcvtudq2ph \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 7b ff 7a f5\s+vcvtudq2ph \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 7b 18 7a f5\s+vcvtudq2ps \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 7b 3f 7a f5\s+vcvtudq2ps \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 7b ff 7a f5\s+vcvtudq2ps \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 fb 18 e6 f5\s+vcvtpd2dq \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 fb 3f e6 f5\s+vcvtpd2dq \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 fb ff e6 f5\s+vcvtpd2dq \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 f9 18 5a f5\s+vcvtpd2ph \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 f9 3f 5a f5\s+vcvtpd2ph \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 f9 ff 5a f5\s+vcvtpd2ph \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 5a f5\s+vcvtpd2ps \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 f9 3f 5a f5\s+vcvtpd2ps \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 5a f5\s+vcvtpd2ps \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f8 18 79 f5\s+vcvtpd2udq \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 f8 3f 79 f5\s+vcvtpd2udq \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f8 ff 79 f5\s+vcvtpd2udq \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 7b f5\s+vcvtpd2qq \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 f9 3f 7b f5\s+vcvtpd2qq \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 7b f5\s+vcvtpd2qq \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 79 f5\s+vcvtpd2uqq \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 f9 3f 79 f5\s+vcvtpd2uqq \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 ff 79 f5\s+vcvtpd2uqq \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 5b f5\s+vcvtph2dq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 3f 5b f5\s+vcvtph2dq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 ff 5b f5\s+vcvtph2dq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 7b f5\s+vcvtph2qq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 3f 7b f5\s+vcvtph2qq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 ff 7b f5\s+vcvtph2qq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 79 f5\s+vcvtph2udq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 3f 79 f5\s+vcvtph2udq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 ff 79 f5\s+vcvtph2udq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 79 f5\s+vcvtph2uqq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 3f 79 f5\s+vcvtph2uqq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 ff 79 f5\s+vcvtph2uqq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 5a f5\s+vcvtph2pd \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 1f 5a f5\s+vcvtph2pd \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 9f 5a f5\s+vcvtph2pd \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 02 79 18 13 f5\s+vcvtph2ps \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 02 79 1f 13 f5\s+vcvtph2ps \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 02 79 9f 13 f5\s+vcvtph2ps \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 06 79 18 13 f5\s+vcvtph2psx \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 06 79 1f 13 f5\s+vcvtph2psx \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 06 79 9f 13 f5\s+vcvtph2psx \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 7d f5\s+vcvtph2uw \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 3f 7d f5\s+vcvtph2uw \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 ff 7d f5\s+vcvtph2uw \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 7d f5\s+vcvtph2w \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 3f 7d f5\s+vcvtph2w \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 ff 7d f5\s+vcvtph2w \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 79 18 5b f5\s+vcvtps2dq \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 79 3f 5b f5\s+vcvtps2dq \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 79 ff 5b f5\s+vcvtps2dq \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 78 18 79 f5\s+vcvtps2udq \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 78 3f 79 f5\s+vcvtps2udq \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 78 ff 79 f5\s+vcvtps2udq \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 78 18 5a f5\s+vcvtps2pd \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 78 1f 5a f5\s+vcvtps2pd \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 78 9f 5a f5\s+vcvtps2pd \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 1d f5\s+vcvtps2phx \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 79 3f 1d f5\s+vcvtps2phx \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 ff 1d f5\s+vcvtps2phx \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 79 18 7b f5\s+vcvtps2qq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 79 3f 7b f5\s+vcvtps2qq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 79 ff 7b f5\s+vcvtps2qq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 79 18 79 f5\s+vcvtps2uqq \{rn-sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 79 3f 79 f5\s+vcvtps2uqq \{rd-sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 79 ff 79 f5\s+vcvtps2uqq \{rz-sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 fa 18 e6 f5\s+vcvtqq2pd \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 fa 3f e6 f5\s+vcvtqq2pd \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 fa ff e6 f5\s+vcvtqq2pd \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 f8 18 5b f5\s+vcvtqq2ph \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 f8 3f 5b f5\s+vcvtqq2ph \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 f8 ff 5b f5\s+vcvtqq2ph \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f8 18 5b f5\s+vcvtqq2ps \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 f8 3f 5b f5\s+vcvtqq2ps \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f8 ff 5b f5\s+vcvtqq2ps \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 fa 18 7a f5\s+vcvtuqq2pd \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 fa 3f 7a f5\s+vcvtuqq2pd \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 fa ff 7a f5\s+vcvtuqq2pd \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 fb 18 7a f5\s+vcvtuqq2ph \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 05 fb 3f 7a f5\s+vcvtuqq2ph \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 fb ff 7a f5\s+vcvtuqq2ph \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 fb 18 7a f5\s+vcvtuqq2ps \{rn-sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 fb 3f 7a f5\s+vcvtuqq2ps \{rd-sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 fb ff 7a f5\s+vcvtuqq2ps \{rz-sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 e6 f5\s+vcvttpd2dq \{sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 f9 1f e6 f5\s+vcvttpd2dq \{sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 9f e6 f5\s+vcvttpd2dq \{sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f8 18 78 f5\s+vcvttpd2udq \{sae\},%ymm29,%xmm30
+\s*[a-f0-9]+:\s*62 01 f8 1f 78 f5\s+vcvttpd2udq \{sae\},%ymm29,%xmm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f8 9f 78 f5\s+vcvttpd2udq \{sae\},%ymm29,%xmm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 7a f5\s+vcvttpd2qq \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 f9 1f 7a f5\s+vcvttpd2qq \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 9f 7a f5\s+vcvttpd2qq \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 f9 18 78 f5\s+vcvttpd2uqq \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 f9 1f 78 f5\s+vcvttpd2uqq \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 f9 9f 78 f5\s+vcvttpd2uqq \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 7a 18 5b f5\s+vcvttph2dq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 7a 1f 5b f5\s+vcvttph2dq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 7a 9f 5b f5\s+vcvttph2dq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 7a f5\s+vcvttph2qq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 1f 7a f5\s+vcvttph2qq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 9f 7a f5\s+vcvttph2qq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 78 f5\s+vcvttph2udq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 1f 78 f5\s+vcvttph2udq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 9f 78 f5\s+vcvttph2udq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 78 f5\s+vcvttph2uqq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 1f 78 f5\s+vcvttph2uqq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 9f 78 f5\s+vcvttph2uqq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 78 18 7c f5\s+vcvttph2uw \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 78 1f 7c f5\s+vcvttph2uw \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 78 9f 7c f5\s+vcvttph2uw \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 79 18 7c f5\s+vcvttph2w \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 79 1f 7c f5\s+vcvttph2w \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 79 9f 7c f5\s+vcvttph2w \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 7a 18 5b f5\s+vcvttps2dq \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 7a 1f 5b f5\s+vcvttps2dq \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 7a 9f 5b f5\s+vcvttps2dq \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 78 18 78 f5\s+vcvttps2udq \{sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 78 1f 78 f5\s+vcvttps2udq \{sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 78 9f 78 f5\s+vcvttps2udq \{sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 79 18 7a f5\s+vcvttps2qq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 79 1f 7a f5\s+vcvttps2qq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 79 9f 7a f5\s+vcvttps2qq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 01 79 18 78 f5\s+vcvttps2uqq \{sae\},%xmm29,%ymm30
+\s*[a-f0-9]+:\s*62 01 79 1f 78 f5\s+vcvttps2uqq \{sae\},%xmm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 01 79 9f 78 f5\s+vcvttps2uqq \{sae\},%xmm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 7b 18 7d f5\s+vcvtuw2ph \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 7b 3f 7d f5\s+vcvtuw2ph \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 7b ff 7d f5\s+vcvtuw2ph \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+\s*[a-f0-9]+:\s*62 05 7a 18 7d f5\s+vcvtw2ph \{rn-sae\},%ymm29,%ymm30
+\s*[a-f0-9]+:\s*62 05 7a 3f 7d f5\s+vcvtw2ph \{rd-sae\},%ymm29,%ymm30\{%k7\}
+\s*[a-f0-9]+:\s*62 05 7a ff 7d f5\s+vcvtw2ph \{rz-sae\},%ymm29,%ymm30\{%k7\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.s b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.s
new file mode 100644
index 00000000000..7bd4082c23c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_2-rounding.s
@@ -0,0 +1,350 @@ 
+# Check 64bit AVX10.2 instructions
+
+	.text
+_start:
+	.irp m, pd, ph, ps
+	vcmp\m	$123, {sae}, %ymm28, %ymm29, %k5
+	vcmp\m	$123, {sae}, %ymm28, %ymm29, %k5{%k7}
+	vgetexp\m	{sae}, %ymm29, %ymm30
+	vgetexp\m	{sae}, %ymm29, %ymm30{%k7}
+	vgetexp\m	{sae}, %ymm29, %ymm30{%k7}{z}
+	vsqrt\m	{rn-sae}, %ymm29, %ymm30
+	vsqrt\m	{rd-sae}, %ymm29, %ymm30{%k7}
+	vsqrt\m	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp a, add, div, mul, scalef, sub
+	.irp m, pd, ph, ps
+	v\a\m	{rn-sae}, %ymm28, %ymm29, %ymm30
+	v\a\m	{rd-sae}, %ymm28, %ymm29, %ymm30{%k7}
+	v\a\m	{rz-sae}, %ymm28, %ymm29, %ymm30{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, max, min
+	.irp m, pd, ph, ps
+	v\a\m	{sae}, %ymm28, %ymm29, %ymm30
+	v\a\m	{sae}, %ymm28, %ymm29, %ymm30{%k7}
+	v\a\m	{sae}, %ymm28, %ymm29, %ymm30{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, getmant, reduce, rndscale
+	.irp m, pd, ph, ps
+	v\a\m	$123, {sae}, %ymm29, %ymm30
+	v\a\m	$123, {sae}, %ymm29, %ymm30{%k7}
+	v\a\m	$123, {sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, madd, maddsub, msub, msubadd, nmadd, nmsub
+	.irp n, 132, 213, 231
+	.irp m, pd, ph, ps
+	vf\a\n\m	{rn-sae}, %ymm28, %ymm29, %ymm30
+	vf\a\n\m	{rd-sae}, %ymm28, %ymm29, %ymm30{%k7}
+	vf\a\n\m	{rz-sae}, %ymm28, %ymm29, %ymm30{%k7}{z}
+	.endr
+	.endr
+	.endr
+
+	.irp a, fixupimm, range
+	.irp m, pd, ps
+	v\a\m	$123, {sae}, %ymm28, %ymm29, %ymm30
+	v\a\m	$123, {sae}, %ymm28, %ymm29, %ymm30{%k7}
+	v\a\m	$123, {sae}, %ymm28, %ymm29, %ymm30{%k7}{z}
+	.endr
+	.endr
+
+	.irp a, cmadd, cmul, madd, mul
+	vf\a\()cph	{rn-sae}, %ymm28, %ymm29, %ymm30
+	vf\a\()cph	{rd-sae}, %ymm28, %ymm29, %ymm30{%k7}
+	vf\a\()cph	{rz-sae}, %ymm28, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp n, dq, udq
+	vcvt\n\()2ph	{rn-sae}, %ymm29, %xmm30
+	vcvt\n\()2ph	{rd-sae}, %ymm29, %xmm30{%k7}
+	vcvt\n\()2ph	{rz-sae}, %ymm29, %xmm30{%k7}{z}
+
+	vcvt\n\()2ps	{rn-sae}, %ymm29, %ymm30
+	vcvt\n\()2ps	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvt\n\()2ps	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, dq, ph, ps, udq
+	vcvtpd2\m	{rn-sae}, %ymm29, %xmm30
+	vcvtpd2\m	{rd-sae}, %ymm29, %xmm30{%k7}
+	vcvtpd2\m	{rz-sae}, %ymm29, %xmm30{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvtpd2\m	{rn-sae}, %ymm29, %ymm30
+	vcvtpd2\m	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvtpd2\m	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvtph2\m	{rn-sae}, %xmm29, %ymm30
+	vcvtph2\m	{rd-sae}, %xmm29, %ymm30{%k7}
+	vcvtph2\m	{rz-sae}, %xmm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, pd, ps, psx
+	vcvtph2\m	{sae}, %xmm29, %ymm30
+	vcvtph2\m	{sae}, %xmm29, %ymm30{%k7}
+	vcvtph2\m	{sae}, %xmm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, uw, w
+	vcvtph2\m	{rn-sae}, %ymm29, %ymm30
+	vcvtph2\m	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvtph2\m	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, dq, udq
+	vcvtps2\m	{rn-sae}, %ymm29, %ymm30
+	vcvtps2\m	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvtps2\m	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	vcvtps2pd	{sae}, %xmm29, %ymm30
+	vcvtps2pd	{sae}, %xmm29, %ymm30{%k7}
+	vcvtps2pd	{sae}, %xmm29, %ymm30{%k7}{z}
+
+	vcvtps2phx	{rn-sae}, %ymm29, %xmm30
+	vcvtps2phx	{rd-sae}, %ymm29, %xmm30{%k7}
+	vcvtps2phx	{rz-sae}, %ymm29, %xmm30{%k7}{z}
+
+	.irp m, qq, uqq
+	vcvtps2\m	{rn-sae}, %xmm29, %ymm30
+	vcvtps2\m	{rd-sae}, %xmm29, %ymm30{%k7}
+	vcvtps2\m	{rz-sae}, %xmm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp n, qq, uqq
+	vcvt\n\()2pd	{rn-sae}, %ymm29, %ymm30
+	vcvt\n\()2pd	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvt\n\()2pd	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+
+	.irp m, ph, ps
+	vcvt\n\()2\m	{rn-sae}, %ymm29, %xmm30
+	vcvt\n\()2\m	{rd-sae}, %ymm29, %xmm30{%k7}
+	vcvt\n\()2\m	{rz-sae}, %ymm29, %xmm30{%k7}{z}
+	.endr
+	.endr
+
+	.irp m, dq, udq
+	vcvttpd2\m	{sae}, %ymm29, %xmm30
+	vcvttpd2\m	{sae}, %ymm29, %xmm30{%k7}
+	vcvttpd2\m	{sae}, %ymm29, %xmm30{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttpd2\m	{sae}, %ymm29, %ymm30
+	vcvttpd2\m	{sae}, %ymm29, %ymm30{%k7}
+	vcvttpd2\m	{sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvttph2\m	{sae}, %xmm29, %ymm30
+	vcvttph2\m	{sae}, %xmm29, %ymm30{%k7}
+	vcvttph2\m	{sae}, %xmm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, uw, w
+	vcvttph2\m	{sae}, %ymm29, %ymm30
+	vcvttph2\m	{sae}, %ymm29, %ymm30{%k7}
+	vcvttph2\m	{sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, dq, udq
+	vcvttps2\m	{sae}, %ymm29, %ymm30
+	vcvttps2\m	{sae}, %ymm29, %ymm30{%k7}
+	vcvttps2\m	{sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttps2\m	{sae}, %xmm29, %ymm30
+	vcvttps2\m	{sae}, %xmm29, %ymm30{%k7}
+	vcvttps2\m	{sae}, %xmm29, %ymm30{%k7}{z}
+	.endr
+
+	.irp n, uw, w
+	vcvt\n\()2ph	{rn-sae}, %ymm29, %ymm30
+	vcvt\n\()2ph	{rd-sae}, %ymm29, %ymm30{%k7}
+	vcvt\n\()2ph	{rz-sae}, %ymm29, %ymm30{%k7}{z}
+	.endr
+
+	.intel_syntax noprefix
+	.irp m, pd, ph, ps
+	vcmp\m	k5, ymm29, ymm28{sae}, 123
+	vcmp\m	k5{k7}, ymm29, ymm28{sae}, 123
+	vgetexp\m	ymm30, ymm29{sae}
+	vgetexp\m	ymm30{k7}, ymm29{sae}
+	vgetexp\m	ymm30{k7}{z}, ymm29{sae}
+	vsqrt\m	ymm30, ymm29{rn-sae}
+	vsqrt\m	ymm30{k7}, ymm29{rd-sae}
+	vsqrt\m	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	.irp a, add, div, mul, scalef, sub
+	.irp m, pd, ph, ps
+	v\a\m	ymm30, ymm29, ymm28{rn-sae}
+	v\a\m	ymm30{k7}, ymm29, ymm28{rd-sae}
+	v\a\m	ymm30{k7}{z}, ymm29, ymm28{rz-sae}
+	.endr
+	.endr
+
+	.irp a, max, min
+	.irp m, pd, ph, ps
+	v\a\m	ymm30, ymm29, ymm28, {sae}
+	v\a\m	ymm30{k7}, ymm29, ymm28, {sae}
+	v\a\m	ymm30{k7}{z}, ymm29, ymm28, {sae}
+	.endr
+	.endr
+
+	.irp a, getmant, reduce, rndscale
+	.irp m, pd, ph, ps
+	v\a\m	ymm30, ymm29{sae}, 123
+	v\a\m	ymm30{k7}, ymm29{sae}, 123
+	v\a\m	ymm30{k7}{z}, ymm29{sae}, 123
+	.endr
+	.endr
+
+	.irp a, madd, maddsub, msub, msubadd, nmadd, nmsub
+	.irp n, 132, 213, 231
+	.irp m, pd, ph, ps
+	vf\a\n\m	ymm30, ymm29, ymm28{rn-sae}
+	vf\a\n\m	ymm30{k7}, ymm29, ymm28{rd-sae}
+	vf\a\n\m	ymm30{k7}{z}, ymm29, ymm28{rz-sae}
+	.endr
+	.endr
+	.endr
+
+	.irp a, fixupimm, range
+	.irp m, pd, ps
+	v\a\m	ymm30, ymm29, ymm28{sae}, 123
+	v\a\m	ymm30{k7}, ymm29, ymm28{sae}, 123
+	v\a\m	ymm30{k7}{z}, ymm29, ymm28{sae}, 123
+	.endr
+	.endr
+
+	.irp a, cmadd, cmul, madd, mul
+	vf\a\()cph	ymm30, ymm29, ymm28{rn-sae}
+	vf\a\()cph	ymm30{k7}, ymm29, ymm28{rd-sae}
+	vf\a\()cph	ymm30{k7}{z}, ymm29, ymm28{rz-sae}
+	.endr
+
+	.irp n, dq, udq
+	vcvt\n\()2ph	xmm30, ymm29{rn-sae}
+	vcvt\n\()2ph	xmm30{k7}, ymm29{rd-sae}
+	vcvt\n\()2ph	xmm30{k7}{z}, ymm29{rz-sae}
+
+	vcvt\n\()2ps	ymm30, ymm29{rn-sae}
+	vcvt\n\()2ps	ymm30{k7}, ymm29{rd-sae}
+	vcvt\n\()2ps	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	.irp m, dq, ph, ps, udq
+	vcvtpd2\m	xmm30, ymm29{rn-sae}
+	vcvtpd2\m	xmm30{k7}, ymm29{rd-sae}
+	vcvtpd2\m	xmm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvtpd2\m	ymm30, ymm29{rn-sae}
+	vcvtpd2\m	ymm30{k7}, ymm29{rd-sae}
+	vcvtpd2\m	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvtph2\m	ymm30, xmm29{rn-sae}
+	vcvtph2\m	ymm30{k7}, xmm29{rd-sae}
+	vcvtph2\m	ymm30{k7}{z}, xmm29{rz-sae}
+	.endr
+
+	.irp m, pd, ps, psx
+	vcvtph2\m	ymm30, xmm29{sae}
+	vcvtph2\m	ymm30{k7}, xmm29{sae}
+	vcvtph2\m	ymm30{k7}{z}, xmm29{sae}
+	.endr
+
+	.irp m, uw, w
+	vcvtph2\m	ymm30, ymm29{rn-sae}
+	vcvtph2\m	ymm30{k7}, ymm29{rd-sae}
+	vcvtph2\m	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	.irp m, dq, udq
+	vcvtps2\m	ymm30, ymm29{rn-sae}
+	vcvtps2\m	ymm30{k7}, ymm29{rd-sae}
+	vcvtps2\m	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
+
+	vcvtps2pd	ymm30, xmm29{sae}
+	vcvtps2pd	ymm30{k7}, xmm29{sae}
+	vcvtps2pd	ymm30{k7}{z}, xmm29{sae}
+
+	vcvtps2phx	xmm30, ymm29{rn-sae}
+	vcvtps2phx	xmm30{k7}, ymm29{rd-sae}
+	vcvtps2phx	xmm30{k7}{z}, ymm29{rz-sae}
+
+	.irp m, qq, uqq
+	vcvtps2\m	ymm30, xmm29{rn-sae}
+	vcvtps2\m	ymm30{k7}, xmm29{rd-sae}
+	vcvtps2\m	ymm30{k7}{z}, xmm29{rz-sae}
+	.endr
+
+	.irp n, qq, uqq
+	vcvt\n\()2pd	ymm30, ymm29{rn-sae}
+	vcvt\n\()2pd	ymm30{k7}, ymm29{rd-sae}
+	vcvt\n\()2pd	ymm30{k7}{z}, ymm29{rz-sae}
+
+	.irp m, ph, ps
+	vcvt\n\()2\m	xmm30, ymm29{rn-sae}
+	vcvt\n\()2\m	xmm30{k7}, ymm29{rd-sae}
+	vcvt\n\()2\m	xmm30{k7}{z}, ymm29{rz-sae}
+	.endr
+	.endr
+
+	.irp m, dq, udq
+	vcvttpd2\m	xmm30, ymm29{sae}
+	vcvttpd2\m	xmm30{k7}, ymm29{sae}
+	vcvttpd2\m	xmm30{k7}{z}, ymm29{sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttpd2\m	ymm30, ymm29{sae}
+	vcvttpd2\m	ymm30{k7}, ymm29{sae}
+	vcvttpd2\m	ymm30{k7}{z}, ymm29{sae}
+	.endr
+
+	.irp m, dq, qq, udq, uqq
+	vcvttph2\m	ymm30, xmm29{sae}
+	vcvttph2\m	ymm30{k7}, xmm29{sae}
+	vcvttph2\m	ymm30{k7}{z}, xmm29{sae}
+	.endr
+
+	.irp m, uw, w
+	vcvttph2\m	ymm30, ymm29{sae}
+	vcvttph2\m	ymm30{k7}, ymm29{sae}
+	vcvttph2\m	ymm30{k7}{z}, ymm29{sae}
+	.endr
+
+	.irp m, dq, udq
+	vcvttps2\m	ymm30, ymm29{sae}
+	vcvttps2\m	ymm30{k7}, ymm29{sae}
+	vcvttps2\m	ymm30{k7}{z}, ymm29{sae}
+	.endr
+
+	.irp m, qq, uqq
+	vcvttps2\m	ymm30, xmm29{sae}
+	vcvttps2\m	ymm30{k7}, xmm29{sae}
+	vcvttps2\m	ymm30{k7}{z}, xmm29{sae}
+	.endr
+
+	.irp n, uw, w
+	vcvt\n\()2ph	ymm30, ymm29{rn-sae}
+	vcvt\n\()2ph	ymm30{k7}, ymm29{rd-sae}
+	vcvt\n\()2ph	ymm30{k7}{z}, ymm29{rz-sae}
+	.endr
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 57cb4aa165a..86e7f4a75b3 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -498,6 +498,8 @@  run_dump_test "x86-64-pbndkb-intel"
 run_dump_test "x86-64-user_msr"
 run_dump_test "x86-64-user_msr-intel"
 run_list_test "x86-64-user_msr-inval"
+run_dump_test "x86-64-avx10_2-rounding"
+run_dump_test "x86-64-avx10_2-rounding-intel"
 run_dump_test "x86-64-clzero"
 run_dump_test "x86-64-mwaitx-bdver4"
 run_list_test "x86-64-mwaitx-reg"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 59ec771369a..42154409d55 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -229,6 +229,7 @@  struct instr_info
     bool b;
     bool no_broadcast;
     bool nf;
+    bool u;
   }
   vex;
 
@@ -9031,6 +9032,8 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
       if (!(*ins->codep & 0x4))
 	ins->rex2 |= REX_X;
 
+      ins->vex.u = *ins->codep & 0x4;
+
       switch ((*ins->codep & 0x3))
 	{
 	case 0:
@@ -9064,9 +9067,9 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
       if (ins->address_mode != mode_64bit)
 	{
 	  /* Report bad for !evex_default and when two fixed values of evex
-	     change..  */
-	  if (ins->evex_type != evex_default
-	      || (ins->rex2 & (REX_B | REX_X)))
+	     change.  */
+	  if (ins->evex_type != evex_default || (ins->rex2 & REX_B)
+	      || ((ins->rex2 & REX_X) && (ins->modrm.mod != 3)))
 	    return &bad_opcode;
 	  /* In 16/32-bit mode silently ignore following bits.  */
 	  ins->rex &= ~REX_B;
@@ -9088,14 +9091,22 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
       if (!fetch_modrm (ins))
 	return &err_opcode;
 
-      if (ins->modrm.mod == 3 && (ins->rex2 & REX_X))
+      /* When modrm.mod != 3, the U bit is used by APX for bit X4.
+	 When modrm.mod == 3, the U bit is used by AVX10.  The U bit and
+	 the b bit should not be zero at the same time.  */
+      if (ins->modrm.mod == 3 && !ins->vex.u && !ins->vex.b)
 	return &bad_opcode;
 
       /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
 	 which has the same encoding as vex.length == 128 and they can share
 	 the same processing with vex.length in OP_VEX.  */
       if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
-	ins->vex.length = 512;
+	{
+	  if (ins->vex.u)
+	    ins->vex.length = 512;
+	  else
+	    ins->vex.length = 256;
+	}
       else
 	{
 	  switch (ins->vex.ll)
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 7b740553c34..565aae722f8 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -241,6 +241,8 @@  static const dependency isa_dependencies[] =
   { "AVX10_1",
     "AVX512VL|AVX512DQ|AVX512CD|AVX512VBMI|AVX512_VBMI2|AVX512IFMA"
     "|AVX512_VNNI|AVX512_BF16|AVX512_FP16|AVX512_VPOPCNTDQ|AVX512_BITALG" },
+  { "AVX10_2",
+    "AVX10_1" },
   { "SEV_ES",
     "SVME" },
   { "SNP",
@@ -402,6 +404,7 @@  static bitfield cpu_flags[] =
   BITFIELD (LKGS),
   BITFIELD (USER_MSR),
   BITFIELD (APX_F),
+  BITFIELD (AVX10_2),
   BITFIELD (MWAITX),
   BITFIELD (CLZERO),
   BITFIELD (OSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index db5ca36b8e0..2785cc304a8 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -321,6 +321,8 @@  enum i386_cpu
   CpuAVX512VL,
   /* Intel APX_F Instructions support required.  */
   CpuAPX_F,
+  /* Intel AVX10.2 Instructions support required.  */
+  CpuAVX10_2,
   /* Not supported in the 64bit mode  */
   CpuNo64,
 
@@ -357,6 +359,7 @@  enum i386_cpu
 		   cpuavx512f:1, \
 		   cpuavx512vl:1, \
 		   cpuapx_f:1, \
+		   cpuavx10_2:1, \
       /* NOTE: This field needs to remain last. */ \
 		   cpuno64:1
 
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 97978fe75e0..23d61fb6a39 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -156,6 +156,8 @@ 
 // substantially similar), depending on what encoding was requested.
 #define APX_F(cpuid) cpuid&(cpuid|APX_F)
 
+#define AVX10_2(cpuid) cpuid&(cpuid|AVX10_2)
+
 // The EVEX purpose of StaticRounding appears only together with SAE. Re-use
 // the bit to mark commutative VEX encodings where swapping the source
 // operands may allow to switch from 3-byte to 2-byte VEX encoding.
@@ -1991,9 +1993,9 @@  vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Uns
 <fma:opc, 132:10, 213:20, 231:30>
 
 <sdh:cpu:cpudq:fma:ppfx:spfx:pfx:spc1:spc2:opc:vex:vexlig:vexw:elem, +
-    s:AVX512F:AVX512DQ:FMA|AVX512F::f3:66:Space0F:Space0F38:0:Vex|EVexDYN:VexLIG|EVexLIG:VexW0:Dword, +
-    d:AVX512F:AVX512DQ:FMA|AVX512F:66:f2:66:Space0F:Space0F38:1:Vex|EVexDYN:VexLIG|EVexLIG:VexW1:Qword, +
-    h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::EVexMap5:EVexMap6:0::EVexLIG:VexW0:Word>
+    s:AVX10_2(AVX512F):AVX10_2(AVX512DQ):FMA|AVX512F|AVX10_2::f3:66:Space0F:Space0F38:0:Vex|EVexDYN:VexLIG|EVexLIG:VexW0:Dword, +
+    d:AVX10_2(AVX512F):AVX10_2(AVX512DQ):FMA|AVX512F|AVX10_2:66:f2:66:Space0F:Space0F38:1:Vex|EVexDYN:VexLIG|EVexLIG:VexW1:Qword, +
+    h:AVX10_2(AVX512_FP16):AVX10_2(AVX512_FP16):AVX10_2(AVX512_FP16)::f3::EVexMap5:EVexMap6:0::EVexLIG:VexW0:Word>
 
 vfmadd<fma>p<sdh>, 0x6688 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfmadd<fma>s<sdh>, 0x6689 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
@@ -2290,12 +2292,12 @@  vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDY
 // NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain
 //       in sync with <Vxy>, for match_template()'s EVEX-to-VEX lowering to
 //       continue to work.
-<Exy:vl:attr:sr:sae:src:dst, +
-    $z::EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, +
-    $i:AVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, +
-    $a:AVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegXMM, +
-    x:AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, +
-    y:AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM>
+<Exy:cpu:cpudq:cpufp:cpubf:attr:sr:sae:src:dst, +
+    $z:AVX512F:AVX512DQ:AVX512_FP16:AVX512_BF16:EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, +
+    $i:AVX10_2(AVX512VL):AVX512DQ&(AVX512VL|AVX10_2):AVX512_FP16&(AVX512VL|AVX10_2):AVX512_BF16&AVX512VL:Disp8ShiftVL|IntelSyntax:StaticRounding|SAE:SAE:RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, +
+    $a:AVX10_2(AVX512VL):AVX512DQ&(AVX512VL|AVX10_2):AVX512_FP16&(AVX512VL|AVX10_2):AVX512_BF16&AVX512VL:Disp8ShiftVL|ATTSyntax:StaticRounding|SAE:SAE:RegXMM|RegYMM|BaseIndex:RegXMM, +
+    x:AVX512VL:AVX512DQ&AVX512VL:AVX512_FP16&AVX512VL:AVX512_BF16&AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, +
+    y:AVX10_2(AVX512VL):AVX512DQ&(AVX512VL|AVX10_2):AVX512_FP16&AVX512VL:AVX512_BF16&AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:StaticRounding|SAE:SAE:RegYMM|Unspecified|BaseIndex:RegXMM>
 
 kand<bw>, 0x<bw:kpfx>41, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
 kandn<bw>, 0x<bw:kpfx>42, <bw:kcpu>, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
@@ -2356,8 +2358,8 @@  vbroadcastsd, 0x6619, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift=3|NoS
 vpbroadcastq, 0x6659, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpbroadcast<dq>, 0x667c, AVX512F, Modrm|Masking|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM }
 
-vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpp<sd>, 0x<sd:ppfx>C2, AVX512F, Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, AVX10_2(AVX512F), Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmpp<sd>, 0x<sd:ppfx>C2, AVX10_2(AVX512F), Modrm|Masking|Space0F|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
 
 vcmp<frel>s<sd>, 0x<sd:spfx>C2/0x<frel:imm>, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask }
 vcmps<sd>, 0x<sd:spfx>C2, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask }
@@ -2382,18 +2384,18 @@  vscatterqps, 0x66A3, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|VexW0|Di
 vcvtdq2pd, 0xF3E6, AVX512F, Modrm|EVex=1|Masking|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=1|Masking|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 
-vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtps2udq, 0x79, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtdq2ps, 0x5B, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtps2udq, 0x79, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vcvtpd2dq<Exy>, 0xf2e6, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
+vcvtpd2dq<Exy>, 0xf2e6, <Exy:cpu>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
 
-vcvtpd2ps<Exy>, 0x665a, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
+vcvtpd2ps<Exy>, 0x665a, <Exy:cpu>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
 
-vcvtpd2udq<Exy>, 0x79, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
+vcvtpd2udq<Exy>, 0x79, <Exy:cpu>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
 
 vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM }
 
-vcvtps2dq, 0x665B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtps2dq, 0x665B, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvtps2pd, 0x5A, AVX512F, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 
@@ -2420,16 +2422,16 @@  vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf
 
 vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcvttpd2dq<Exy>, 0x66e6, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> }
-vcvttpd2udq<Exy>, 0x78, AVX512F&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> }
+vcvttpd2dq<Exy>, 0x66e6, <Exy:cpu>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> }
+vcvttpd2udq<Exy>, 0x78, <Exy:cpu>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> }
 
-vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvttps2udq, 0x78, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttps2dq, 0xF35B, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttps2udq, 0x78, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvtts<sd>2si, 0x<sd:spfx>2c, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 }
 vcvtts<sdh>2usi, 0x<sdh:spfx>78, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 }
 
-vcvtudq2ps, 0xF27A, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtudq2ps, 0xF27A, AVX10_2(AVX512F), Modrm|Masking|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vexpandpd, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpexpandq, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -2443,7 +2445,7 @@  vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|N
 vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
 vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
 
-vfixupimmp<sd>, 0x6654, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfixupimmp<sd>, 0x6654, AVX10_2(AVX512F), Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfixupimms<sd>, 0x6655, AVX512F, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
 
 vgetmantp<sdh>, 0x<sdh:pfx>26, <sdh:cpu>, Modrm|Masking|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -2723,10 +2725,10 @@  vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp
 vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 
 vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vcvtph2ps, 0x6613, AVX10_2(AVX512VL), Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Unspecified|BaseIndex, RegYMM }
 
 vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
+vcvtps2pd, 0x5A, AVX10_2(AVX512VL), Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 
 vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
 vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex }
@@ -2908,12 +2910,12 @@  vptestnm<bw>, 0xf326, AVX512BW, Modrm|Masking|Space0F38|Src1VVVV|<bw:vexw>|Disp8
 
 // AVX512DQ instructions.
 
-<xyz:vl:attr:sr:att:src, +
-    $i::Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, +
-    $a::Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|BaseIndex, +
-    z::EVex512|Disp8MemShift=6:StaticRounding|SAE:ATTSyntax:RegZMM|Unspecified|BaseIndex, +
-    x:AVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, +
-    y:AVX512VL:EVex256|Disp8MemShift=5::ATTSyntax:RegYMM|Unspecified|BaseIndex>
+<xyz:cpu:attr:sr:att:src, +
+    $i:AVX10_2(AVX512_FP16):Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, +
+    $a:AVX10_2(AVX512_FP16):Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|BaseIndex, +
+    z:AVX512_FP16:EVex512|Disp8MemShift=6:StaticRounding|SAE:ATTSyntax:RegZMM|Unspecified|BaseIndex, +
+    x:AVX512_FP16&AVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, +
+    y:AVX512_FP16&(AVX512VL|AVX10_2):EVex256|Disp8MemShift=5:StaticRounding|SAE:ATTSyntax:RegYMM|Unspecified|BaseIndex>
 
 kadd<bw>, 0x<bw:kpfx>4A, AVX512DQ, Modrm|Vex256|Space0F|Src1VVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask }
 ktest<bw>, 0x<bw:kpfx>99, AVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask }
@@ -2931,32 +2933,32 @@  vbroadcasti32x8, 0x665B, AVX512DQ, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8Me
 vbroadcastf64x2, 0x661A, AVX512DQ, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
 vbroadcasti64x2, 0x665A, AVX512DQ, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
 
-vcvtpd2qq, 0x667B, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtpd2uqq, 0x6679, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtpd2qq, 0x667B, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtpd2uqq, 0x6679, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvtps2qq, 0x667B, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtps2qq, 0x667B, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
+vcvtps2qq, 0x667B, AVX512DQ&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 vcvtps2uqq, 0x6679, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtps2uqq, 0x6679, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
+vcvtps2uqq, 0x6679, AVX512DQ&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 
-vcvtqq2pd, 0xF3E6, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtuqq2pd, 0xF37A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtqq2pd, 0xF3E6, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtuqq2pd, 0xF37A, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vcvtqq2ps<Exy>, 0x5b, AVX512DQ&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
+vcvtqq2ps<Exy>, 0x5b, <Exy:cpudq>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
 
-vcvttpd2qq, 0x667A, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvttpd2uqq, 0x6678, AVX512DQ, Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttpd2qq, 0x667A, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttpd2uqq, 0x6678, AVX10_2(AVX512DQ), Modrm|Masking|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvttps2qq, 0x667A, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttps2qq, 0x667A, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
+vcvttps2qq, 0x667A, AVX512DQ&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 vcvttps2uqq, 0x6678, AVX512DQ, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
 vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
+vcvttps2uqq, 0x6678, AVX512DQ&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
 
-vcvtuqq2ps<Exy>, 0xf27a, AVX512DQ&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
+vcvtuqq2ps<Exy>, 0xf27a, <Exy:cpudq>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
 
 vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
 vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
@@ -2983,7 +2985,7 @@  vpmovm2<dq>, 0xf338, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegMas
 
 vpmullq, 0x6640, AVX512DQ, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
-vrangep<sd>, 0x6650, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vrangep<sd>, 0x6650, AVX10_2(AVX512DQ), Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vranges<sd>, 0x6651, AVX512DQ, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
 
 vreducep<sdh>, 0x<sdh:pfx>56, <sdh:cpudq>, Modrm|Masking|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -3245,7 +3247,7 @@  movdir64b, 0x66f8, MOVDIR64B&APX_F, Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unsp
 
 vcvtne2ps2bf16, 0xf272, AVX512_BF16, Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
-vcvtneps2bf16<Exy>, 0xf372, AVX512_BF16&<Exy:vl>, Modrm|Space0F38|<Exy:attr>|Masking|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> }
+vcvtneps2bf16<Exy>, 0xf372, <Exy:cpubf>, Modrm|Space0F38|<Exy:attr>|Masking|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> }
 
 vdpbf16ps, 0xf352, AVX512_BF16, Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
@@ -3395,59 +3397,59 @@  hreset, 0xf30f3af0c0, HRESET, NoSuf, { Imm8 }
 
 // FP16 (HFNI) instructions.
 
-vfcmaddcph, 0xf256, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfcmaddcph, 0xf256, AVX10_2(AVX512_FP16), Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfcmaddcsh, 0xf257, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfmaddcph, 0xf356, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfmaddcph, 0xf356, AVX10_2(AVX512_FP16), Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfmaddcsh, 0xf357, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfcmulcph, 0xf2d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfcmulcph, 0xf2d6, AVX10_2(AVX512_FP16), Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfcmulcsh, 0xf2d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfmulcph, 0xf3d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfmulcph, 0xf3d6, AVX10_2(AVX512_FP16), Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfmulcsh, 0xf3d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpph, 0xc2, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX10_2(AVX512_FP16), Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmpph, 0xc2, AVX10_2(AVX512_FP16), Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
 
 vcmp<frel>sh, 0xf3c2/0x<frel:imm>, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
 vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
 
-vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
-vcvtudq2ph<Exy>, 0xf27a, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtdq2ph<Exy>, 0x5b, <Exy:cpufp>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtudq2ph<Exy>, 0xf27a, <Exy:cpufp>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
 
-vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
-vcvtuqq2ph<xyz>, 0xf27a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtqq2ph<xyz>, 0x5b, <xyz:cpu>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtuqq2ph<xyz>, 0xf27a, <xyz:cpu>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
 
-vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtpd2ph<xyz>, 0x665a, <xyz:cpu>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
 
-vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtps2phx<Exy>, 0x661d, <Exy:cpufp>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
 
-vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtw2ph, 0xf37d, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtuw2ph, 0xf27d, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2dq, 0x665b, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
 vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2udq, 0x79, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
 vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2qq, 0x667b, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
 vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2uqq, 0x6679, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
 vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2pd, 0x5a, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
 vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtph2w, 0x667d, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtph2uw, 0x7d, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
 vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
@@ -3464,31 +3466,31 @@  vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp
 vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 
 vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvttph2dq, 0xf35b, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
 vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvttph2udq, 0x78, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
 vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvttph2qq, 0x667a, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
 vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvttph2uqq, 0x6678, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
 vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
 vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2psx, 0x6613, AVX512_FP16&(AVX512VL|AVX10_2), Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
 vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttph2w, 0x667c, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttph2uw, 0x7c, AVX10_2(AVX512_FP16), Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 
-vfpclassph<xyz>, 0x66, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8|Imm8S, <xyz:src>|Word, RegMask }
+vfpclassph<xyz>, 0x66, <xyz:cpu>, Modrm|<xyz:attr>|Masking|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8|Imm8S, <xyz:src>|Word, RegMask }
 
 vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM }
 vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 }