[v5] RISC-V: Add support for RISC-V Profiles.

Message ID 20240807154345.12243-1-jiawei@iscas.ac.cn
State New
Headers
Series [v5] RISC-V: Add support for RISC-V Profiles. |

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Commit Message

Jiawei Aug. 7, 2024, 3:43 p.m. UTC
  Supports RISC-V profiles[1] in -march option.

Default input set the profile before other formal extensions.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

version log: Adjust New info in right place, fix format issue.

bfd/ChangeLog:

	* elfxx-riscv.c (struct riscv_profiles): New struct.
	(riscv_handle_profiles): New handle function.
	(riscv_parse_subset): Add Profiles parse.
	* elfxx-riscv.h (riscv_handle_profiles): New prototype.

gas/ChangeLog:

	* NEWS: Add RISC-V Profiles support.
	* doc/as.texi: Add Profiles in march option.
	* doc/c-riscv.texi: Add RISC-V Profiles introductions.
	* testsuite/gas/riscv/attribute-15.d: New test.
	* testsuite/gas/riscv/attribute-16.d: New test.

---
 bfd/elfxx-riscv.c                      | 79 ++++++++++++++++++++++++--
 bfd/elfxx-riscv.h                      |  3 +
 gas/NEWS                               |  2 +
 gas/doc/as.texi                        |  2 +-
 gas/doc/c-riscv.texi                   | 14 +++--
 gas/testsuite/gas/riscv/attribute-15.d |  6 ++
 gas/testsuite/gas/riscv/attribute-16.d |  6 ++
 7 files changed, 103 insertions(+), 9 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
 create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
  

Comments

Nelson Chu Sept. 3, 2024, 7:05 a.m. UTC | #1
Basically looks good, I am fine with the current implementation, just some
minor issues probably need to be clarified,

On Wed, Aug 7, 2024 at 11:44 PM Jiawei <jiawei@iscas.ac.cn> wrote:

> Supports RISC-V profiles[1] in -march option.
>
> Default input set the profile before other formal extensions.
>
> [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc


404 link needs to be updated :P


> +/* This table records the mapping form RISC-V Profiles into march
> string.  */
> +static struct riscv_profiles riscv_profiles_table[] =
> +{
> +  /* RVI20U only contains the base extension 'i' as mandatory extension.
> */
> +  {"RVI20U64", "rv64i"},
> +  {"RVI20U32", "rv32i"},
> +
> +  /* RVA20U contains the
> 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
> +     zicclsm,za128rs' as mandatory extensions.  */
> +  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
> +   "_zicclsm_za128rs"},
> +
> +  /* RVA22U contains the
> 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
> +     zihpm,ziccif,ziccrse,ziccamoa,
> zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
> +     zfhmin,zkt' as mandatory extensions.  */
> +  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
> +   "_zicboz_zfhmin_zkt"},
>

According to the commit e8d4709e, RISC-V: Don't allow any uppercase letter
in the arch string - Do the profile strings also need to be lower cases
since they still belong to the -march option?  For example,
-march=rvi20u64+fdc


>
> @@ -2148,6 +2179,45 @@ riscv_set_default_arch (riscv_parse_subset_t *rps)
>      }
>  }
>
> +const char *
> +riscv_handle_profiles (const char *p)
> +{
> +  /* Checking if input string contains a Profiles.
> +     There are two cases use Profiles in -march option:
> +
> +       1. Only use Profiles as -march input
> +       2. Mixed Profiles with other extensions
> +
> +     Use '+' to split Profiles and other extensions.  */
>

Not sure if using `+' as the separator is a good idea, since its usage
seems confused with the `+' in .option arch.  I think maybe we can clarify
the architecture string that must be started with, rv32, rv64, or defined
profile string.  So that the other extensions can simply be attached after
`_'.  That is - startswith (arch, string), string can be "rv32", "rv64", or
profile strings "rvi20u64", ....


> diff --git a/gas/doc/as.texi b/gas/doc/as.texi
> index 0b4109e1149..3240427fabe 100644
> --- a/gas/doc/as.texi
> +++ b/gas/doc/as.texi
> @@ -557,7 +557,7 @@ gcc(1), ld(1), and the Info entries for
> @file{binutils} and @file{ld}.
>
>  @emph{Target RISC-V options:}
>     [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
> -   [@b{-march}=@var{ISA}]
> +   [@b{-march}=@var{ISA/Profiles/Profiles+ISA}]

    [@b{-mabi}=@var{ABI}]
>     [@b{-mlittle-endian}|@b{-mbig-endian}]
>  @end ifset
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index cec7457fe81..6334b637275 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -41,9 +41,10 @@ Generate position-independent code
>  @item -fno-pic
>  Don't generate position-independent code (default)
>
> -@cindex @samp{-march=ISA} option, RISC-V
> -@item -march=ISA
> -Select the base isa, as specified by ISA.  For example -march=rv32ima.
> +@cindex @samp{-march=ISA/Profiles/Profies+ISA} option, RISC-V
> +@item -march=ISA/Profiles/Profiles+ISA
> +Select the base isa, as specified by ISA or Profiles or Profies+ISA.
> +For example -march=rv32ima -march=RVI20U64 -march=RVI20U64+d.
>  If this option and the architecture attributes aren't set, then assembler
>  will check the default configure setting --with-arch=ISA.
>

The ISA means architecture string, and must be start with rv[32|64][i|e|g]
before, so -march=Profiles+ISA looks confused since -march=rvi20u64+rv32i
should be correct according to the rule, but in fact it's an illegal usage
for the current implementation.  Personally, I think the profile strings
belonged to the base isa may be a good idea, which is rv32i, rv32e, rv32g,
rv64i, rv64g, rvi20u64, rvi20u32, rva20u64 or rva22u64.

Thanks
Nelson
  
Jiawei Sept. 4, 2024, 3:11 a.m. UTC | #2
在 2024/9/3 15:05, Nelson Chu 写道:
> Basically looks good, I am fine with the current implementation, just 
> some minor issues probably need to be clarified,
>
> On Wed, Aug 7, 2024 at 11:44 PM Jiawei <jiawei@iscas.ac.cn> wrote:
>
>     Supports RISC-V profiles[1] in -march option.
>
>     Default input set the profile before other formal extensions.
>
>     [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
>
>
> 404 link needs to be updated :P

Thanks for you remark, will use github repo to replace it

https://github.com/riscv/riscv-profiles

>     +/* This table records the mapping form RISC-V Profiles into march
>     string.  */
>     +static struct riscv_profiles riscv_profiles_table[] =
>     +{
>     +  /* RVI20U only contains the base extension 'i' as mandatory
>     extension.  */
>     +  {"RVI20U64", "rv64i"},
>     +  {"RVI20U32", "rv32i"},
>     +
>     +  /* RVA20U contains the
>     'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
>     +     zicclsm,za128rs' as mandatory extensions.  */
>     +  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
>     +   "_zicclsm_za128rs"},
>     +
>     +  /* RVA22U contains the
>     'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
>     +     zihpm,ziccif,ziccrse,ziccamoa,
>     zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
>     +     zfhmin,zkt' as mandatory extensions.  */
>     +  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
>     +  "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>     +   "_zicboz_zfhmin_zkt"},
>
>
> According to the commit e8d4709e, RISC-V: Don't allow any uppercase 
> letter in the arch string - Do the profile strings also need to be 
> lower cases since they still belong to the -march option?  For 
> example, -march=rvi20u64+fdc

The original intention of using uppercase letters is to be consistent 
with the definition of profile naming convention in the specification 
manual. However, llvm upstream used the lowercase letters, perhaps 
maintaining user usage habits is a good choice.

>
>     @@ -2148,6 +2179,45 @@ riscv_set_default_arch
>     (riscv_parse_subset_t *rps)
>          }
>      }
>
>     +const char *
>     +riscv_handle_profiles (const char *p)
>     +{
>     +  /* Checking if input string contains a Profiles.
>     +     There are two cases use Profiles in -march option:
>     +
>     +       1. Only use Profiles as -march input
>     +       2. Mixed Profiles with other extensions
>     +
>     +     Use '+' to split Profiles and other extensions.  */
>
>
> Not sure if using `+' as the separator is a good idea, since its usage 
> seems confused with the `+' in .option arch.  I think maybe we can 
> clarify the architecture string that must be started with, rv32, rv64, 
> or defined profile string.  So that the other extensions can simply be 
> attached after `_'.  That is - startswith (arch, string), string can 
> be "rv32", "rv64", or profile strings "rvi20u64", ....
One of the considerations is just to distinguish Profiles from standard 
ISA extensions.
>
>     diff --git a/gas/doc/as.texi b/gas/doc/as.texi
>     index 0b4109e1149..3240427fabe 100644
>     --- a/gas/doc/as.texi
>     +++ b/gas/doc/as.texi
>     @@ -557,7 +557,7 @@ gcc(1), ld(1), and the Info entries for
>     @file{binutils} and @file{ld}.
>
>      @emph{Target RISC-V options:}
>         [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
>     -   [@b{-march}=@var{ISA}]
>     +   [@b{-march}=@var{ISA/Profiles/Profiles+ISA}] 
>
>         [@b{-mabi}=@var{ABI}]
>         [@b{-mlittle-endian}|@b{-mbig-endian}]
>      @end ifset
>     diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
>     index cec7457fe81..6334b637275 100644
>     --- a/gas/doc/c-riscv.texi
>     +++ b/gas/doc/c-riscv.texi
>     @@ -41,9 +41,10 @@ Generate position-independent code
>      @item -fno-pic
>      Don't generate position-independent code (default)
>
>     -@cindex @samp{-march=ISA} option, RISC-V
>     -@item -march=ISA
>     -Select the base isa, as specified by ISA.  For example
>     -march=rv32ima.
>     +@cindex @samp{-march=ISA/Profiles/Profies+ISA} option, RISC-V
>     +@item -march=ISA/Profiles/Profiles+ISA
>     +Select the base isa, as specified by ISA or Profiles or Profies+ISA.
>     +For example -march=rv32ima -march=RVI20U64 -march=RVI20U64+d.
>      If this option and the architecture attributes aren't set, then
>     assembler
>      will check the default configure setting --with-arch=ISA.
>
>
> The ISA means architecture string, and must be start with 
> rv[32|64][i|e|g] before, so -march=Profiles+ISA looks confused since 
> -march=rvi20u64+rv32i should be correct according to the rule, but in 
> fact it's an illegal usage for the current implementation.  
> Personally, I think the profile strings belonged to the base isa may 
> be a good idea, which is rv32i, rv32e, rv32g, rv64i, rv64g, rvi20u64, 
> rvi20u32, rva20u64 or rva22u64.
> Thanks
> Nelson
Thanks for your suggestions. In fact, we have discussed the format of 
profiles in -march in the riscv toolchain calling convention 
repository,and the final format is not fixed yet.

https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36
  
Nelson Chu Sept. 9, 2024, 1:01 a.m. UTC | #3
On Wed, Sep 4, 2024 at 11:12 AM Jiawei <jiawei@iscas.ac.cn> wrote:

>
> 在 2024/9/3 15:05, Nelson Chu 写道:
>
> Basically looks good, I am fine with the current implementation, just some
> minor issues probably need to be clarified,
>
> On Wed, Aug 7, 2024 at 11:44 PM Jiawei <jiawei@iscas.ac.cn> wrote:
>
>> Supports RISC-V profiles[1] in -march option.
>>
>> Default input set the profile before other formal extensions.
>>
>> [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
>
>
> 404 link needs to be updated :P
>
> Thanks for you remark, will use github repo to replace it
>
> https://github.com/riscv/riscv-profiles
>
>
>
>> +/* This table records the mapping form RISC-V Profiles into march
>> string.  */
>> +static struct riscv_profiles riscv_profiles_table[] =
>> +{
>> +  /* RVI20U only contains the base extension 'i' as mandatory
>> extension.  */
>> +  {"RVI20U64", "rv64i"},
>> +  {"RVI20U32", "rv32i"},
>> +
>> +  /* RVA20U contains the
>> 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
>> +     zicclsm,za128rs' as mandatory extensions.  */
>> +  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_za128rs"},
>> +
>> +  /* RVA22U contains the
>> 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
>> +     zihpm,ziccif,ziccrse,ziccamoa,
>> zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
>> +     zfhmin,zkt' as mandatory extensions.  */
>> +  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>> +   "_zicboz_zfhmin_zkt"},
>>
>
> According to the commit e8d4709e, RISC-V: Don't allow any uppercase letter
> in the arch string - Do the profile strings also need to be lower cases
> since they still belong to the -march option?  For example,
> -march=rvi20u64+fdc
>
> The original intention of using uppercase letters is to be consistent with
> the definition of profile naming convention in the specification manual.
> However, llvm upstream used the lowercase letters, perhaps maintaining user
> usage habits is a good choice.
>
>
>
>>
>> @@ -2148,6 +2179,45 @@ riscv_set_default_arch (riscv_parse_subset_t *rps)
>>      }
>>  }
>>
>> +const char *
>> +riscv_handle_profiles (const char *p)
>> +{
>> +  /* Checking if input string contains a Profiles.
>> +     There are two cases use Profiles in -march option:
>> +
>> +       1. Only use Profiles as -march input
>> +       2. Mixed Profiles with other extensions
>> +
>> +     Use '+' to split Profiles and other extensions.  */
>>
>
> Not sure if using `+' as the separator is a good idea, since its usage
> seems confused with the `+' in .option arch.  I think maybe we can clarify
> the architecture string that must be started with, rv32, rv64, or defined
> profile string.  So that the other extensions can simply be attached after
> `_'.  That is - startswith (arch, string), string can be "rv32", "rv64", or
> profile strings "rvi20u64", ....
>
> One of the considerations is just to distinguish Profiles from standard
> ISA extensions.
>
>
>
>> diff --git a/gas/doc/as.texi b/gas/doc/as.texi
>> index 0b4109e1149..3240427fabe 100644
>> --- a/gas/doc/as.texi
>> +++ b/gas/doc/as.texi
>> @@ -557,7 +557,7 @@ gcc(1), ld(1), and the Info entries for
>> @file{binutils} and @file{ld}.
>>
>>  @emph{Target RISC-V options:}
>>     [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
>> -   [@b{-march}=@var{ISA}]
>> +   [@b{-march}=@var{ISA/Profiles/Profiles+ISA}]
>
>     [@b{-mabi}=@var{ABI}]
>>     [@b{-mlittle-endian}|@b{-mbig-endian}]
>>  @end ifset
>> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
>> index cec7457fe81..6334b637275 100644
>> --- a/gas/doc/c-riscv.texi
>> +++ b/gas/doc/c-riscv.texi
>> @@ -41,9 +41,10 @@ Generate position-independent code
>>  @item -fno-pic
>>  Don't generate position-independent code (default)
>>
>> -@cindex @samp{-march=ISA} option, RISC-V
>> -@item -march=ISA
>> -Select the base isa, as specified by ISA.  For example -march=rv32ima.
>> +@cindex @samp{-march=ISA/Profiles/Profies+ISA} option, RISC-V
>> +@item -march=ISA/Profiles/Profiles+ISA
>> +Select the base isa, as specified by ISA or Profiles or Profies+ISA.
>> +For example -march=rv32ima -march=RVI20U64 -march=RVI20U64+d.
>>  If this option and the architecture attributes aren't set, then assembler
>>  will check the default configure setting --with-arch=ISA.
>>
>
> The ISA means architecture string, and must be start with rv[32|64][i|e|g]
> before, so -march=Profiles+ISA looks confused since -march=rvi20u64+rv32i
> should be correct according to the rule, but in fact it's an illegal usage
> for the current implementation.  Personally, I think the profile strings
> belonged to the base isa may be a good idea, which is rv32i, rv32e, rv32g,
> rv64i, rv64g, rvi20u64, rvi20u32, rva20u64 or rva22u64.
>
> Thanks
> Nelson
>
> Thanks for your suggestions. In fact, we have discussed the format of
> profiles in -march in the riscv toolchain calling convention repository,and
> the final format is not fixed yet.
>
> https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36
>

Thanks, that's great if toolchain convention records the rules.  Routhly
review that the llvm landed patch seems same as the above thoughts,
including,
1. The lower profile names
2. Just using `_' to separate profiles and extra extensions

So it would be great if GNU gcc/binutils also have the same implementations
:-)

Nelson
  

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d517b2ecd3d..96ab82fec5f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1022,6 +1022,12 @@  static const struct elf_reloc_map riscv_reloc_map[] =
   { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* Given a BFD reloc type, return a howto structure.  */
 
 reloc_howto_type *
@@ -1273,6 +1279,31 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {NULL, NULL, NULL}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static struct riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+     zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+     zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+     zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 /* For default_enable field, decide if the extension should
    be enbaled by default.  */
 
@@ -2148,6 +2179,45 @@  riscv_set_default_arch (riscv_parse_subset_t *rps)
     }
 }
 
+const char *
+riscv_handle_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+     There are two cases use Profiles in -march option:
+
+       1. Only use Profiles as -march input
+       2. Mixed Profiles with other extensions
+
+     Use '+' to split Profiles and other extensions.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
+    {
+      const char *match = strstr (p, riscv_profiles_table[i].profile_name);
+      const char *plus_ext = strchr (p, '+');
+      /* Find profile at the beginning.  */
+      if (match != NULL && match == p)
+	{
+	  /* If there's no '+' sign, return the profile_string directly.  */
+	  if (!plus_ext)
+	    return riscv_profiles_table[i].profile_string;
+	  /* If there's a '+' sign, need to add profiles with other ext.  */
+	  else
+	    {
+	      size_t arch_len = (strlen (riscv_profiles_table[i].profile_string)
+				 + strlen (plus_ext));
+	      /* Reset the input string with Profiles mandatory extensions,
+		 end with '_' to connect other additional extensions.  */
+	      char *result = (char *) malloc (arch_len + 2);
+	      strcpy (result, riscv_profiles_table[i].profile_string);
+	      strcat (result, "_");
+	      strcat (result, plus_ext + 1); /* skip the '+'.  */
+	      return result;
+	    }
+	}
+    }
+  return p;
+}
+
+
 /* Function for parsing ISA string.
 
    Return Value:
@@ -2174,18 +2244,19 @@  riscv_parse_subset (riscv_parse_subset_t *rps,
       return riscv_parse_check_conflicts (rps);
     }
 
-  for (p = arch; *p != '\0'; p++)
+   p = riscv_handle_profiles (arch);
+
+  for (const char *q = p; *q != '\0'; q++)
     {
-      if (ISUPPER (*p))
+      if (ISUPPER (*q))
 	{
 	  rps->error_handler
 	    (_("%s: ISA string cannot contain uppercase letters"),
-	     arch);
+	     q);
 	  return false;
 	}
     }
 
-  p = arch;
   if (startswith (p, "rv32"))
     {
       *rps->xlen = 32;
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
index 49be71746b9..40577a664c9 100644
--- a/bfd/elfxx-riscv.h
+++ b/bfd/elfxx-riscv.h
@@ -121,6 +121,9 @@  riscv_multi_subset_supports (riscv_parse_subset_t *, enum riscv_insn_class);
 extern const char *
 riscv_multi_subset_supports_ext (riscv_parse_subset_t *, enum riscv_insn_class);
 
+extern const char *
+riscv_handle_profiles(const char*);
+
 extern void
 riscv_print_extensions (void);
 
diff --git a/gas/NEWS b/gas/NEWS
index 69c6317c486..e0b0aaf78c6 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -2,6 +2,8 @@ 
 
 * Add support for RISC-V CORE-V extension (XCvBitmanip) with version 1.0.
 
+* Add support for RISC-V Profiles RV20/22.
+
 Changes in 2.43:
 
 * Add support for LoongArch .option for fine-grained control of assembly
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 0b4109e1149..3240427fabe 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -557,7 +557,7 @@  gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 
 @emph{Target RISC-V options:}
    [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
-   [@b{-march}=@var{ISA}]
+   [@b{-march}=@var{ISA/Profiles/Profiles+ISA}]
    [@b{-mabi}=@var{ABI}]
    [@b{-mlittle-endian}|@b{-mbig-endian}]
 @end ifset
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index cec7457fe81..6334b637275 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -41,9 +41,10 @@  Generate position-independent code
 @item -fno-pic
 Don't generate position-independent code (default)
 
-@cindex @samp{-march=ISA} option, RISC-V
-@item -march=ISA
-Select the base isa, as specified by ISA.  For example -march=rv32ima.
+@cindex @samp{-march=ISA/Profiles/Profies+ISA} option, RISC-V
+@item -march=ISA/Profiles/Profiles+ISA
+Select the base isa, as specified by ISA or Profiles or Profies+ISA.
+For example -march=rv32ima -march=RVI20U64 -march=RVI20U64+d.
 If this option and the architecture attributes aren't set, then assembler
 will check the default configure setting --with-arch=ISA.
 
@@ -715,7 +716,12 @@  to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
 for the default version of its base ISA.  On the other hand, the architecture
 @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
 which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
-with default versions of the standard extensions.
+with default versions of the standard extensions. All Profiles are expanded
+ to the mandatory extensions it includes then processing.  For example,
+@code{RVI20U32} is expanded to @code{RV32I2P0} for processing, which contains
+the mandatory extensions @code{I} as it defined.  And you can also combine
+Profiles with ISA use +, like @code{RVI20U32+D} is expanded to the
+@code{RV32I2P0_F2P0_D2P0}.
 
 @item Tag_RISCV_unaligned_access (6)
 Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d
new file mode 100644
index 00000000000..61376a75f39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-15.d
@@ -0,0 +1,6 @@ 
+#as: -march=RVA20U64
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d
new file mode 100644
index 00000000000..5da9aa4ab84
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-16.d
@@ -0,0 +1,6 @@ 
+#as: -march=RVI20U32+d
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"