RISC-V: Add support for RISC-V Profiles.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b8f314d1c01..73b83abd021 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1022,6 +1022,12 @@  static const struct elf_reloc_map riscv_reloc_map[] =
   { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* Given a BFD reloc type, return a howto structure.  */
 
 reloc_howto_type *
@@ -1272,6 +1278,31 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {NULL, NULL, NULL}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static struct riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+     zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+     zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+     zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 /* For default_enable field, decide if the extension should
    be enbaled by default.  */
 
@@ -2144,6 +2175,40 @@  riscv_set_default_arch (riscv_parse_subset_t *rps)
     }
 }
 
+const char *
+riscv_handle_profiles (const char * p){
+  /* Checking if input string contains a Profiles.
+     There are two cases use Profiles in -march option
+
+       1. Only use Profiles as -march input
+       2. Mixed Profiles with other extensions
+
+     use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+    const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+    const char* plus_ext = strchr(p, '+');
+    /* Find profile at the begin.  */
+    if (match != NULL && match == p) {
+      /* If there's no '+' sign, return the profile_string directly.  */
+      if(!plus_ext)
+	return riscv_profiles_table[i].profile_string;
+      /* If there's a '+' sign, need to add profiles with other ext.  */
+      else {
+	size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+
+		  strlen(plus_ext);
+	/* Reset the input string with Profiles mandatory extensions,
+	   end with '_' to connect other additional extensions.  */
+	char* result = (char*)malloc(arch_len + 2);
+	strcpy(result, riscv_profiles_table[i].profile_string);
+	strcat(result, "_");
+	strcat(result, plus_ext + 1); /* skip the '+'.  */
+	return result;
+      }
+    }
+  }
+  return p;
+}
+
 /* Function for parsing ISA string.
 
    Return Value:
@@ -2170,18 +2235,19 @@  riscv_parse_subset (riscv_parse_subset_t *rps,
       return riscv_parse_check_conflicts (rps);
     }
 
-  for (p = arch; *p != '\0'; p++)
+   p = riscv_handle_profiles (arch);
+
+  for (const char *q = p; *q != '\0'; q++)
     {
-      if (ISUPPER (*p))
+      if (ISUPPER (*q))
 	{
 	  rps->error_handler
 	    (_("%s: ISA string cannot contain uppercase letters"),
-	     arch);
+	     q);
 	  return false;
 	}
     }
 
-  p = arch;
   if (startswith (p, "rv32"))
     {
       *rps->xlen = 32;
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
index 49be71746b9..40577a664c9 100644
--- a/bfd/elfxx-riscv.h
+++ b/bfd/elfxx-riscv.h
@@ -121,6 +121,9 @@  riscv_multi_subset_supports (riscv_parse_subset_t *, enum riscv_insn_class);
 extern const char *
 riscv_multi_subset_supports_ext (riscv_parse_subset_t *, enum riscv_insn_class);
 
+extern const char *
+riscv_handle_profiles(const char*);
+
 extern void
 riscv_print_extensions (void);
 
diff --git a/gas/NEWS b/gas/NEWS
index b9d742a2375..8143418e970 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -42,6 +42,8 @@  Changes in 2.43:
 * Remove support for RISC-V privileged spec 1.9.1, but linker can still
   recognize it in case of linking old objects.
 
+* Add support for RISC-V Profiles RV20/22.
+
 * Add support for RISC-V Zacas extension with version 1.0.
 
 * Add support for RISC-V Zcmp extension with version 1.0.
diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d
new file mode 100644
index 00000000000..61376a75f39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-15.d
@@ -0,0 +1,6 @@ 
+#as: -march=RVA20U64
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d
new file mode 100644
index 00000000000..5da9aa4ab84
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-16.d
@@ -0,0 +1,6 @@ 
+#as: -march=RVI20U32+d
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"