[v1,4/4] aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)

Message ID 20240704142338.1582659-5-matthieu.longo@arm.com
State Accepted
Headers
Series aarch64: add new Armv9.5-A features and their associated registers (RAS, Debug, Performance Monitor) |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Matthieu Longo July 4, 2024, 2:23 p.m. UTC
  This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
 gas/testsuite/gas/aarch64/sysreg/sysreg.d | 5 +++++
 gas/testsuite/gas/aarch64/sysreg/sysreg.s | 5 +++++
 opcodes/aarch64-sys-regs.def              | 1 +
 3 files changed, 11 insertions(+)
  

Patch

diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
index 54ade34a87e..4fa9f0d559d 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
@@ -11,6 +11,11 @@  Disassembly of section \.text:
 .*:	d53b9c60 	mrs	x0, pmovsclr_el0
 .*:	d51b9e60 	msr	pmovsset_el0, x0
 .*:	d53b9e60 	mrs	x0, pmovsset_el0
+.*:	d5380580 	mrs	x0, id_aa64afr0_el1
+.*:	d53805a0 	mrs	x0, id_aa64afr1_el1
+.*:	d5380500 	mrs	x0, id_aa64dfr0_el1
+.*:	d5380520 	mrs	x0, id_aa64dfr1_el1
+.*:	d5380540 	mrs	x0, id_aa64dfr2_el1
 .*:	d5380140 	mrs	x0, id_dfr0_el1
 .*:	d5380100 	mrs	x0, id_pfr0_el1
 .*:	d5380120 	mrs	x0, id_pfr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
index 9c0fd4ae2fd..cf0461412b5 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
@@ -5,6 +5,11 @@ 
 	rw_sys_reg sys_reg=pmovsclr_el0
 	rw_sys_reg sys_reg=pmovsset_el0
 
+	rw_sys_reg sys_reg=id_aa64afr0_el1 w=0
+	rw_sys_reg sys_reg=id_aa64afr1_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr0_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr1_el1 w=0
+	rw_sys_reg sys_reg=id_aa64dfr2_el1 w=0
 	rw_sys_reg sys_reg=id_dfr0_el1 w=0
 	rw_sys_reg sys_reg=id_pfr0_el1 w=0
 	rw_sys_reg sys_reg=id_pfr1_el1 w=0
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index cd2f1ac8516..6a554d9a12a 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -519,6 +519,7 @@ 
   SYSREG ("id_aa64afr1_el1",	CPENC (3,0,0,5,5),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr0_el1",	CPENC (3,0,0,5,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64dfr1_el1",	CPENC (3,0,0,5,1),	F_REG_READ,		AARCH64_NO_FEATURES)
+  SYSREG ("id_aa64dfr2_el1",	CPENC (3,0,0,5,2),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar0_el1",	CPENC (3,0,0,6,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar1_el1",	CPENC (3,0,0,6,1),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar2_el1",	CPENC (3,0,0,6,2),	F_REG_READ,		AARCH64_NO_FEATURES)