[v1,07/12] aarch64: Add support for sve2p1 zipq[1-2] instructions.

Message ID 20240704124045.306577-8-srinath.parvathaneni@arm.com
State New
Headers
Series aarch64: Add support for remaining sve2p1 instructions. |

Checks

Context Check Description
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linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
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Commit Message

Srinath Parvathaneni July 4, 2024, 12:40 p.m. UTC
  This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is
available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d |  2 +-
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 24 ++++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 12 ++++++++++
 gas/testsuite/gas/aarch64/sve2p1-6.d         | 18 ++++++++++++++-
 gas/testsuite/gas/aarch64/sve2p1-6.s         | 18 +++++++++++++++
 opcodes/aarch64-tbl.h                        |  2 ++
 6 files changed, 74 insertions(+), 2 deletions(-)
  

Patch

diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
index 0971a587815..db35ae7acb3 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -1,3 +1,3 @@ 
-#name: Test of illegal SVE2.1 tblq, uzpq1 and uzpq2 instruction.
+#name: Test of illegal SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
 #as: -march=armv9.4-a
 #error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
index c784ca6c891..55987acc8b0 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -40,3 +40,27 @@ 
 .*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.h,{z0.h-z1.h},z0.h'
 .*: Error: expected an SVE vector register at operand 1 -- `uzpq2 {z0.s},z31.s,z0.b'
 .*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `zipq1 z31.s,z0.b,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	zipq1 z31.b, z0.b, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	zipq1 z31.h, z0.h, z0.h
+.*: Info:    	zipq1 z31.s, z0.s, z0.s
+.*: Info:    	zipq1 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.h,{z0.b-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `zipq1 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `zipq2 z31.s,z0.b,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	zipq2 z31.b, z0.b, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	zipq2 z31.h, z0.h, z0.h
+.*: Info:    	zipq2 z31.s, z0.s, z0.s
+.*: Info:    	zipq2 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.h,{z0.b-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `zipq2 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
index 8a6df867726..f79dfac78d4 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -16,3 +16,15 @@  uzpq2 z0.s, {z0.s, z1.s}, z0.s
 uzpq2 z0.h, {z0.h - z1.h}, z0.h
 uzpq2 {z0.s}, z31.s, z0.b
 uzpq2 z0.b, {z0.b}, {z31.b}
+zipq1 z0.s, {z0.b}, z0.b
+zipq1 z31.s, z0.b, z0.h
+zipq1 z0.s, {z0.s, z1.s}, z0.s
+zipq1 z0.h, {z0.b - z1.h}, z0.h
+zipq1 {z0.s}, z31.s, z0.b
+zipq1 z0.b, {z0.b}, {z31.b}
+zipq2 z0.s, {z0.b}, z0.b
+zipq2 z31.s, z0.b, z0.h
+zipq2 z0.s, {z0.s, z1.s}, z0.s
+zipq2 z0.h, {z0.b - z1.h}, z0.h
+zipq2 {z0.s}, z31.s, z0.b
+zipq2 z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index b36515f234c..83ba1426135 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,4 +1,4 @@ 
-#name: Test of SVE2.1 tblq, uzpq1 and uzpq2 instruction.
+#name: Test of SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
 #as: -march=armv9.4-a
 #objdump: -dr
 
@@ -32,3 +32,19 @@ 
 .*:	44dfefff 	uzpq2	z31.d, z31.d, z31.d
 .*:	448fed45 	uzpq2	z5.s, z10.s, z15.s
 .*:	4454edea 	uzpq2	z10.h, z15.h, z20.h
+.*:	4400e000 	zipq1	z0.b, z0.b, z0.b
+.*:	4400e01f 	zipq1	z31.b, z0.b, z0.b
+.*:	44c0e000 	zipq1	z0.d, z0.d, z0.d
+.*:	4400e3e0 	zipq1	z0.b, z31.b, z0.b
+.*:	441fe000 	zipq1	z0.b, z0.b, z31.b
+.*:	44dfe3ff 	zipq1	z31.d, z31.d, z31.d
+.*:	448fe145 	zipq1	z5.s, z10.s, z15.s
+.*:	4454e1ea 	zipq1	z10.h, z15.h, z20.h
+.*:	4400e400 	zipq2	z0.b, z0.b, z0.b
+.*:	4400e41f 	zipq2	z31.b, z0.b, z0.b
+.*:	44c0e400 	zipq2	z0.d, z0.d, z0.d
+.*:	4400e7e0 	zipq2	z0.b, z31.b, z0.b
+.*:	441fe400 	zipq2	z0.b, z0.b, z31.b
+.*:	44dfe7ff 	zipq2	z31.d, z31.d, z31.d
+.*:	448fe545 	zipq2	z5.s, z10.s, z15.s
+.*:	4454e5ea 	zipq2	z10.h, z15.h, z20.h
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
index b8c6ed72a89..11126c35221 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -24,3 +24,21 @@  uzpq2 z0.b, z0.b, z31.b
 uzpq2 z31.d, z31.d, z31.d
 uzpq2 z5.s, z10.s, z15.s
 uzpq2 z10.h, z15.h, z20.h
+
+zipq1 z0.b, z0.b, z0.b
+zipq1 z31.b, z0.b, z0.b
+zipq1 z0.d, z0.d, z0.d
+zipq1 z0.b, z31.b, z0.b
+zipq1 z0.b, z0.b, z31.b
+zipq1 z31.d, z31.d, z31.d
+zipq1 z5.s, z10.s, z15.s
+zipq1 z10.h, z15.h, z20.h
+
+zipq2 z0.b, z0.b, z0.b
+zipq2 z31.b, z0.b, z0.b
+zipq2 z0.d, z0.d, z0.d
+zipq2 z0.b, z31.b, z0.b
+zipq2 z0.b, z0.b, z31.b
+zipq2 z31.d, z31.d, z31.d
+zipq2 z5.s, z10.s, z15.s
+zipq2 z10.h, z15.h, z20.h
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7089f167552..9832fc29485 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6645,6 +6645,8 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
   SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
   SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+  SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+  SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
 
   SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
   SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),