[v1,03/12] aarch64: Add support for sve2p1 tblq instruction.

Message ID 20240704124045.306577-4-srinath.parvathaneni@arm.com
State New
Headers
Series aarch64: Add support for remaining sve2p1 instructions. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Test failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Srinath Parvathaneni July 4, 2024, 12:40 p.m. UTC
  This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d |  3 +++
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 18 ++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s |  6 ++++++
 gas/testsuite/gas/aarch64/sve2p1-6.d         | 18 ++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-6.s         |  8 ++++++++
 opcodes/aarch64-tbl.h                        |  1 +
 6 files changed, 54 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.s
  

Patch

diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
new file mode 100644
index 00000000000..1aa2b39f857
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -0,0 +1,3 @@ 
+#name: Test of illegal SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
new file mode 100644
index 00000000000..0fea3255db4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -0,0 +1,18 @@ 
+.*: Assembler messages:
+.*: Error: operand mismatch -- `tblq z0.s,{z0.b},z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	tblq z0.b, {z0.b}, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	tblq z0.h, {z0.h}, z0.h
+.*: Info:    	tblq z0.s, {z0.s}, z0.s
+.*: Info:    	tblq z0.d, {z0.d}, z0.d
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s-z1.s},z0.s'
+.*: Error: operand mismatch -- `tblq z0.s,{z31.s},z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	tblq z0.s, {z31.s}, z0.s
+.*: Info:    other valid variant\(s\):
+.*: Info:    	tblq z0.b, {z31.b}, z0.b
+.*: Info:    	tblq z0.h, {z31.h}, z0.h
+.*: Info:    	tblq z0.d, {z31.d}, z0.d
+.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
new file mode 100644
index 00000000000..0f8300e385c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -0,0 +1,6 @@ 
+tblq z0.s, {z0.b}, z0.b
+tblq z31.b, z0.b, z0.b
+tblq z0.s, {z0.s, z1.s}, z0.s
+tblq z0.s, {z0.s - z1.s}, z0.s
+tblq z0.s, {z31.s}, z0.b
+tblq z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
new file mode 100644
index 00000000000..d146903c4a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -0,0 +1,18 @@ 
+#name: Test of SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	4400f800 	tblq	z0.b, {z0.b}, z0.b
+.*:	4400f81f 	tblq	z31.b, {z0.b}, z0.b
+.*:	44c0f800 	tblq	z0.d, {z0.d}, z0.d
+.*:	4400fbe0 	tblq	z0.b, {z31.b}, z0.b
+.*:	441ff800 	tblq	z0.b, {z0.b}, z31.b
+.*:	44dffbff 	tblq	z31.d, {z31.d}, z31.d
+.*:	444ff945 	tblq	z5.h, {z10.h}, z15.h
+.*:	4487f861 	tblq	z1.s, {z3.s}, z7.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
new file mode 100644
index 00000000000..d2a0ef5fedf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -0,0 +1,8 @@ 
+tblq z0.b, {z0.b}, z0.b
+tblq z31.b, {z0.b}, z0.b
+tblq z0.d, {z0.d}, z0.d
+tblq z0.b, {z31.b}, z0.b
+tblq z0.b, {z0.b}, z31.b
+tblq z31.d, {z31.d}, z31.d
+tblq z5.h, {z10.h}, z15.h
+tblq z1.s, {z3.s}, z7.s
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 81b23b3f369..56a6c9d6e82 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6641,6 +6641,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
   SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+  SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
   SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
 
   SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),