new file mode 100644
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-6-invalid.l
new file mode 100644
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `tblq z0.s,{z0.b},z0.b'
+.*: Info: did you mean this\?
+.*: Info: tblq z0.b, {z0.b}, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: tblq z0.h, {z0.h}, z0.h
+.*: Info: tblq z0.s, {z0.s}, z0.s
+.*: Info: tblq z0.d, {z0.d}, z0.d
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s-z1.s},z0.s'
+.*: Error: operand mismatch -- `tblq z0.s,{z31.s},z0.b'
+.*: Info: did you mean this\?
+.*: Info: tblq z0.s, {z31.s}, z0.s
+.*: Info: other valid variant\(s\):
+.*: Info: tblq z0.b, {z31.b}, z0.b
+.*: Info: tblq z0.h, {z31.h}, z0.h
+.*: Info: tblq z0.d, {z31.d}, z0.d
+.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
new file mode 100644
@@ -0,0 +1,6 @@
+tblq z0.s, {z0.b}, z0.b
+tblq z31.b, z0.b, z0.b
+tblq z0.s, {z0.s, z1.s}, z0.s
+tblq z0.s, {z0.s - z1.s}, z0.s
+tblq z0.s, {z31.s}, z0.b
+tblq z0.b, {z0.b}, {z31.b}
new file mode 100644
@@ -0,0 +1,18 @@
+#name: Test of SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 4400f800 tblq z0.b, {z0.b}, z0.b
+.*: 4400f81f tblq z31.b, {z0.b}, z0.b
+.*: 44c0f800 tblq z0.d, {z0.d}, z0.d
+.*: 4400fbe0 tblq z0.b, {z31.b}, z0.b
+.*: 441ff800 tblq z0.b, {z0.b}, z31.b
+.*: 44dffbff tblq z31.d, {z31.d}, z31.d
+.*: 444ff945 tblq z5.h, {z10.h}, z15.h
+.*: 4487f861 tblq z1.s, {z3.s}, z7.s
new file mode 100644
@@ -0,0 +1,8 @@
+tblq z0.b, {z0.b}, z0.b
+tblq z31.b, {z0.b}, z0.b
+tblq z0.d, {z0.d}, z0.d
+tblq z0.b, {z31.b}, z0.b
+tblq z0.b, {z0.b}, z31.b
+tblq z31.d, {z31.d}, z31.d
+tblq z5.h, {z10.h}, z15.h
+tblq z1.s, {z3.s}, z7.s
@@ -6641,6 +6641,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),