[v1,01/12] aarch64: Add support for sve2p1 orqv instruction.

Message ID 20240704124045.306577-2-srinath.parvathaneni@arm.com
State New
Headers
Series aarch64: Add support for remaining sve2p1 instructions. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Test failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Srinath Parvathaneni July 4, 2024, 12:40 p.m. UTC
  This patch adds support for SVE2p1 "orqv" instruction, spec available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
 gas/testsuite/gas/aarch64/sve2p1-5-invalid.d |  3 +++
 gas/testsuite/gas/aarch64/sve2p1-5-invalid.l | 27 ++++++++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-5-invalid.s |  8 ++++++
 gas/testsuite/gas/aarch64/sve2p1-5.d         | 18 +++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-5.s         |  8 ++++++
 opcodes/aarch64-tbl.h                        |  1 +
 6 files changed, 65 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.s
  

Patch

diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
new file mode 100644
index 00000000000..d28b059b244
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
@@ -0,0 +1,3 @@ 
+#name: Test of illegal SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-5-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
new file mode 100644
index 00000000000..4cd75025da9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
@@ -0,0 +1,27 @@ 
+.*: Assembler messages:
+.*: Error: operand mismatch -- `orqv v0.8h,p0,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.16b, p0, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.8h, p0, z0.h
+.*: Info:    	orqv v0.4s, p0, z0.s
+.*: Info:    	orqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `orqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `orqv v0.2d,p7,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.16b, p7, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.8h, p7, z0.h
+.*: Info:    	orqv v0.4s, p7, z0.s
+.*: Info:    	orqv v0.2d, p7, z0.d
+.*: Error: bad vector arrangement type at operand 1 -- `orqv v0.2b,p7,z0.b'
+.*: Error: indexed vector register expected at operand 1 -- `orqv v0.b,p0,z0.16b'
+.*: Error: unexpected character `8' in element size at operand 3 -- `orqv v0.4h,p0,z0.8h'
+.*: Error: unexpected character `4' in element size at operand 3 -- `orqv v0.4s,p8/m,z0.4s'
+.*: Error: operand mismatch -- `orqv v0.2d,p0/z,z0.d'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.2d, p0, z0.d
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.16b, p0, z0.b
+.*: Info:    	orqv v0.8h, p0, z0.h
+.*: Info:    	orqv v0.4s, p0, z0.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
new file mode 100644
index 00000000000..36edb878433
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
@@ -0,0 +1,8 @@ 
+orqv v0.8h, p0, z0.b
+orqv v31.16b, p8, z0.b
+orqv v0.2d, p7, z0.b
+orqv v0.2b, p7, z0.b
+orqv v0.b, p0, z0.16b
+orqv v0.4h, p0, z0.8h
+orqv v0.4s, p8/m, z0.4s
+orqv v0.2d, p0/z, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.d b/gas/testsuite/gas/aarch64/sve2p1-5.d
new file mode 100644
index 00000000000..f581e345f58
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.d
@@ -0,0 +1,18 @@ 
+#name: Test of SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	041c2000 	orqv	v0.16b, p0, z0.b
+.*:	041c201f 	orqv	v31.16b, p0, z0.b
+.*:	04dc2000 	orqv	v0.2d, p0, z0.d
+.*:	041c3c00 	orqv	v0.16b, p7, z0.b
+.*:	041c23e0 	orqv	v0.16b, p0, z31.b
+.*:	04dc3fff 	orqv	v31.2d, p7, z31.d
+.*:	045c35ef 	orqv	v15.8h, p5, z15.h
+.*:	049c2e8a 	orqv	v10.4s, p3, z20.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.s b/gas/testsuite/gas/aarch64/sve2p1-5.s
new file mode 100644
index 00000000000..12f0b859751
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.s
@@ -0,0 +1,8 @@ 
+orqv v0.16b, p0, z0.b
+orqv v31.16b, p0, z0.b
+orqv v0.2d, p0, z0.d
+orqv v0.16b, p7, z0.b
+orqv v0.16b, p0, z31.b
+orqv v31.2d, p7, z31.d
+orqv v15.8h, p5, z15.h
+orqv v10.4s, p3, z20.s
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7ef9cea9119..81b23b3f369 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6640,6 +6640,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
+  SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
   SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
 
   SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),