[v1,09/12] aarch64: Add support for sve2p1 tbxq instruction.

Message ID 20240704124045.306577-10-srinath.parvathaneni@arm.com
State New
Headers
Series aarch64: Add support for remaining sve2p1 instructions. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
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Commit Message

Srinath Parvathaneni July 4, 2024, 12:40 p.m. UTC
  This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d |  2 +-
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 12 ++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s |  6 ++++++
 gas/testsuite/gas/aarch64/sve2p1-6.d         | 10 +++++++++-
 gas/testsuite/gas/aarch64/sve2p1-6.s         |  9 +++++++++
 opcodes/aarch64-tbl.h                        |  1 +
 6 files changed, 38 insertions(+), 2 deletions(-)
  

Patch

diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
index db35ae7acb3..437f810868d 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -1,3 +1,3 @@ 
-#name: Test of illegal SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
+#name: Test of illegal SVE2.1 tblq, tbxq, uzpq[1-2] and zipq[1-2] instruction.
 #as: -march=armv9.4-a
 #error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
index 55987acc8b0..f37a3a0df9f 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -16,6 +16,18 @@ 
 .*: Info:    	tblq z0.h, {z31.h}, z0.h
 .*: Info:    	tblq z0.d, {z31.d}, z0.d
 .*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `tbxq z31.s,z0.b,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	tbxq z31.b, z0.b, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	tbxq z31.h, z0.h, z0.h
+.*: Info:    	tbxq z31.s, z0.s, z0.s
+.*: Info:    	tbxq z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.h,{z0.h-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `tbxq {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.b,{z0.b},{z31.b}'
 .*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.b},z0.b'
 .*: Error: operand mismatch -- `uzpq1 z31.s,z0.b,z0.h'
 .*: Info:    did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
index f79dfac78d4..7d3209e5293 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -4,6 +4,12 @@  tblq z0.s, {z0.s, z1.s}, z0.s
 tblq z0.s, {z0.s - z1.s}, z0.s
 tblq z0.s, {z31.s}, z0.b
 tblq z0.b, {z0.b}, {z31.b}
+tbxq z0.s, {z0.b}, z0.b
+tbxq z31.s, z0.b, z0.h
+tbxq z0.s, {z0.s, z1.s}, z0.s
+tbxq z0.h, {z0.h - z1.h}, z0.h
+tbxq {z0.s}, z31.s, z0.b
+tbxq z0.b, {z0.b}, {z31.b}
 uzpq1 z0.s, {z0.b}, z0.b
 uzpq1 z31.s, z0.b, z0.h
 uzpq1 z0.s, {z0.s, z1.s}, z0.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index 83ba1426135..42d1ee41e99 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,4 +1,4 @@ 
-#name: Test of SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
+#name: Test of SVE2.1 tblq, tbxq, uzpq[1-2] and zipq[1-2] instruction.
 #as: -march=armv9.4-a
 #objdump: -dr
 
@@ -16,6 +16,14 @@ 
 .*:	44dffbff 	tblq	z31.d, {z31.d}, z31.d
 .*:	444ff945 	tblq	z5.h, {z10.h}, z15.h
 .*:	4487f861 	tblq	z1.s, {z3.s}, z7.s
+.*:	05203400 	tbxq	z0.b, z0.b, z0.b
+.*:	0520341f 	tbxq	z31.b, z0.b, z0.b
+.*:	05e03400 	tbxq	z0.d, z0.d, z0.d
+.*:	052037e0 	tbxq	z0.b, z31.b, z0.b
+.*:	053f3400 	tbxq	z0.b, z0.b, z31.b
+.*:	05ff37ff 	tbxq	z31.d, z31.d, z31.d
+.*:	05af3545 	tbxq	z5.s, z10.s, z15.s
+.*:	057435ea 	tbxq	z10.h, z15.h, z20.h
 .*:	4400e800 	uzpq1	z0.b, z0.b, z0.b
 .*:	4400e81f 	uzpq1	z31.b, z0.b, z0.b
 .*:	44c0e800 	uzpq1	z0.d, z0.d, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
index 11126c35221..f61cd82e1b3 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -7,6 +7,15 @@  tblq z31.d, {z31.d}, z31.d
 tblq z5.h, {z10.h}, z15.h
 tblq z1.s, {z3.s}, z7.s
 
+tbxq z0.b, z0.b, z0.b
+tbxq z31.b, z0.b, z0.b
+tbxq z0.d, z0.d, z0.d
+tbxq z0.b, z31.b, z0.b
+tbxq z0.b, z0.b, z31.b
+tbxq z31.d, z31.d, z31.d
+tbxq z5.s, z10.s, z15.s
+tbxq z10.h, z15.h, z20.h
+
 uzpq1 z0.b, z0.b, z0.b
 uzpq1 z31.b, z0.b, z0.b
 uzpq1 z0.d, z0.d, z0.d
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9832fc29485..0bd2cc0c34b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6642,6 +6642,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
   SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
   SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
+  SVE2p1_INSN("tbxq",0x05203400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
   SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
   SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
   SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),