diff mbox series

[3/3] x86: Add aliases for CTEST and {EVEX} TEST.

Message ID 20240704085255.3279875-4-lili.cui@intel.com
State New
Headers
Series Add {load}/{store} tests for apx instructions |

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Commit Message

Cui, Lili July 4, 2024, 8:52 a.m. UTC 
  Since both operands of TEST are src, legacy TEST added an alias to support swapping operands. Now similar support is added to CTEST and {EVEX} TEST.

Added 'ctestb (%eax), %ecx' as an alias for 'ctestb %ecx, (%eax)'

Added '{evex} test (%eax), %ecx' as an alias for '{evex} test %ecx, (%eax)'

gas/ChangeLog:

        * testsuite/gas/i386/x86-64-pseudos-apx.d: Added tests for 'ctest' and
        '{evex} test'.
        * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.

opcodes/ChangeLog:

        * i386-opc.tbl: Added aliases for 'ctest' and '{evex} test'
---
 gas/testsuite/gas/i386/x86-64-pseudos-apx.d | 10 ++++++++++
 gas/testsuite/gas/i386/x86-64-pseudos-apx.s |  4 ++--
 opcodes/i386-opc.tbl                        |  6 ++++--
 3 files changed, 16 insertions(+), 4 deletions(-)

Comments

Jan Beulich July 4, 2024, 11:49 a.m. UTC | #1 
On 04.07.2024 10:52, Cui, Lili wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -357,10 +357,12 @@ ccmp<scc>, 0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|I
>  test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
>  test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +test, 0x840a, 0, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +test, 0x840a, 0, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
>  test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  
> -ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ctest<scc>, 0x840<scc:opc>, APX_F, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ctest<scc>, 0x840<scc:opc>, APX_F, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
>  ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

Hmm, no - rather than dropping D and yet further increasing the number of
templates, the D should actually be made work. I can certainly take a look
myself, if you prefer.

Jan
Cui, Lili July 5, 2024, 2:47 a.m. UTC | #2 
> On 04.07.2024 10:52, Cui, Lili wrote:
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -357,10 +357,12 @@ ccmp<scc>, 0x800<scc:opc>/7, APX_F,
> > W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|I  test, 0x84, 0,
> > D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  test, 0xa8, 0,
> > W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S,
> > Acc|Byte|Word|Dword|Qword }  test, 0xf6/0, 0,
> > W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -test, 0x840a, 0,
> > D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +test, 0x840a, 0, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf,
> {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +} test, 0x840a, 0,
> W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64
> > +}
> >  test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf|Optimize, {
> > Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > }
> >
> > -ctest<scc>, 0x840<scc:opc>, APX_F,
> > D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +ctest<scc>, 0x840<scc:opc>, APX_F,
> > +W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +} ctest<scc>, 0x840<scc:opc>, APX_F,
> > +W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64
> > +}
> >  ctest<scc>, 0xf60<scc:opc>/0, APX_F,
> > W|Modrm|EVexMap4|Scc|No_sSuf|Optimize,
> { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> 
> Hmm, no - rather than dropping D and yet further increasing the number of
> templates, the D should actually be made work. I can certainly take a look
> myself, if you prefer.
> 

I tried changing the first "else if" back to the original "is_cpu (t, CpuAPX_F) && i.operands == 3" and adding more conditions to the second 'else if', but I think this is probably not the style you want. If you can help, I will be very grateful.

              else if (t->opcode_space == SPACE_EVEXMAP4
                       && t->opcode_modifier.w)
                {
                  found_reverse_match = Opcode_D;
                  goto check_operands_345;
                }
              else if (t->opcode_space != SPACE_BASE
                       && (t->opcode_space != SPACE_0F
                           /* MOV to/from CR/DR/TR, as an exception, follow
                              the base opcode space encoding model.  */
                           || (t->base_opcode | 7) != 0x27))
                found_reverse_match = (t->base_opcode & 0xee) != 0x6e
                                      ? Opcode_ExtD : Opcode_SIMD_IntD;
              else if (!t->opcode_modifier.commutative)
                found_reverse_match = Opcode_D;
              else
                found_reverse_match = ~0;

Thanks,
Lili.
diff mbox series

Patch

diff --git a/gas/testsuite/gas/i386/x86-64-pseudos-apx.d b/gas/testsuite/gas/i386/x86-64-pseudos-apx.d
index 1f8cd2b413e..feb18b01878 100644
--- a/gas/testsuite/gas/i386/x86-64-pseudos-apx.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos-apx.d
@@ -105,6 +105,11 @@  Disassembly of section \.text:
 [	 ]*[a-f0-9]+:[	 ]*62 dc 04 0a 39 cf[	 ]+ccmptl \{dfv=\} %ecx,%r31d
 [	 ]*[a-f0-9]+:[	 ]*67 62 64 04 0a 3b 39[	 ]+ccmptl \{dfv=\} \(%ecx\),%r31d
 [	 ]*[a-f0-9]+:[	 ]*67 62 64 04 0a 39 39[	 ]+ccmptl \{dfv=\} %r31d,\(%ecx\)
+[	 ]*[a-f0-9]+:[	 ]*62 dc 04 0a 85 cf[	 ]+ctesttl \{dfv=\} %ecx,%r31d
+[	 ]*[a-f0-9]+:[	 ]*62 dc 04 0a 85 cf[	 ]+ctesttl \{dfv=\} %ecx,%r31d
+[	 ]*[a-f0-9]+:[	 ]*62 dc 04 0a 85 cf[	 ]+ctesttl \{dfv=\} %ecx,%r31d
+[	 ]*[a-f0-9]+:[	 ]*67 62 64 04 0a 85 39[	 ]+ctesttl \{dfv=\} %r31d,\(%ecx\)
+[	 ]*[a-f0-9]+:[	 ]*67 62 64 04 0a 85 39[	 ]+ctesttl \{dfv=\} %r31d,\(%ecx\)
 [	 ]*[a-f0-9]+:[	 ]*62 dc 7c 18 01 cf[	 ]+addl   %ecx,%r31d,%eax
 [	 ]*[a-f0-9]+:[	 ]*62 64 7c 18 03 f9[	 ]+addl.s %ecx,%r31d,%eax
 [	 ]*[a-f0-9]+:[	 ]*62 dc 7c 18 01 cf[	 ]+addl   %ecx,%r31d,%eax
@@ -164,4 +169,9 @@  Disassembly of section \.text:
 [	 ]*[a-f0-9]+:[	 ]*62 f4 04 02 39 d0[	 ]+ccmpbl \{dfv=\} %edx,%eax
 [	 ]*[a-f0-9]+:[	 ]*67 62 f4 04 02 3b 02[	 ]+ccmpbl \{dfv=\} \(%edx\),%eax
 [	 ]*[a-f0-9]+:[	 ]*67 62 f4 04 02 39 02[	 ]+ccmpbl \{dfv=\} %eax,\(%edx\)
+[	 ]*[a-f0-9]+:[	 ]*62 f4 04 02 85 d0[	 ]+ctestbl \{dfv=\} %edx,%eax
+[	 ]*[a-f0-9]+:[	 ]*62 f4 04 02 85 d0[	 ]+ctestbl \{dfv=\} %edx,%eax
+[	 ]*[a-f0-9]+:[	 ]*62 f4 04 02 85 d0[	 ]+ctestbl \{dfv=\} %edx,%eax
+[	 ]*[a-f0-9]+:[	 ]*67 62 f4 04 02 85 02[	 ]+ctestbl \{dfv=\} %eax,\(%edx\)
+[	 ]*[a-f0-9]+:[	 ]*67 62 f4 04 02 85 02[	 ]+ctestbl \{dfv=\} %eax,\(%edx\)
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-pseudos-apx.s b/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
index 592c20315d1..fa9b8f4e4df 100644
--- a/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
@@ -16,7 +16,7 @@  _start:
         {store} movaps %xmm2, (%r31)
 
         #APX EVEX promoted from legacy
-        .irp m, adc, add, and, or, sbb, sub, xor, cmp
+        .irp m, adc, add, and, or, sbb, sub, xor, cmp, test
         {evex}         \m %ecx, %r31d
         {evex} {load}  \m %ecx, %r31d
         {evex} {store} \m %ecx, %r31d
@@ -36,7 +36,7 @@  _start:
         .endr
 
         #APX News.
-        .irp m, cfcmovb, ccmpb
+        .irp m, cfcmovb, ccmpb, ctestb
         \m %edx, %eax
         {load}  \m %edx, %eax
         {store} \m %edx, %eax
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 8c0d93402b5..7609763d630 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -357,10 +357,12 @@  ccmp<scc>, 0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|I
 test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0x840a, 0, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0x840a, 0, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
-ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0x840<scc:opc>, APX_F, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0x840<scc:opc>, APX_F, W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 <scc>